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25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/stringify.h>
28#include <linux/kernel.h>
29#include <linux/sched/signal.h>
30#include <linux/types.h>
31#include <linux/compiler.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/in.h>
35#include <linux/interrupt.h>
36#include <linux/ioport.h>
37#include <linux/pci.h>
38#include <linux/netdevice.h>
39#include <linux/etherdevice.h>
40#include <linux/skbuff.h>
41#include <linux/ethtool.h>
42#include <linux/mdio.h>
43#include <linux/mii.h>
44#include <linux/phy.h>
45#include <linux/brcmphy.h>
46#include <linux/if.h>
47#include <linux/if_vlan.h>
48#include <linux/ip.h>
49#include <linux/tcp.h>
50#include <linux/workqueue.h>
51#include <linux/prefetch.h>
52#include <linux/dma-mapping.h>
53#include <linux/firmware.h>
54#include <linux/ssb/ssb_driver_gige.h>
55#include <linux/hwmon.h>
56#include <linux/hwmon-sysfs.h>
57#include <linux/crc32poly.h>
58
59#include <net/checksum.h>
60#include <net/ip.h>
61
62#include <linux/io.h>
63#include <asm/byteorder.h>
64#include <linux/uaccess.h>
65
66#include <uapi/linux/net_tstamp.h>
67#include <linux/ptp_clock_kernel.h>
68
69#define BAR_0 0
70#define BAR_2 2
71
72#include "tg3.h"
73
74
75
76static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
77{
78 return test_bit(flag, bits);
79}
80
81static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
82{
83 set_bit(flag, bits);
84}
85
86static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
87{
88 clear_bit(flag, bits);
89}
90
91#define tg3_flag(tp, flag) \
92 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
93#define tg3_flag_set(tp, flag) \
94 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
95#define tg3_flag_clear(tp, flag) \
96 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
97
98#define DRV_MODULE_NAME "tg3"
99
100#define TG3_MAJ_NUM 3
101#define TG3_MIN_NUM 137
102
103#define RESET_KIND_SHUTDOWN 0
104#define RESET_KIND_INIT 1
105#define RESET_KIND_SUSPEND 2
106
107#define TG3_DEF_RX_MODE 0
108#define TG3_DEF_TX_MODE 0
109#define TG3_DEF_MSG_ENABLE \
110 (NETIF_MSG_DRV | \
111 NETIF_MSG_PROBE | \
112 NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | \
114 NETIF_MSG_IFDOWN | \
115 NETIF_MSG_IFUP | \
116 NETIF_MSG_RX_ERR | \
117 NETIF_MSG_TX_ERR)
118
119#define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120
121
122
123
124
125#define TG3_TX_TIMEOUT (5 * HZ)
126
127
128#define TG3_MIN_MTU ETH_ZLEN
129#define TG3_MAX_MTU(tp) \
130 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131
132
133
134
135
136#define TG3_RX_STD_RING_SIZE(tp) \
137 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
138 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
139#define TG3_DEF_RX_RING_PENDING 200
140#define TG3_RX_JMB_RING_SIZE(tp) \
141 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
142 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
143#define TG3_DEF_RX_JUMBO_RING_PENDING 100
144
145
146
147
148
149
150
151
152#define TG3_TX_RING_SIZE 512
153#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154
155#define TG3_RX_STD_RING_BYTES(tp) \
156 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
157#define TG3_RX_JMB_RING_BYTES(tp) \
158 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
159#define TG3_RX_RCB_RING_BYTES(tp) \
160 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
161#define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 TG3_TX_RING_SIZE)
163#define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164
165#define TG3_DMA_BYTE_ENAB 64
166
167#define TG3_RX_STD_DMA_SZ 1536
168#define TG3_RX_JMB_DMA_SZ 9046
169
170#define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171
172#define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
173#define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174
175#define TG3_RX_STD_BUFF_RING_SIZE(tp) \
176 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177
178#define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
179 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180
181
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183
184
185
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188
189
190
191
192#define TG3_RX_COPY_THRESHOLD 256
193#if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
194 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195#else
196 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
197#endif
198
199#if (NET_IP_ALIGN != 0)
200#define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201#else
202#define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
203#endif
204
205
206#define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
207#define TG3_TX_BD_DMA_MAX_2K 2048
208#define TG3_TX_BD_DMA_MAX_4K 4096
209
210#define TG3_RAW_IP_ALIGN 2
211
212#define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
213#define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214
215#define TG3_FW_UPDATE_TIMEOUT_SEC 5
216#define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217
218#define FIRMWARE_TG3 "tigon/tg3.bin"
219#define FIRMWARE_TG357766 "tigon/tg357766.bin"
220#define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
221#define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222
223MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
224MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
225MODULE_LICENSE("GPL");
226MODULE_FIRMWARE(FIRMWARE_TG3);
227MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
229
230static int tg3_debug = -1;
231module_param(tg3_debug, int, 0);
232MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
233
234#define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235#define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
236
237static const struct pci_device_id tg3_pci_tbl[] = {
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
345 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
346 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
347 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
348 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
349 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
351 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
352 {PCI_DEVICE(0x10cf, 0x11a2)},
353 {}
354};
355
356MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
357
358static const struct {
359 const char string[ETH_GSTRING_LEN];
360} ethtool_stats_keys[] = {
361 { "rx_octets" },
362 { "rx_fragments" },
363 { "rx_ucast_packets" },
364 { "rx_mcast_packets" },
365 { "rx_bcast_packets" },
366 { "rx_fcs_errors" },
367 { "rx_align_errors" },
368 { "rx_xon_pause_rcvd" },
369 { "rx_xoff_pause_rcvd" },
370 { "rx_mac_ctrl_rcvd" },
371 { "rx_xoff_entered" },
372 { "rx_frame_too_long_errors" },
373 { "rx_jabbers" },
374 { "rx_undersize_packets" },
375 { "rx_in_length_errors" },
376 { "rx_out_length_errors" },
377 { "rx_64_or_less_octet_packets" },
378 { "rx_65_to_127_octet_packets" },
379 { "rx_128_to_255_octet_packets" },
380 { "rx_256_to_511_octet_packets" },
381 { "rx_512_to_1023_octet_packets" },
382 { "rx_1024_to_1522_octet_packets" },
383 { "rx_1523_to_2047_octet_packets" },
384 { "rx_2048_to_4095_octet_packets" },
385 { "rx_4096_to_8191_octet_packets" },
386 { "rx_8192_to_9022_octet_packets" },
387
388 { "tx_octets" },
389 { "tx_collisions" },
390
391 { "tx_xon_sent" },
392 { "tx_xoff_sent" },
393 { "tx_flow_control" },
394 { "tx_mac_errors" },
395 { "tx_single_collisions" },
396 { "tx_mult_collisions" },
397 { "tx_deferred" },
398 { "tx_excessive_collisions" },
399 { "tx_late_collisions" },
400 { "tx_collide_2times" },
401 { "tx_collide_3times" },
402 { "tx_collide_4times" },
403 { "tx_collide_5times" },
404 { "tx_collide_6times" },
405 { "tx_collide_7times" },
406 { "tx_collide_8times" },
407 { "tx_collide_9times" },
408 { "tx_collide_10times" },
409 { "tx_collide_11times" },
410 { "tx_collide_12times" },
411 { "tx_collide_13times" },
412 { "tx_collide_14times" },
413 { "tx_collide_15times" },
414 { "tx_ucast_packets" },
415 { "tx_mcast_packets" },
416 { "tx_bcast_packets" },
417 { "tx_carrier_sense_errors" },
418 { "tx_discards" },
419 { "tx_errors" },
420
421 { "dma_writeq_full" },
422 { "dma_write_prioq_full" },
423 { "rxbds_empty" },
424 { "rx_discards" },
425 { "rx_errors" },
426 { "rx_threshold_hit" },
427
428 { "dma_readq_full" },
429 { "dma_read_prioq_full" },
430 { "tx_comp_queue_full" },
431
432 { "ring_set_send_prod_index" },
433 { "ring_status_update" },
434 { "nic_irqs" },
435 { "nic_avoided_irqs" },
436 { "nic_tx_threshold_hit" },
437
438 { "mbuf_lwm_thresh_hit" },
439};
440
441#define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
442#define TG3_NVRAM_TEST 0
443#define TG3_LINK_TEST 1
444#define TG3_REGISTER_TEST 2
445#define TG3_MEMORY_TEST 3
446#define TG3_MAC_LOOPB_TEST 4
447#define TG3_PHY_LOOPB_TEST 5
448#define TG3_EXT_LOOPB_TEST 6
449#define TG3_INTERRUPT_TEST 7
450
451
452static const struct {
453 const char string[ETH_GSTRING_LEN];
454} ethtool_test_keys[] = {
455 [TG3_NVRAM_TEST] = { "nvram test (online) " },
456 [TG3_LINK_TEST] = { "link test (online) " },
457 [TG3_REGISTER_TEST] = { "register test (offline)" },
458 [TG3_MEMORY_TEST] = { "memory test (offline)" },
459 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
460 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
461 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
462 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
463};
464
465#define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
466
467
468static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
469{
470 writel(val, tp->regs + off);
471}
472
473static u32 tg3_read32(struct tg3 *tp, u32 off)
474{
475 return readl(tp->regs + off);
476}
477
478static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
479{
480 writel(val, tp->aperegs + off);
481}
482
483static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
484{
485 return readl(tp->aperegs + off);
486}
487
488static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
489{
490 unsigned long flags;
491
492 spin_lock_irqsave(&tp->indirect_lock, flags);
493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
495 spin_unlock_irqrestore(&tp->indirect_lock, flags);
496}
497
498static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
499{
500 writel(val, tp->regs + off);
501 readl(tp->regs + off);
502}
503
504static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
505{
506 unsigned long flags;
507 u32 val;
508
509 spin_lock_irqsave(&tp->indirect_lock, flags);
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
512 spin_unlock_irqrestore(&tp->indirect_lock, flags);
513 return val;
514}
515
516static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
517{
518 unsigned long flags;
519
520 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
522 TG3_64BIT_REG_LOW, val);
523 return;
524 }
525 if (off == TG3_RX_STD_PROD_IDX_REG) {
526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
527 TG3_64BIT_REG_LOW, val);
528 return;
529 }
530
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
535
536
537
538
539 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
540 (val == 0x1)) {
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
543 }
544}
545
546static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
547{
548 unsigned long flags;
549 u32 val;
550
551 spin_lock_irqsave(&tp->indirect_lock, flags);
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
555 return val;
556}
557
558
559
560
561
562
563static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
564{
565 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
566
567 tp->write32(tp, off, val);
568 else {
569
570 tg3_write32(tp, off, val);
571 if (usec_wait)
572 udelay(usec_wait);
573 tp->read32(tp, off);
574 }
575
576
577
578 if (usec_wait)
579 udelay(usec_wait);
580}
581
582static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
583{
584 tp->write32_mbox(tp, off, val);
585 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
586 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
587 !tg3_flag(tp, ICH_WORKAROUND)))
588 tp->read32_mbox(tp, off);
589}
590
591static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
592{
593 void __iomem *mbox = tp->regs + off;
594 writel(val, mbox);
595 if (tg3_flag(tp, TXD_MBOX_HWBUG))
596 writel(val, mbox);
597 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
598 tg3_flag(tp, FLUSH_POSTED_WRITES))
599 readl(mbox);
600}
601
602static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
603{
604 return readl(tp->regs + off + GRCMBOX_BASE);
605}
606
607static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
608{
609 writel(val, tp->regs + off + GRCMBOX_BASE);
610}
611
612#define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
613#define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
614#define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615#define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616#define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
617
618#define tw32(reg, val) tp->write32(tp, reg, val)
619#define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
620#define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
621#define tr32(reg) tp->read32(tp, reg)
622
623static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
624{
625 unsigned long flags;
626
627 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
628 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
629 return;
630
631 spin_lock_irqsave(&tp->indirect_lock, flags);
632 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
635
636
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
638 } else {
639 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
640 tw32_f(TG3PCI_MEM_WIN_DATA, val);
641
642
643 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
644 }
645 spin_unlock_irqrestore(&tp->indirect_lock, flags);
646}
647
648static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
649{
650 unsigned long flags;
651
652 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
653 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
654 *val = 0;
655 return;
656 }
657
658 spin_lock_irqsave(&tp->indirect_lock, flags);
659 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
662
663
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
665 } else {
666 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
667 *val = tr32(TG3PCI_MEM_WIN_DATA);
668
669
670 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
671 }
672 spin_unlock_irqrestore(&tp->indirect_lock, flags);
673}
674
675static void tg3_ape_lock_init(struct tg3 *tp)
676{
677 int i;
678 u32 regbase, bit;
679
680 if (tg3_asic_rev(tp) == ASIC_REV_5761)
681 regbase = TG3_APE_LOCK_GRANT;
682 else
683 regbase = TG3_APE_PER_LOCK_GRANT;
684
685
686 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
687 switch (i) {
688 case TG3_APE_LOCK_PHY0:
689 case TG3_APE_LOCK_PHY1:
690 case TG3_APE_LOCK_PHY2:
691 case TG3_APE_LOCK_PHY3:
692 bit = APE_LOCK_GRANT_DRIVER;
693 break;
694 default:
695 if (!tp->pci_fn)
696 bit = APE_LOCK_GRANT_DRIVER;
697 else
698 bit = 1 << tp->pci_fn;
699 }
700 tg3_ape_write32(tp, regbase + 4 * i, bit);
701 }
702
703}
704
705static int tg3_ape_lock(struct tg3 *tp, int locknum)
706{
707 int i, off;
708 int ret = 0;
709 u32 status, req, gnt, bit;
710
711 if (!tg3_flag(tp, ENABLE_APE))
712 return 0;
713
714 switch (locknum) {
715 case TG3_APE_LOCK_GPIO:
716 if (tg3_asic_rev(tp) == ASIC_REV_5761)
717 return 0;
718 fallthrough;
719 case TG3_APE_LOCK_GRC:
720 case TG3_APE_LOCK_MEM:
721 if (!tp->pci_fn)
722 bit = APE_LOCK_REQ_DRIVER;
723 else
724 bit = 1 << tp->pci_fn;
725 break;
726 case TG3_APE_LOCK_PHY0:
727 case TG3_APE_LOCK_PHY1:
728 case TG3_APE_LOCK_PHY2:
729 case TG3_APE_LOCK_PHY3:
730 bit = APE_LOCK_REQ_DRIVER;
731 break;
732 default:
733 return -EINVAL;
734 }
735
736 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
737 req = TG3_APE_LOCK_REQ;
738 gnt = TG3_APE_LOCK_GRANT;
739 } else {
740 req = TG3_APE_PER_LOCK_REQ;
741 gnt = TG3_APE_PER_LOCK_GRANT;
742 }
743
744 off = 4 * locknum;
745
746 tg3_ape_write32(tp, req + off, bit);
747
748
749 for (i = 0; i < 100; i++) {
750 status = tg3_ape_read32(tp, gnt + off);
751 if (status == bit)
752 break;
753 if (pci_channel_offline(tp->pdev))
754 break;
755
756 udelay(10);
757 }
758
759 if (status != bit) {
760
761 tg3_ape_write32(tp, gnt + off, bit);
762 ret = -EBUSY;
763 }
764
765 return ret;
766}
767
768static void tg3_ape_unlock(struct tg3 *tp, int locknum)
769{
770 u32 gnt, bit;
771
772 if (!tg3_flag(tp, ENABLE_APE))
773 return;
774
775 switch (locknum) {
776 case TG3_APE_LOCK_GPIO:
777 if (tg3_asic_rev(tp) == ASIC_REV_5761)
778 return;
779 fallthrough;
780 case TG3_APE_LOCK_GRC:
781 case TG3_APE_LOCK_MEM:
782 if (!tp->pci_fn)
783 bit = APE_LOCK_GRANT_DRIVER;
784 else
785 bit = 1 << tp->pci_fn;
786 break;
787 case TG3_APE_LOCK_PHY0:
788 case TG3_APE_LOCK_PHY1:
789 case TG3_APE_LOCK_PHY2:
790 case TG3_APE_LOCK_PHY3:
791 bit = APE_LOCK_GRANT_DRIVER;
792 break;
793 default:
794 return;
795 }
796
797 if (tg3_asic_rev(tp) == ASIC_REV_5761)
798 gnt = TG3_APE_LOCK_GRANT;
799 else
800 gnt = TG3_APE_PER_LOCK_GRANT;
801
802 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
803}
804
805static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
806{
807 u32 apedata;
808
809 while (timeout_us) {
810 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
811 return -EBUSY;
812
813 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
814 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
815 break;
816
817 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
818
819 udelay(10);
820 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
821 }
822
823 return timeout_us ? 0 : -EBUSY;
824}
825
826#ifdef CONFIG_TIGON3_HWMON
827static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828{
829 u32 i, apedata;
830
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
833
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
835 break;
836
837 udelay(10);
838 }
839
840 return i == timeout_us / 10;
841}
842
843static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 len)
845{
846 int err;
847 u32 i, bufoff, msgoff, maxlen, apedata;
848
849 if (!tg3_flag(tp, APE_HAS_NCSI))
850 return 0;
851
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
854 return -ENODEV;
855
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
858 return -EAGAIN;
859
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
861 TG3_APE_SHMEM_BASE;
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
864
865 while (len) {
866 u32 length;
867
868
869 length = (len > maxlen) ? maxlen : len;
870 len -= length;
871
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
874 return -EAGAIN;
875
876
877 err = tg3_ape_event_lock(tp, 1000);
878 if (err)
879 return err;
880
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
885
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
888
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891
892 base_off += length;
893
894 if (tg3_ape_wait_for_event(tp, 30000))
895 return -EAGAIN;
896
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
900 data++;
901 }
902 }
903
904 return 0;
905}
906#endif
907
908static int tg3_ape_send_event(struct tg3 *tp, u32 event)
909{
910 int err;
911 u32 apedata;
912
913 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
914 if (apedata != APE_SEG_SIG_MAGIC)
915 return -EAGAIN;
916
917 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
918 if (!(apedata & APE_FW_STATUS_READY))
919 return -EAGAIN;
920
921
922 err = tg3_ape_event_lock(tp, 20000);
923 if (err)
924 return err;
925
926 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
927 event | APE_EVENT_STATUS_EVENT_PENDING);
928
929 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
930 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
931
932 return 0;
933}
934
935static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
936{
937 u32 event;
938 u32 apedata;
939
940 if (!tg3_flag(tp, ENABLE_APE))
941 return;
942
943 switch (kind) {
944 case RESET_KIND_INIT:
945 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
947 APE_HOST_SEG_SIG_MAGIC);
948 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
949 APE_HOST_SEG_LEN_MAGIC);
950 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
951 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
952 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
953 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
954 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
955 APE_HOST_BEHAV_NO_PHYLOCK);
956 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
957 TG3_APE_HOST_DRVR_STATE_START);
958
959 event = APE_EVENT_STATUS_STATE_START;
960 break;
961 case RESET_KIND_SHUTDOWN:
962 if (device_may_wakeup(&tp->pdev->dev) &&
963 tg3_flag(tp, WOL_ENABLE)) {
964 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
965 TG3_APE_HOST_WOL_SPEED_AUTO);
966 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
967 } else
968 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
969
970 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
971
972 event = APE_EVENT_STATUS_STATE_UNLOAD;
973 break;
974 default:
975 return;
976 }
977
978 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
979
980 tg3_ape_send_event(tp, event);
981}
982
983static void tg3_send_ape_heartbeat(struct tg3 *tp,
984 unsigned long interval)
985{
986
987 if (!tg3_flag(tp, ENABLE_APE) ||
988 time_before(jiffies, tp->ape_hb_jiffies + interval))
989 return;
990
991 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);
992 tp->ape_hb_jiffies = jiffies;
993}
994
995static void tg3_disable_ints(struct tg3 *tp)
996{
997 int i;
998
999 tw32(TG3PCI_MISC_HOST_CTRL,
1000 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
1001 for (i = 0; i < tp->irq_max; i++)
1002 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
1003}
1004
1005static void tg3_enable_ints(struct tg3 *tp)
1006{
1007 int i;
1008
1009 tp->irq_sync = 0;
1010 wmb();
1011
1012 tw32(TG3PCI_MISC_HOST_CTRL,
1013 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1014
1015 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1016 for (i = 0; i < tp->irq_cnt; i++) {
1017 struct tg3_napi *tnapi = &tp->napi[i];
1018
1019 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1020 if (tg3_flag(tp, 1SHOT_MSI))
1021 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1022
1023 tp->coal_now |= tnapi->coal_now;
1024 }
1025
1026
1027 if (!tg3_flag(tp, TAGGED_STATUS) &&
1028 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1029 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1030 else
1031 tw32(HOSTCC_MODE, tp->coal_now);
1032
1033 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1034}
1035
1036static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1037{
1038 struct tg3 *tp = tnapi->tp;
1039 struct tg3_hw_status *sblk = tnapi->hw_status;
1040 unsigned int work_exists = 0;
1041
1042
1043 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1044 if (sblk->status & SD_STATUS_LINK_CHG)
1045 work_exists = 1;
1046 }
1047
1048
1049 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1050 work_exists = 1;
1051
1052
1053 if (tnapi->rx_rcb_prod_idx &&
1054 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1055 work_exists = 1;
1056
1057 return work_exists;
1058}
1059
1060
1061
1062
1063
1064
1065static void tg3_int_reenable(struct tg3_napi *tnapi)
1066{
1067 struct tg3 *tp = tnapi->tp;
1068
1069 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1070
1071
1072
1073
1074
1075 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1076 tw32(HOSTCC_MODE, tp->coalesce_mode |
1077 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1078}
1079
1080static void tg3_switch_clocks(struct tg3 *tp)
1081{
1082 u32 clock_ctrl;
1083 u32 orig_clock_ctrl;
1084
1085 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1086 return;
1087
1088 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1089
1090 orig_clock_ctrl = clock_ctrl;
1091 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1092 CLOCK_CTRL_CLKRUN_OENABLE |
1093 0x1f);
1094 tp->pci_clock_ctrl = clock_ctrl;
1095
1096 if (tg3_flag(tp, 5705_PLUS)) {
1097 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1098 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1099 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1100 }
1101 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1102 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1103 clock_ctrl |
1104 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1105 40);
1106 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1107 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1108 40);
1109 }
1110 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1111}
1112
1113#define PHY_BUSY_LOOPS 5000
1114
1115static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 u32 *val)
1117{
1118 u32 frame_val;
1119 unsigned int loops;
1120 int ret;
1121
1122 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1123 tw32_f(MAC_MI_MODE,
1124 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1125 udelay(80);
1126 }
1127
1128 tg3_ape_lock(tp, tp->phy_ape_lock);
1129
1130 *val = 0x0;
1131
1132 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1133 MI_COM_PHY_ADDR_MASK);
1134 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1135 MI_COM_REG_ADDR_MASK);
1136 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1137
1138 tw32_f(MAC_MI_COM, frame_val);
1139
1140 loops = PHY_BUSY_LOOPS;
1141 while (loops != 0) {
1142 udelay(10);
1143 frame_val = tr32(MAC_MI_COM);
1144
1145 if ((frame_val & MI_COM_BUSY) == 0) {
1146 udelay(5);
1147 frame_val = tr32(MAC_MI_COM);
1148 break;
1149 }
1150 loops -= 1;
1151 }
1152
1153 ret = -EBUSY;
1154 if (loops != 0) {
1155 *val = frame_val & MI_COM_DATA_MASK;
1156 ret = 0;
1157 }
1158
1159 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1160 tw32_f(MAC_MI_MODE, tp->mi_mode);
1161 udelay(80);
1162 }
1163
1164 tg3_ape_unlock(tp, tp->phy_ape_lock);
1165
1166 return ret;
1167}
1168
1169static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1170{
1171 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1172}
1173
1174static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 u32 val)
1176{
1177 u32 frame_val;
1178 unsigned int loops;
1179 int ret;
1180
1181 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1182 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1183 return 0;
1184
1185 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1186 tw32_f(MAC_MI_MODE,
1187 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1188 udelay(80);
1189 }
1190
1191 tg3_ape_lock(tp, tp->phy_ape_lock);
1192
1193 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1194 MI_COM_PHY_ADDR_MASK);
1195 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1196 MI_COM_REG_ADDR_MASK);
1197 frame_val |= (val & MI_COM_DATA_MASK);
1198 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1199
1200 tw32_f(MAC_MI_COM, frame_val);
1201
1202 loops = PHY_BUSY_LOOPS;
1203 while (loops != 0) {
1204 udelay(10);
1205 frame_val = tr32(MAC_MI_COM);
1206 if ((frame_val & MI_COM_BUSY) == 0) {
1207 udelay(5);
1208 frame_val = tr32(MAC_MI_COM);
1209 break;
1210 }
1211 loops -= 1;
1212 }
1213
1214 ret = -EBUSY;
1215 if (loops != 0)
1216 ret = 0;
1217
1218 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1219 tw32_f(MAC_MI_MODE, tp->mi_mode);
1220 udelay(80);
1221 }
1222
1223 tg3_ape_unlock(tp, tp->phy_ape_lock);
1224
1225 return ret;
1226}
1227
1228static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1229{
1230 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1231}
1232
1233static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1234{
1235 int err;
1236
1237 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1238 if (err)
1239 goto done;
1240
1241 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1242 if (err)
1243 goto done;
1244
1245 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1246 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1247 if (err)
1248 goto done;
1249
1250 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1251
1252done:
1253 return err;
1254}
1255
1256static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1257{
1258 int err;
1259
1260 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1261 if (err)
1262 goto done;
1263
1264 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1265 if (err)
1266 goto done;
1267
1268 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1269 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1270 if (err)
1271 goto done;
1272
1273 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1274
1275done:
1276 return err;
1277}
1278
1279static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1280{
1281 int err;
1282
1283 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1284 if (!err)
1285 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1286
1287 return err;
1288}
1289
1290static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1291{
1292 int err;
1293
1294 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1295 if (!err)
1296 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1297
1298 return err;
1299}
1300
1301static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1302{
1303 int err;
1304
1305 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1306 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1307 MII_TG3_AUXCTL_SHDWSEL_MISC);
1308 if (!err)
1309 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1310
1311 return err;
1312}
1313
1314static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1315{
1316 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1317 set |= MII_TG3_AUXCTL_MISC_WREN;
1318
1319 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1320}
1321
1322static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1323{
1324 u32 val;
1325 int err;
1326
1327 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1328
1329 if (err)
1330 return err;
1331
1332 if (enable)
1333 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1334 else
1335 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1336
1337 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1338 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1339
1340 return err;
1341}
1342
1343static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1344{
1345 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1346 reg | val | MII_TG3_MISC_SHDW_WREN);
1347}
1348
1349static int tg3_bmcr_reset(struct tg3 *tp)
1350{
1351 u32 phy_control;
1352 int limit, err;
1353
1354
1355
1356
1357 phy_control = BMCR_RESET;
1358 err = tg3_writephy(tp, MII_BMCR, phy_control);
1359 if (err != 0)
1360 return -EBUSY;
1361
1362 limit = 5000;
1363 while (limit--) {
1364 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1365 if (err != 0)
1366 return -EBUSY;
1367
1368 if ((phy_control & BMCR_RESET) == 0) {
1369 udelay(40);
1370 break;
1371 }
1372 udelay(10);
1373 }
1374 if (limit < 0)
1375 return -EBUSY;
1376
1377 return 0;
1378}
1379
1380static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1381{
1382 struct tg3 *tp = bp->priv;
1383 u32 val;
1384
1385 spin_lock_bh(&tp->lock);
1386
1387 if (__tg3_readphy(tp, mii_id, reg, &val))
1388 val = -EIO;
1389
1390 spin_unlock_bh(&tp->lock);
1391
1392 return val;
1393}
1394
1395static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1396{
1397 struct tg3 *tp = bp->priv;
1398 u32 ret = 0;
1399
1400 spin_lock_bh(&tp->lock);
1401
1402 if (__tg3_writephy(tp, mii_id, reg, val))
1403 ret = -EIO;
1404
1405 spin_unlock_bh(&tp->lock);
1406
1407 return ret;
1408}
1409
1410static void tg3_mdio_config_5785(struct tg3 *tp)
1411{
1412 u32 val;
1413 struct phy_device *phydev;
1414
1415 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1416 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1417 case PHY_ID_BCM50610:
1418 case PHY_ID_BCM50610M:
1419 val = MAC_PHYCFG2_50610_LED_MODES;
1420 break;
1421 case PHY_ID_BCMAC131:
1422 val = MAC_PHYCFG2_AC131_LED_MODES;
1423 break;
1424 case PHY_ID_RTL8211C:
1425 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1426 break;
1427 case PHY_ID_RTL8201E:
1428 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1429 break;
1430 default:
1431 return;
1432 }
1433
1434 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1435 tw32(MAC_PHYCFG2, val);
1436
1437 val = tr32(MAC_PHYCFG1);
1438 val &= ~(MAC_PHYCFG1_RGMII_INT |
1439 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1440 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1441 tw32(MAC_PHYCFG1, val);
1442
1443 return;
1444 }
1445
1446 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1447 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1448 MAC_PHYCFG2_FMODE_MASK_MASK |
1449 MAC_PHYCFG2_GMODE_MASK_MASK |
1450 MAC_PHYCFG2_ACT_MASK_MASK |
1451 MAC_PHYCFG2_QUAL_MASK_MASK |
1452 MAC_PHYCFG2_INBAND_ENABLE;
1453
1454 tw32(MAC_PHYCFG2, val);
1455
1456 val = tr32(MAC_PHYCFG1);
1457 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1458 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1459 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1460 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1461 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1462 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1463 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1464 }
1465 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1466 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1467 tw32(MAC_PHYCFG1, val);
1468
1469 val = tr32(MAC_EXT_RGMII_MODE);
1470 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1471 MAC_RGMII_MODE_RX_QUALITY |
1472 MAC_RGMII_MODE_RX_ACTIVITY |
1473 MAC_RGMII_MODE_RX_ENG_DET |
1474 MAC_RGMII_MODE_TX_ENABLE |
1475 MAC_RGMII_MODE_TX_LOWPWR |
1476 MAC_RGMII_MODE_TX_RESET);
1477 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1478 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1479 val |= MAC_RGMII_MODE_RX_INT_B |
1480 MAC_RGMII_MODE_RX_QUALITY |
1481 MAC_RGMII_MODE_RX_ACTIVITY |
1482 MAC_RGMII_MODE_RX_ENG_DET;
1483 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1484 val |= MAC_RGMII_MODE_TX_ENABLE |
1485 MAC_RGMII_MODE_TX_LOWPWR |
1486 MAC_RGMII_MODE_TX_RESET;
1487 }
1488 tw32(MAC_EXT_RGMII_MODE, val);
1489}
1490
1491static void tg3_mdio_start(struct tg3 *tp)
1492{
1493 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1494 tw32_f(MAC_MI_MODE, tp->mi_mode);
1495 udelay(80);
1496
1497 if (tg3_flag(tp, MDIOBUS_INITED) &&
1498 tg3_asic_rev(tp) == ASIC_REV_5785)
1499 tg3_mdio_config_5785(tp);
1500}
1501
1502static int tg3_mdio_init(struct tg3 *tp)
1503{
1504 int i;
1505 u32 reg;
1506 struct phy_device *phydev;
1507
1508 if (tg3_flag(tp, 5717_PLUS)) {
1509 u32 is_serdes;
1510
1511 tp->phy_addr = tp->pci_fn + 1;
1512
1513 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1514 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1515 else
1516 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1517 TG3_CPMU_PHY_STRAP_IS_SERDES;
1518 if (is_serdes)
1519 tp->phy_addr += 7;
1520 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1521 int addr;
1522
1523 addr = ssb_gige_get_phyaddr(tp->pdev);
1524 if (addr < 0)
1525 return addr;
1526 tp->phy_addr = addr;
1527 } else
1528 tp->phy_addr = TG3_PHY_MII_ADDR;
1529
1530 tg3_mdio_start(tp);
1531
1532 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1533 return 0;
1534
1535 tp->mdio_bus = mdiobus_alloc();
1536 if (tp->mdio_bus == NULL)
1537 return -ENOMEM;
1538
1539 tp->mdio_bus->name = "tg3 mdio bus";
1540 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1541 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1542 tp->mdio_bus->priv = tp;
1543 tp->mdio_bus->parent = &tp->pdev->dev;
1544 tp->mdio_bus->read = &tg3_mdio_read;
1545 tp->mdio_bus->write = &tg3_mdio_write;
1546 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1547
1548
1549
1550
1551
1552
1553 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1554 tg3_bmcr_reset(tp);
1555
1556 i = mdiobus_register(tp->mdio_bus);
1557 if (i) {
1558 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1559 mdiobus_free(tp->mdio_bus);
1560 return i;
1561 }
1562
1563 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
1564
1565 if (!phydev || !phydev->drv) {
1566 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1567 mdiobus_unregister(tp->mdio_bus);
1568 mdiobus_free(tp->mdio_bus);
1569 return -ENODEV;
1570 }
1571
1572 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1573 case PHY_ID_BCM57780:
1574 phydev->interface = PHY_INTERFACE_MODE_GMII;
1575 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1576 break;
1577 case PHY_ID_BCM50610:
1578 case PHY_ID_BCM50610M:
1579 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1580 PHY_BRCM_RX_REFCLK_UNUSED |
1581 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1582 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1583 fallthrough;
1584 case PHY_ID_RTL8211C:
1585 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1586 break;
1587 case PHY_ID_RTL8201E:
1588 case PHY_ID_BCMAC131:
1589 phydev->interface = PHY_INTERFACE_MODE_MII;
1590 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1591 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1592 break;
1593 }
1594
1595 tg3_flag_set(tp, MDIOBUS_INITED);
1596
1597 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1598 tg3_mdio_config_5785(tp);
1599
1600 return 0;
1601}
1602
1603static void tg3_mdio_fini(struct tg3 *tp)
1604{
1605 if (tg3_flag(tp, MDIOBUS_INITED)) {
1606 tg3_flag_clear(tp, MDIOBUS_INITED);
1607 mdiobus_unregister(tp->mdio_bus);
1608 mdiobus_free(tp->mdio_bus);
1609 }
1610}
1611
1612
1613static inline void tg3_generate_fw_event(struct tg3 *tp)
1614{
1615 u32 val;
1616
1617 val = tr32(GRC_RX_CPU_EVENT);
1618 val |= GRC_RX_CPU_DRIVER_EVENT;
1619 tw32_f(GRC_RX_CPU_EVENT, val);
1620
1621 tp->last_event_jiffies = jiffies;
1622}
1623
1624#define TG3_FW_EVENT_TIMEOUT_USEC 2500
1625
1626
1627static void tg3_wait_for_event_ack(struct tg3 *tp)
1628{
1629 int i;
1630 unsigned int delay_cnt;
1631 long time_remain;
1632
1633
1634 time_remain = (long)(tp->last_event_jiffies + 1 +
1635 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1636 (long)jiffies;
1637 if (time_remain < 0)
1638 return;
1639
1640
1641 delay_cnt = jiffies_to_usecs(time_remain);
1642 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1643 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1644 delay_cnt = (delay_cnt >> 3) + 1;
1645
1646 for (i = 0; i < delay_cnt; i++) {
1647 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1648 break;
1649 if (pci_channel_offline(tp->pdev))
1650 break;
1651
1652 udelay(8);
1653 }
1654}
1655
1656
1657static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1658{
1659 u32 reg, val;
1660
1661 val = 0;
1662 if (!tg3_readphy(tp, MII_BMCR, ®))
1663 val = reg << 16;
1664 if (!tg3_readphy(tp, MII_BMSR, ®))
1665 val |= (reg & 0xffff);
1666 *data++ = val;
1667
1668 val = 0;
1669 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1670 val = reg << 16;
1671 if (!tg3_readphy(tp, MII_LPA, ®))
1672 val |= (reg & 0xffff);
1673 *data++ = val;
1674
1675 val = 0;
1676 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1677 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1678 val = reg << 16;
1679 if (!tg3_readphy(tp, MII_STAT1000, ®))
1680 val |= (reg & 0xffff);
1681 }
1682 *data++ = val;
1683
1684 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1685 val = reg << 16;
1686 else
1687 val = 0;
1688 *data++ = val;
1689}
1690
1691
1692static void tg3_ump_link_report(struct tg3 *tp)
1693{
1694 u32 data[4];
1695
1696 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1697 return;
1698
1699 tg3_phy_gather_ump_data(tp, data);
1700
1701 tg3_wait_for_event_ack(tp);
1702
1703 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1704 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1709
1710 tg3_generate_fw_event(tp);
1711}
1712
1713
1714static void tg3_stop_fw(struct tg3 *tp)
1715{
1716 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1717
1718 tg3_wait_for_event_ack(tp);
1719
1720 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1721
1722 tg3_generate_fw_event(tp);
1723
1724
1725 tg3_wait_for_event_ack(tp);
1726 }
1727}
1728
1729
1730static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1731{
1732 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1733 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1734
1735 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1736 switch (kind) {
1737 case RESET_KIND_INIT:
1738 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1739 DRV_STATE_START);
1740 break;
1741
1742 case RESET_KIND_SHUTDOWN:
1743 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1744 DRV_STATE_UNLOAD);
1745 break;
1746
1747 case RESET_KIND_SUSPEND:
1748 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 DRV_STATE_SUSPEND);
1750 break;
1751
1752 default:
1753 break;
1754 }
1755 }
1756}
1757
1758
1759static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1760{
1761 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1762 switch (kind) {
1763 case RESET_KIND_INIT:
1764 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 DRV_STATE_START_DONE);
1766 break;
1767
1768 case RESET_KIND_SHUTDOWN:
1769 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1770 DRV_STATE_UNLOAD_DONE);
1771 break;
1772
1773 default:
1774 break;
1775 }
1776 }
1777}
1778
1779
1780static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1781{
1782 if (tg3_flag(tp, ENABLE_ASF)) {
1783 switch (kind) {
1784 case RESET_KIND_INIT:
1785 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1786 DRV_STATE_START);
1787 break;
1788
1789 case RESET_KIND_SHUTDOWN:
1790 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1791 DRV_STATE_UNLOAD);
1792 break;
1793
1794 case RESET_KIND_SUSPEND:
1795 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 DRV_STATE_SUSPEND);
1797 break;
1798
1799 default:
1800 break;
1801 }
1802 }
1803}
1804
1805static int tg3_poll_fw(struct tg3 *tp)
1806{
1807 int i;
1808 u32 val;
1809
1810 if (tg3_flag(tp, NO_FWARE_REPORTED))
1811 return 0;
1812
1813 if (tg3_flag(tp, IS_SSB_CORE)) {
1814
1815 return 0;
1816 }
1817
1818 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1819
1820 for (i = 0; i < 200; i++) {
1821 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1822 return 0;
1823 if (pci_channel_offline(tp->pdev))
1824 return -ENODEV;
1825
1826 udelay(100);
1827 }
1828 return -ENODEV;
1829 }
1830
1831
1832 for (i = 0; i < 100000; i++) {
1833 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1834 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1835 break;
1836 if (pci_channel_offline(tp->pdev)) {
1837 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1838 tg3_flag_set(tp, NO_FWARE_REPORTED);
1839 netdev_info(tp->dev, "No firmware running\n");
1840 }
1841
1842 break;
1843 }
1844
1845 udelay(10);
1846 }
1847
1848
1849
1850
1851
1852
1853 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1854 tg3_flag_set(tp, NO_FWARE_REPORTED);
1855
1856 netdev_info(tp->dev, "No firmware running\n");
1857 }
1858
1859 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1860
1861
1862
1863 mdelay(10);
1864 }
1865
1866 return 0;
1867}
1868
1869static void tg3_link_report(struct tg3 *tp)
1870{
1871 if (!netif_carrier_ok(tp->dev)) {
1872 netif_info(tp, link, tp->dev, "Link is down\n");
1873 tg3_ump_link_report(tp);
1874 } else if (netif_msg_link(tp)) {
1875 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1876 (tp->link_config.active_speed == SPEED_1000 ?
1877 1000 :
1878 (tp->link_config.active_speed == SPEED_100 ?
1879 100 : 10)),
1880 (tp->link_config.active_duplex == DUPLEX_FULL ?
1881 "full" : "half"));
1882
1883 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1884 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1885 "on" : "off",
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1887 "on" : "off");
1888
1889 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1890 netdev_info(tp->dev, "EEE is %s\n",
1891 tp->setlpicnt ? "enabled" : "disabled");
1892
1893 tg3_ump_link_report(tp);
1894 }
1895
1896 tp->link_up = netif_carrier_ok(tp->dev);
1897}
1898
1899static u32 tg3_decode_flowctrl_1000T(u32 adv)
1900{
1901 u32 flowctrl = 0;
1902
1903 if (adv & ADVERTISE_PAUSE_CAP) {
1904 flowctrl |= FLOW_CTRL_RX;
1905 if (!(adv & ADVERTISE_PAUSE_ASYM))
1906 flowctrl |= FLOW_CTRL_TX;
1907 } else if (adv & ADVERTISE_PAUSE_ASYM)
1908 flowctrl |= FLOW_CTRL_TX;
1909
1910 return flowctrl;
1911}
1912
1913static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1914{
1915 u16 miireg;
1916
1917 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1918 miireg = ADVERTISE_1000XPAUSE;
1919 else if (flow_ctrl & FLOW_CTRL_TX)
1920 miireg = ADVERTISE_1000XPSE_ASYM;
1921 else if (flow_ctrl & FLOW_CTRL_RX)
1922 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1923 else
1924 miireg = 0;
1925
1926 return miireg;
1927}
1928
1929static u32 tg3_decode_flowctrl_1000X(u32 adv)
1930{
1931 u32 flowctrl = 0;
1932
1933 if (adv & ADVERTISE_1000XPAUSE) {
1934 flowctrl |= FLOW_CTRL_RX;
1935 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1936 flowctrl |= FLOW_CTRL_TX;
1937 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1938 flowctrl |= FLOW_CTRL_TX;
1939
1940 return flowctrl;
1941}
1942
1943static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1944{
1945 u8 cap = 0;
1946
1947 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1948 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1949 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1950 if (lcladv & ADVERTISE_1000XPAUSE)
1951 cap = FLOW_CTRL_RX;
1952 if (rmtadv & ADVERTISE_1000XPAUSE)
1953 cap = FLOW_CTRL_TX;
1954 }
1955
1956 return cap;
1957}
1958
1959static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1960{
1961 u8 autoneg;
1962 u8 flowctrl = 0;
1963 u32 old_rx_mode = tp->rx_mode;
1964 u32 old_tx_mode = tp->tx_mode;
1965
1966 if (tg3_flag(tp, USE_PHYLIB))
1967 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;
1968 else
1969 autoneg = tp->link_config.autoneg;
1970
1971 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1972 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1973 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1974 else
1975 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1976 } else
1977 flowctrl = tp->link_config.flowctrl;
1978
1979 tp->link_config.active_flowctrl = flowctrl;
1980
1981 if (flowctrl & FLOW_CTRL_RX)
1982 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1983 else
1984 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1985
1986 if (old_rx_mode != tp->rx_mode)
1987 tw32_f(MAC_RX_MODE, tp->rx_mode);
1988
1989 if (flowctrl & FLOW_CTRL_TX)
1990 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1991 else
1992 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1993
1994 if (old_tx_mode != tp->tx_mode)
1995 tw32_f(MAC_TX_MODE, tp->tx_mode);
1996}
1997
1998static void tg3_adjust_link(struct net_device *dev)
1999{
2000 u8 oldflowctrl, linkmesg = 0;
2001 u32 mac_mode, lcl_adv, rmt_adv;
2002 struct tg3 *tp = netdev_priv(dev);
2003 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2004
2005 spin_lock_bh(&tp->lock);
2006
2007 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2008 MAC_MODE_HALF_DUPLEX);
2009
2010 oldflowctrl = tp->link_config.active_flowctrl;
2011
2012 if (phydev->link) {
2013 lcl_adv = 0;
2014 rmt_adv = 0;
2015
2016 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2017 mac_mode |= MAC_MODE_PORT_MODE_MII;
2018 else if (phydev->speed == SPEED_1000 ||
2019 tg3_asic_rev(tp) != ASIC_REV_5785)
2020 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2021 else
2022 mac_mode |= MAC_MODE_PORT_MODE_MII;
2023
2024 if (phydev->duplex == DUPLEX_HALF)
2025 mac_mode |= MAC_MODE_HALF_DUPLEX;
2026 else {
2027 lcl_adv = mii_advertise_flowctrl(
2028 tp->link_config.flowctrl);
2029
2030 if (phydev->pause)
2031 rmt_adv = LPA_PAUSE_CAP;
2032 if (phydev->asym_pause)
2033 rmt_adv |= LPA_PAUSE_ASYM;
2034 }
2035
2036 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2037 } else
2038 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2039
2040 if (mac_mode != tp->mac_mode) {
2041 tp->mac_mode = mac_mode;
2042 tw32_f(MAC_MODE, tp->mac_mode);
2043 udelay(40);
2044 }
2045
2046 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2047 if (phydev->speed == SPEED_10)
2048 tw32(MAC_MI_STAT,
2049 MAC_MI_STAT_10MBPS_MODE |
2050 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2051 else
2052 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2053 }
2054
2055 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2056 tw32(MAC_TX_LENGTHS,
2057 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2058 (6 << TX_LENGTHS_IPG_SHIFT) |
2059 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2060 else
2061 tw32(MAC_TX_LENGTHS,
2062 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2063 (6 << TX_LENGTHS_IPG_SHIFT) |
2064 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065
2066 if (phydev->link != tp->old_link ||
2067 phydev->speed != tp->link_config.active_speed ||
2068 phydev->duplex != tp->link_config.active_duplex ||
2069 oldflowctrl != tp->link_config.active_flowctrl)
2070 linkmesg = 1;
2071
2072 tp->old_link = phydev->link;
2073 tp->link_config.active_speed = phydev->speed;
2074 tp->link_config.active_duplex = phydev->duplex;
2075
2076 spin_unlock_bh(&tp->lock);
2077
2078 if (linkmesg)
2079 tg3_link_report(tp);
2080}
2081
2082static int tg3_phy_init(struct tg3 *tp)
2083{
2084 struct phy_device *phydev;
2085
2086 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2087 return 0;
2088
2089
2090 tg3_bmcr_reset(tp);
2091
2092 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2093
2094
2095 phydev = phy_connect(tp->dev, phydev_name(phydev),
2096 tg3_adjust_link, phydev->interface);
2097 if (IS_ERR(phydev)) {
2098 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2099 return PTR_ERR(phydev);
2100 }
2101
2102
2103 switch (phydev->interface) {
2104 case PHY_INTERFACE_MODE_GMII:
2105 case PHY_INTERFACE_MODE_RGMII:
2106 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2107 phy_set_max_speed(phydev, SPEED_1000);
2108 phy_support_asym_pause(phydev);
2109 break;
2110 }
2111 fallthrough;
2112 case PHY_INTERFACE_MODE_MII:
2113 phy_set_max_speed(phydev, SPEED_100);
2114 phy_support_asym_pause(phydev);
2115 break;
2116 default:
2117 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2118 return -EINVAL;
2119 }
2120
2121 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2122
2123 phy_attached_info(phydev);
2124
2125 return 0;
2126}
2127
2128static void tg3_phy_start(struct tg3 *tp)
2129{
2130 struct phy_device *phydev;
2131
2132 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2133 return;
2134
2135 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
2136
2137 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2138 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2139 phydev->speed = tp->link_config.speed;
2140 phydev->duplex = tp->link_config.duplex;
2141 phydev->autoneg = tp->link_config.autoneg;
2142 ethtool_convert_legacy_u32_to_link_mode(
2143 phydev->advertising, tp->link_config.advertising);
2144 }
2145
2146 phy_start(phydev);
2147
2148 phy_start_aneg(phydev);
2149}
2150
2151static void tg3_phy_stop(struct tg3 *tp)
2152{
2153 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2154 return;
2155
2156 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2157}
2158
2159static void tg3_phy_fini(struct tg3 *tp)
2160{
2161 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2162 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));
2163 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2164 }
2165}
2166
2167static int tg3_phy_set_extloopbk(struct tg3 *tp)
2168{
2169 int err;
2170 u32 val;
2171
2172 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2173 return 0;
2174
2175 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2176
2177 err = tg3_phy_auxctl_write(tp,
2178 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2179 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2180 0x4c20);
2181 goto done;
2182 }
2183
2184 err = tg3_phy_auxctl_read(tp,
2185 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2186 if (err)
2187 return err;
2188
2189 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2190 err = tg3_phy_auxctl_write(tp,
2191 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2192
2193done:
2194 return err;
2195}
2196
2197static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2198{
2199 u32 phytest;
2200
2201 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2202 u32 phy;
2203
2204 tg3_writephy(tp, MII_TG3_FET_TEST,
2205 phytest | MII_TG3_FET_SHADOW_EN);
2206 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2207 if (enable)
2208 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2209 else
2210 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2211 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2212 }
2213 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2214 }
2215}
2216
2217static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2218{
2219 u32 reg;
2220
2221 if (!tg3_flag(tp, 5705_PLUS) ||
2222 (tg3_flag(tp, 5717_PLUS) &&
2223 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2224 return;
2225
2226 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2227 tg3_phy_fet_toggle_apd(tp, enable);
2228 return;
2229 }
2230
2231 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2232 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2233 MII_TG3_MISC_SHDW_SCR5_SDTL |
2234 MII_TG3_MISC_SHDW_SCR5_C125OE;
2235 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2236 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2237
2238 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2239
2240
2241 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2242 if (enable)
2243 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2244
2245 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2246}
2247
2248static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2249{
2250 u32 phy;
2251
2252 if (!tg3_flag(tp, 5705_PLUS) ||
2253 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2254 return;
2255
2256 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2257 u32 ephy;
2258
2259 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2260 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2261
2262 tg3_writephy(tp, MII_TG3_FET_TEST,
2263 ephy | MII_TG3_FET_SHADOW_EN);
2264 if (!tg3_readphy(tp, reg, &phy)) {
2265 if (enable)
2266 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2267 else
2268 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2269 tg3_writephy(tp, reg, phy);
2270 }
2271 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2272 }
2273 } else {
2274 int ret;
2275
2276 ret = tg3_phy_auxctl_read(tp,
2277 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2278 if (!ret) {
2279 if (enable)
2280 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2281 else
2282 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2283 tg3_phy_auxctl_write(tp,
2284 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2285 }
2286 }
2287}
2288
2289static void tg3_phy_set_wirespeed(struct tg3 *tp)
2290{
2291 int ret;
2292 u32 val;
2293
2294 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2295 return;
2296
2297 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2298 if (!ret)
2299 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2300 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2301}
2302
2303static void tg3_phy_apply_otp(struct tg3 *tp)
2304{
2305 u32 otp, phy;
2306
2307 if (!tp->phy_otp)
2308 return;
2309
2310 otp = tp->phy_otp;
2311
2312 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2313 return;
2314
2315 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2316 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2317 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2318
2319 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2320 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2321 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2322
2323 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2324 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2325 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2326
2327 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2328 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2329
2330 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2331 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2332
2333 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2334 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2335 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2336
2337 tg3_phy_toggle_auxctl_smdsp(tp, false);
2338}
2339
2340static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2341{
2342 u32 val;
2343 struct ethtool_eee *dest = &tp->eee;
2344
2345 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2346 return;
2347
2348 if (eee)
2349 dest = eee;
2350
2351 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2352 return;
2353
2354
2355 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2356 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2357 dest->eee_active = 1;
2358 } else
2359 dest->eee_active = 0;
2360
2361
2362 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2363 return;
2364 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2365
2366
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2368 return;
2369 dest->eee_enabled = !!val;
2370 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2371
2372
2373 val = tr32(TG3_CPMU_EEE_MODE);
2374 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2375
2376
2377 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2378}
2379
2380static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2381{
2382 u32 val;
2383
2384 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2385 return;
2386
2387 tp->setlpicnt = 0;
2388
2389 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2390 current_link_up &&
2391 tp->link_config.active_duplex == DUPLEX_FULL &&
2392 (tp->link_config.active_speed == SPEED_100 ||
2393 tp->link_config.active_speed == SPEED_1000)) {
2394 u32 eeectl;
2395
2396 if (tp->link_config.active_speed == SPEED_1000)
2397 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2398 else
2399 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2400
2401 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2402
2403 tg3_eee_pull_config(tp, NULL);
2404 if (tp->eee.eee_active)
2405 tp->setlpicnt = 2;
2406 }
2407
2408 if (!tp->setlpicnt) {
2409 if (current_link_up &&
2410 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2411 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2412 tg3_phy_toggle_auxctl_smdsp(tp, false);
2413 }
2414
2415 val = tr32(TG3_CPMU_EEE_MODE);
2416 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2417 }
2418}
2419
2420static void tg3_phy_eee_enable(struct tg3 *tp)
2421{
2422 u32 val;
2423
2424 if (tp->link_config.active_speed == SPEED_1000 &&
2425 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2426 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2427 tg3_flag(tp, 57765_CLASS)) &&
2428 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2429 val = MII_TG3_DSP_TAP26_ALNOKO |
2430 MII_TG3_DSP_TAP26_RMRXSTO;
2431 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2432 tg3_phy_toggle_auxctl_smdsp(tp, false);
2433 }
2434
2435 val = tr32(TG3_CPMU_EEE_MODE);
2436 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2437}
2438
2439static int tg3_wait_macro_done(struct tg3 *tp)
2440{
2441 int limit = 100;
2442
2443 while (limit--) {
2444 u32 tmp32;
2445
2446 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2447 if ((tmp32 & 0x1000) == 0)
2448 break;
2449 }
2450 }
2451 if (limit < 0)
2452 return -EBUSY;
2453
2454 return 0;
2455}
2456
2457static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2458{
2459 static const u32 test_pat[4][6] = {
2460 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2461 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2462 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2463 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2464 };
2465 int chan;
2466
2467 for (chan = 0; chan < 4; chan++) {
2468 int i;
2469
2470 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2471 (chan * 0x2000) | 0x0200);
2472 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2473
2474 for (i = 0; i < 6; i++)
2475 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2476 test_pat[chan][i]);
2477
2478 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2479 if (tg3_wait_macro_done(tp)) {
2480 *resetp = 1;
2481 return -EBUSY;
2482 }
2483
2484 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2485 (chan * 0x2000) | 0x0200);
2486 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2487 if (tg3_wait_macro_done(tp)) {
2488 *resetp = 1;
2489 return -EBUSY;
2490 }
2491
2492 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2493 if (tg3_wait_macro_done(tp)) {
2494 *resetp = 1;
2495 return -EBUSY;
2496 }
2497
2498 for (i = 0; i < 6; i += 2) {
2499 u32 low, high;
2500
2501 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2502 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2503 tg3_wait_macro_done(tp)) {
2504 *resetp = 1;
2505 return -EBUSY;
2506 }
2507 low &= 0x7fff;
2508 high &= 0x000f;
2509 if (low != test_pat[chan][i] ||
2510 high != test_pat[chan][i+1]) {
2511 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2512 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2514
2515 return -EBUSY;
2516 }
2517 }
2518 }
2519
2520 return 0;
2521}
2522
2523static int tg3_phy_reset_chanpat(struct tg3 *tp)
2524{
2525 int chan;
2526
2527 for (chan = 0; chan < 4; chan++) {
2528 int i;
2529
2530 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2531 (chan * 0x2000) | 0x0200);
2532 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2533 for (i = 0; i < 6; i++)
2534 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2535 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2536 if (tg3_wait_macro_done(tp))
2537 return -EBUSY;
2538 }
2539
2540 return 0;
2541}
2542
2543static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2544{
2545 u32 reg32, phy9_orig;
2546 int retries, do_phy_reset, err;
2547
2548 retries = 10;
2549 do_phy_reset = 1;
2550 do {
2551 if (do_phy_reset) {
2552 err = tg3_bmcr_reset(tp);
2553 if (err)
2554 return err;
2555 do_phy_reset = 0;
2556 }
2557
2558
2559 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2560 continue;
2561
2562 reg32 |= 0x3000;
2563 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2564
2565
2566 tg3_writephy(tp, MII_BMCR,
2567 BMCR_FULLDPLX | BMCR_SPEED1000);
2568
2569
2570 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2571 continue;
2572
2573 tg3_writephy(tp, MII_CTRL1000,
2574 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2575
2576 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2577 if (err)
2578 return err;
2579
2580
2581 tg3_phydsp_write(tp, 0x8005, 0x0800);
2582
2583 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2584 if (!err)
2585 break;
2586 } while (--retries);
2587
2588 err = tg3_phy_reset_chanpat(tp);
2589 if (err)
2590 return err;
2591
2592 tg3_phydsp_write(tp, 0x8005, 0x0000);
2593
2594 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2595 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2596
2597 tg3_phy_toggle_auxctl_smdsp(tp, false);
2598
2599 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2600
2601 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2602 if (err)
2603 return err;
2604
2605 reg32 &= ~0x3000;
2606 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2607
2608 return 0;
2609}
2610
2611static void tg3_carrier_off(struct tg3 *tp)
2612{
2613 netif_carrier_off(tp->dev);
2614 tp->link_up = false;
2615}
2616
2617static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2618{
2619 if (tg3_flag(tp, ENABLE_ASF))
2620 netdev_warn(tp->dev,
2621 "Management side-band traffic will be interrupted during phy settings change\n");
2622}
2623
2624
2625
2626
2627static int tg3_phy_reset(struct tg3 *tp)
2628{
2629 u32 val, cpmuctrl;
2630 int err;
2631
2632 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2633 val = tr32(GRC_MISC_CFG);
2634 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2635 udelay(40);
2636 }
2637 err = tg3_readphy(tp, MII_BMSR, &val);
2638 err |= tg3_readphy(tp, MII_BMSR, &val);
2639 if (err != 0)
2640 return -EBUSY;
2641
2642 if (netif_running(tp->dev) && tp->link_up) {
2643 netif_carrier_off(tp->dev);
2644 tg3_link_report(tp);
2645 }
2646
2647 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2648 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2649 tg3_asic_rev(tp) == ASIC_REV_5705) {
2650 err = tg3_phy_reset_5703_4_5(tp);
2651 if (err)
2652 return err;
2653 goto out;
2654 }
2655
2656 cpmuctrl = 0;
2657 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2658 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2659 cpmuctrl = tr32(TG3_CPMU_CTRL);
2660 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2661 tw32(TG3_CPMU_CTRL,
2662 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2663 }
2664
2665 err = tg3_bmcr_reset(tp);
2666 if (err)
2667 return err;
2668
2669 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2670 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2671 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2672
2673 tw32(TG3_CPMU_CTRL, cpmuctrl);
2674 }
2675
2676 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2677 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2678 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2679 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2680 CPMU_LSPD_1000MB_MACCLK_12_5) {
2681 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2682 udelay(40);
2683 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2684 }
2685 }
2686
2687 if (tg3_flag(tp, 5717_PLUS) &&
2688 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2689 return 0;
2690
2691 tg3_phy_apply_otp(tp);
2692
2693 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2694 tg3_phy_toggle_apd(tp, true);
2695 else
2696 tg3_phy_toggle_apd(tp, false);
2697
2698out:
2699 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2700 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2701 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2702 tg3_phydsp_write(tp, 0x000a, 0x0323);
2703 tg3_phy_toggle_auxctl_smdsp(tp, false);
2704 }
2705
2706 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2707 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2709 }
2710
2711 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2712 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2713 tg3_phydsp_write(tp, 0x000a, 0x310b);
2714 tg3_phydsp_write(tp, 0x201f, 0x9506);
2715 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2716 tg3_phy_toggle_auxctl_smdsp(tp, false);
2717 }
2718 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2719 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2720 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2721 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2722 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2723 tg3_writephy(tp, MII_TG3_TEST1,
2724 MII_TG3_TEST1_TRIM_EN | 0x4);
2725 } else
2726 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2727
2728 tg3_phy_toggle_auxctl_smdsp(tp, false);
2729 }
2730 }
2731
2732
2733
2734 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2735
2736 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2737 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2738
2739 err = tg3_phy_auxctl_read(tp,
2740 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2741 if (!err)
2742 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2743 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2744 }
2745
2746
2747
2748
2749 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2750 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2751 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2752 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2753 }
2754
2755 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2756
2757 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2758 }
2759
2760 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2761 tg3_phydsp_write(tp, 0xffb, 0x4000);
2762
2763 tg3_phy_toggle_automdix(tp, true);
2764 tg3_phy_set_wirespeed(tp);
2765 return 0;
2766}
2767
2768#define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2769#define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2770#define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2771 TG3_GPIO_MSG_NEED_VAUX)
2772#define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2773 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2774 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2775 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2776 (TG3_GPIO_MSG_DRVR_PRES << 12))
2777
2778#define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2779 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2780 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2781 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2782 (TG3_GPIO_MSG_NEED_VAUX << 12))
2783
2784static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2785{
2786 u32 status, shift;
2787
2788 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2789 tg3_asic_rev(tp) == ASIC_REV_5719)
2790 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2791 else
2792 status = tr32(TG3_CPMU_DRV_STATUS);
2793
2794 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2795 status &= ~(TG3_GPIO_MSG_MASK << shift);
2796 status |= (newstat << shift);
2797
2798 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2799 tg3_asic_rev(tp) == ASIC_REV_5719)
2800 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2801 else
2802 tw32(TG3_CPMU_DRV_STATUS, status);
2803
2804 return status >> TG3_APE_GPIO_MSG_SHIFT;
2805}
2806
2807static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2808{
2809 if (!tg3_flag(tp, IS_NIC))
2810 return 0;
2811
2812 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2813 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2814 tg3_asic_rev(tp) == ASIC_REV_5720) {
2815 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2816 return -EIO;
2817
2818 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2819
2820 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2821 TG3_GRC_LCLCTL_PWRSW_DELAY);
2822
2823 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2824 } else {
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2827 }
2828
2829 return 0;
2830}
2831
2832static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2833{
2834 u32 grc_local_ctrl;
2835
2836 if (!tg3_flag(tp, IS_NIC) ||
2837 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2838 tg3_asic_rev(tp) == ASIC_REV_5701)
2839 return;
2840
2841 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2842
2843 tw32_wait_f(GRC_LOCAL_CTRL,
2844 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2845 TG3_GRC_LCLCTL_PWRSW_DELAY);
2846
2847 tw32_wait_f(GRC_LOCAL_CTRL,
2848 grc_local_ctrl,
2849 TG3_GRC_LCLCTL_PWRSW_DELAY);
2850
2851 tw32_wait_f(GRC_LOCAL_CTRL,
2852 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2853 TG3_GRC_LCLCTL_PWRSW_DELAY);
2854}
2855
2856static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2857{
2858 if (!tg3_flag(tp, IS_NIC))
2859 return;
2860
2861 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2862 tg3_asic_rev(tp) == ASIC_REV_5701) {
2863 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2864 (GRC_LCLCTRL_GPIO_OE0 |
2865 GRC_LCLCTRL_GPIO_OE1 |
2866 GRC_LCLCTRL_GPIO_OE2 |
2867 GRC_LCLCTRL_GPIO_OUTPUT0 |
2868 GRC_LCLCTRL_GPIO_OUTPUT1),
2869 TG3_GRC_LCLCTL_PWRSW_DELAY);
2870 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2871 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2872
2873 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2874 GRC_LCLCTRL_GPIO_OE1 |
2875 GRC_LCLCTRL_GPIO_OE2 |
2876 GRC_LCLCTRL_GPIO_OUTPUT0 |
2877 GRC_LCLCTRL_GPIO_OUTPUT1 |
2878 tp->grc_local_ctrl;
2879 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2880 TG3_GRC_LCLCTL_PWRSW_DELAY);
2881
2882 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2883 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2884 TG3_GRC_LCLCTL_PWRSW_DELAY);
2885
2886 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2887 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2888 TG3_GRC_LCLCTL_PWRSW_DELAY);
2889 } else {
2890 u32 no_gpio2;
2891 u32 grc_local_ctrl = 0;
2892
2893
2894 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2895 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2896 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2897 grc_local_ctrl,
2898 TG3_GRC_LCLCTL_PWRSW_DELAY);
2899 }
2900
2901
2902 no_gpio2 = tp->nic_sram_data_cfg &
2903 NIC_SRAM_DATA_CFG_NO_GPIO2;
2904
2905 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2906 GRC_LCLCTRL_GPIO_OE1 |
2907 GRC_LCLCTRL_GPIO_OE2 |
2908 GRC_LCLCTRL_GPIO_OUTPUT1 |
2909 GRC_LCLCTRL_GPIO_OUTPUT2;
2910 if (no_gpio2) {
2911 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2912 GRC_LCLCTRL_GPIO_OUTPUT2);
2913 }
2914 tw32_wait_f(GRC_LOCAL_CTRL,
2915 tp->grc_local_ctrl | grc_local_ctrl,
2916 TG3_GRC_LCLCTL_PWRSW_DELAY);
2917
2918 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2919
2920 tw32_wait_f(GRC_LOCAL_CTRL,
2921 tp->grc_local_ctrl | grc_local_ctrl,
2922 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923
2924 if (!no_gpio2) {
2925 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2926 tw32_wait_f(GRC_LOCAL_CTRL,
2927 tp->grc_local_ctrl | grc_local_ctrl,
2928 TG3_GRC_LCLCTL_PWRSW_DELAY);
2929 }
2930 }
2931}
2932
2933static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2934{
2935 u32 msg = 0;
2936
2937
2938 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2939 return;
2940
2941 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2942 msg = TG3_GPIO_MSG_NEED_VAUX;
2943
2944 msg = tg3_set_function_status(tp, msg);
2945
2946 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2947 goto done;
2948
2949 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2950 tg3_pwrsrc_switch_to_vaux(tp);
2951 else
2952 tg3_pwrsrc_die_with_vmain(tp);
2953
2954done:
2955 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2956}
2957
2958static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2959{
2960 bool need_vaux = false;
2961
2962
2963 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2964 return;
2965
2966 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2967 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2968 tg3_asic_rev(tp) == ASIC_REV_5720) {
2969 tg3_frob_aux_power_5717(tp, include_wol ?
2970 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2971 return;
2972 }
2973
2974 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2975 struct net_device *dev_peer;
2976
2977 dev_peer = pci_get_drvdata(tp->pdev_peer);
2978
2979
2980 if (dev_peer) {
2981 struct tg3 *tp_peer = netdev_priv(dev_peer);
2982
2983 if (tg3_flag(tp_peer, INIT_COMPLETE))
2984 return;
2985
2986 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2987 tg3_flag(tp_peer, ENABLE_ASF))
2988 need_vaux = true;
2989 }
2990 }
2991
2992 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2993 tg3_flag(tp, ENABLE_ASF))
2994 need_vaux = true;
2995
2996 if (need_vaux)
2997 tg3_pwrsrc_switch_to_vaux(tp);
2998 else
2999 tg3_pwrsrc_die_with_vmain(tp);
3000}
3001
3002static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3003{
3004 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3005 return 1;
3006 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3007 if (speed != SPEED_10)
3008 return 1;
3009 } else if (speed == SPEED_10)
3010 return 1;
3011
3012 return 0;
3013}
3014
3015static bool tg3_phy_power_bug(struct tg3 *tp)
3016{
3017 switch (tg3_asic_rev(tp)) {
3018 case ASIC_REV_5700:
3019 case ASIC_REV_5704:
3020 return true;
3021 case ASIC_REV_5780:
3022 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3023 return true;
3024 return false;
3025 case ASIC_REV_5717:
3026 if (!tp->pci_fn)
3027 return true;
3028 return false;
3029 case ASIC_REV_5719:
3030 case ASIC_REV_5720:
3031 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3032 !tp->pci_fn)
3033 return true;
3034 return false;
3035 }
3036
3037 return false;
3038}
3039
3040static bool tg3_phy_led_bug(struct tg3 *tp)
3041{
3042 switch (tg3_asic_rev(tp)) {
3043 case ASIC_REV_5719:
3044 case ASIC_REV_5720:
3045 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3046 !tp->pci_fn)
3047 return true;
3048 return false;
3049 }
3050
3051 return false;
3052}
3053
3054static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3055{
3056 u32 val;
3057
3058 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3059 return;
3060
3061 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3062 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3063 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3064 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3065
3066 sg_dig_ctrl |=
3067 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3068 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3069 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3070 }
3071 return;
3072 }
3073
3074 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3075 tg3_bmcr_reset(tp);
3076 val = tr32(GRC_MISC_CFG);
3077 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3078 udelay(40);
3079 return;
3080 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3081 u32 phytest;
3082 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3083 u32 phy;
3084
3085 tg3_writephy(tp, MII_ADVERTISE, 0);
3086 tg3_writephy(tp, MII_BMCR,
3087 BMCR_ANENABLE | BMCR_ANRESTART);
3088
3089 tg3_writephy(tp, MII_TG3_FET_TEST,
3090 phytest | MII_TG3_FET_SHADOW_EN);
3091 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3092 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3093 tg3_writephy(tp,
3094 MII_TG3_FET_SHDW_AUXMODE4,
3095 phy);
3096 }
3097 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3098 }
3099 return;
3100 } else if (do_low_power) {
3101 if (!tg3_phy_led_bug(tp))
3102 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3103 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3104
3105 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3106 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3107 MII_TG3_AUXCTL_PCTL_VREG_11V;
3108 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3109 }
3110
3111
3112
3113
3114 if (tg3_phy_power_bug(tp))
3115 return;
3116
3117 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3118 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3119 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3120 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3121 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3122 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3123 }
3124
3125 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3126}
3127
3128
3129static int tg3_nvram_lock(struct tg3 *tp)
3130{
3131 if (tg3_flag(tp, NVRAM)) {
3132 int i;
3133
3134 if (tp->nvram_lock_cnt == 0) {
3135 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3136 for (i = 0; i < 8000; i++) {
3137 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3138 break;
3139 udelay(20);
3140 }
3141 if (i == 8000) {
3142 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3143 return -ENODEV;
3144 }
3145 }
3146 tp->nvram_lock_cnt++;
3147 }
3148 return 0;
3149}
3150
3151
3152static void tg3_nvram_unlock(struct tg3 *tp)
3153{
3154 if (tg3_flag(tp, NVRAM)) {
3155 if (tp->nvram_lock_cnt > 0)
3156 tp->nvram_lock_cnt--;
3157 if (tp->nvram_lock_cnt == 0)
3158 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3159 }
3160}
3161
3162
3163static void tg3_enable_nvram_access(struct tg3 *tp)
3164{
3165 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3166 u32 nvaccess = tr32(NVRAM_ACCESS);
3167
3168 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3169 }
3170}
3171
3172
3173static void tg3_disable_nvram_access(struct tg3 *tp)
3174{
3175 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3176 u32 nvaccess = tr32(NVRAM_ACCESS);
3177
3178 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3179 }
3180}
3181
3182static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3183 u32 offset, u32 *val)
3184{
3185 u32 tmp;
3186 int i;
3187
3188 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3189 return -EINVAL;
3190
3191 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3192 EEPROM_ADDR_DEVID_MASK |
3193 EEPROM_ADDR_READ);
3194 tw32(GRC_EEPROM_ADDR,
3195 tmp |
3196 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3197 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3198 EEPROM_ADDR_ADDR_MASK) |
3199 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3200
3201 for (i = 0; i < 1000; i++) {
3202 tmp = tr32(GRC_EEPROM_ADDR);
3203
3204 if (tmp & EEPROM_ADDR_COMPLETE)
3205 break;
3206 msleep(1);
3207 }
3208 if (!(tmp & EEPROM_ADDR_COMPLETE))
3209 return -EBUSY;
3210
3211 tmp = tr32(GRC_EEPROM_DATA);
3212
3213
3214
3215
3216
3217 *val = swab32(tmp);
3218
3219 return 0;
3220}
3221
3222#define NVRAM_CMD_TIMEOUT 10000
3223
3224static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3225{
3226 int i;
3227
3228 tw32(NVRAM_CMD, nvram_cmd);
3229 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3230 usleep_range(10, 40);
3231 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3232 udelay(10);
3233 break;
3234 }
3235 }
3236
3237 if (i == NVRAM_CMD_TIMEOUT)
3238 return -EBUSY;
3239
3240 return 0;
3241}
3242
3243static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3244{
3245 if (tg3_flag(tp, NVRAM) &&
3246 tg3_flag(tp, NVRAM_BUFFERED) &&
3247 tg3_flag(tp, FLASH) &&
3248 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3249 (tp->nvram_jedecnum == JEDEC_ATMEL))
3250
3251 addr = ((addr / tp->nvram_pagesize) <<
3252 ATMEL_AT45DB0X1B_PAGE_POS) +
3253 (addr % tp->nvram_pagesize);
3254
3255 return addr;
3256}
3257
3258static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3259{
3260 if (tg3_flag(tp, NVRAM) &&
3261 tg3_flag(tp, NVRAM_BUFFERED) &&
3262 tg3_flag(tp, FLASH) &&
3263 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3264 (tp->nvram_jedecnum == JEDEC_ATMEL))
3265
3266 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3267 tp->nvram_pagesize) +
3268 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3269
3270 return addr;
3271}
3272
3273
3274
3275
3276
3277
3278
3279static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3280{
3281 int ret;
3282
3283 if (!tg3_flag(tp, NVRAM))
3284 return tg3_nvram_read_using_eeprom(tp, offset, val);
3285
3286 offset = tg3_nvram_phys_addr(tp, offset);
3287
3288 if (offset > NVRAM_ADDR_MSK)
3289 return -EINVAL;
3290
3291 ret = tg3_nvram_lock(tp);
3292 if (ret)
3293 return ret;
3294
3295 tg3_enable_nvram_access(tp);
3296
3297 tw32(NVRAM_ADDR, offset);
3298 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3299 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3300
3301 if (ret == 0)
3302 *val = tr32(NVRAM_RDDATA);
3303
3304 tg3_disable_nvram_access(tp);
3305
3306 tg3_nvram_unlock(tp);
3307
3308 return ret;
3309}
3310
3311
3312static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3313{
3314 u32 v;
3315 int res = tg3_nvram_read(tp, offset, &v);
3316 if (!res)
3317 *val = cpu_to_be32(v);
3318 return res;
3319}
3320
3321static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3322 u32 offset, u32 len, u8 *buf)
3323{
3324 int i, j, rc = 0;
3325 u32 val;
3326
3327 for (i = 0; i < len; i += 4) {
3328 u32 addr;
3329 __be32 data;
3330
3331 addr = offset + i;
3332
3333 memcpy(&data, buf + i, 4);
3334
3335
3336
3337
3338
3339
3340
3341 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3342
3343 val = tr32(GRC_EEPROM_ADDR);
3344 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3345
3346 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3347 EEPROM_ADDR_READ);
3348 tw32(GRC_EEPROM_ADDR, val |
3349 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3350 (addr & EEPROM_ADDR_ADDR_MASK) |
3351 EEPROM_ADDR_START |
3352 EEPROM_ADDR_WRITE);
3353
3354 for (j = 0; j < 1000; j++) {
3355 val = tr32(GRC_EEPROM_ADDR);
3356
3357 if (val & EEPROM_ADDR_COMPLETE)
3358 break;
3359 msleep(1);
3360 }
3361 if (!(val & EEPROM_ADDR_COMPLETE)) {
3362 rc = -EBUSY;
3363 break;
3364 }
3365 }
3366
3367 return rc;
3368}
3369
3370
3371static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3372 u8 *buf)
3373{
3374 int ret = 0;
3375 u32 pagesize = tp->nvram_pagesize;
3376 u32 pagemask = pagesize - 1;
3377 u32 nvram_cmd;
3378 u8 *tmp;
3379
3380 tmp = kmalloc(pagesize, GFP_KERNEL);
3381 if (tmp == NULL)
3382 return -ENOMEM;
3383
3384 while (len) {
3385 int j;
3386 u32 phy_addr, page_off, size;
3387
3388 phy_addr = offset & ~pagemask;
3389
3390 for (j = 0; j < pagesize; j += 4) {
3391 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3392 (__be32 *) (tmp + j));
3393 if (ret)
3394 break;
3395 }
3396 if (ret)
3397 break;
3398
3399 page_off = offset & pagemask;
3400 size = pagesize;
3401 if (len < size)
3402 size = len;
3403
3404 len -= size;
3405
3406 memcpy(tmp + page_off, buf, size);
3407
3408 offset = offset + (pagesize - page_off);
3409
3410 tg3_enable_nvram_access(tp);
3411
3412
3413
3414
3415
3416 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3417
3418 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3419 break;
3420
3421
3422 tw32(NVRAM_ADDR, phy_addr);
3423
3424 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3425 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3426
3427 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3428 break;
3429
3430
3431 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3432
3433 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3434 break;
3435
3436 for (j = 0; j < pagesize; j += 4) {
3437 __be32 data;
3438
3439 data = *((__be32 *) (tmp + j));
3440
3441 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3442
3443 tw32(NVRAM_ADDR, phy_addr + j);
3444
3445 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3446 NVRAM_CMD_WR;
3447
3448 if (j == 0)
3449 nvram_cmd |= NVRAM_CMD_FIRST;
3450 else if (j == (pagesize - 4))
3451 nvram_cmd |= NVRAM_CMD_LAST;
3452
3453 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3454 if (ret)
3455 break;
3456 }
3457 if (ret)
3458 break;
3459 }
3460
3461 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3462 tg3_nvram_exec_cmd(tp, nvram_cmd);
3463
3464 kfree(tmp);
3465
3466 return ret;
3467}
3468
3469
3470static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3471 u8 *buf)
3472{
3473 int i, ret = 0;
3474
3475 for (i = 0; i < len; i += 4, offset += 4) {
3476 u32 page_off, phy_addr, nvram_cmd;
3477 __be32 data;
3478
3479 memcpy(&data, buf + i, 4);
3480 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3481
3482 page_off = offset % tp->nvram_pagesize;
3483
3484 phy_addr = tg3_nvram_phys_addr(tp, offset);
3485
3486 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3487
3488 if (page_off == 0 || i == 0)
3489 nvram_cmd |= NVRAM_CMD_FIRST;
3490 if (page_off == (tp->nvram_pagesize - 4))
3491 nvram_cmd |= NVRAM_CMD_LAST;
3492
3493 if (i == (len - 4))
3494 nvram_cmd |= NVRAM_CMD_LAST;
3495
3496 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3497 !tg3_flag(tp, FLASH) ||
3498 !tg3_flag(tp, 57765_PLUS))
3499 tw32(NVRAM_ADDR, phy_addr);
3500
3501 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3502 !tg3_flag(tp, 5755_PLUS) &&
3503 (tp->nvram_jedecnum == JEDEC_ST) &&
3504 (nvram_cmd & NVRAM_CMD_FIRST)) {
3505 u32 cmd;
3506
3507 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3508 ret = tg3_nvram_exec_cmd(tp, cmd);
3509 if (ret)
3510 break;
3511 }
3512 if (!tg3_flag(tp, FLASH)) {
3513
3514 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3515 }
3516
3517 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3518 if (ret)
3519 break;
3520 }
3521 return ret;
3522}
3523
3524
3525static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3526{
3527 int ret;
3528
3529 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3530 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3531 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3532 udelay(40);
3533 }
3534
3535 if (!tg3_flag(tp, NVRAM)) {
3536 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3537 } else {
3538 u32 grc_mode;
3539
3540 ret = tg3_nvram_lock(tp);
3541 if (ret)
3542 return ret;
3543
3544 tg3_enable_nvram_access(tp);
3545 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3546 tw32(NVRAM_WRITE1, 0x406);
3547
3548 grc_mode = tr32(GRC_MODE);
3549 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3550
3551 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3552 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3553 buf);
3554 } else {
3555 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3556 buf);
3557 }
3558
3559 grc_mode = tr32(GRC_MODE);
3560 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3561
3562 tg3_disable_nvram_access(tp);
3563 tg3_nvram_unlock(tp);
3564 }
3565
3566 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3567 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3568 udelay(40);
3569 }
3570
3571 return ret;
3572}
3573
3574#define RX_CPU_SCRATCH_BASE 0x30000
3575#define RX_CPU_SCRATCH_SIZE 0x04000
3576#define TX_CPU_SCRATCH_BASE 0x34000
3577#define TX_CPU_SCRATCH_SIZE 0x04000
3578
3579
3580static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3581{
3582 int i;
3583 const int iters = 10000;
3584
3585 for (i = 0; i < iters; i++) {
3586 tw32(cpu_base + CPU_STATE, 0xffffffff);
3587 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3588 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3589 break;
3590 if (pci_channel_offline(tp->pdev))
3591 return -EBUSY;
3592 }
3593
3594 return (i == iters) ? -EBUSY : 0;
3595}
3596
3597
3598static int tg3_rxcpu_pause(struct tg3 *tp)
3599{
3600 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3601
3602 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3603 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3604 udelay(10);
3605
3606 return rc;
3607}
3608
3609
3610static int tg3_txcpu_pause(struct tg3 *tp)
3611{
3612 return tg3_pause_cpu(tp, TX_CPU_BASE);
3613}
3614
3615
3616static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3617{
3618 tw32(cpu_base + CPU_STATE, 0xffffffff);
3619 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3620}
3621
3622
3623static void tg3_rxcpu_resume(struct tg3 *tp)
3624{
3625 tg3_resume_cpu(tp, RX_CPU_BASE);
3626}
3627
3628
3629static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3630{
3631 int rc;
3632
3633 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3634
3635 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3636 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3637
3638 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3639 return 0;
3640 }
3641 if (cpu_base == RX_CPU_BASE) {
3642 rc = tg3_rxcpu_pause(tp);
3643 } else {
3644
3645
3646
3647
3648 if (tg3_flag(tp, IS_SSB_CORE))
3649 return 0;
3650
3651 rc = tg3_txcpu_pause(tp);
3652 }
3653
3654 if (rc) {
3655 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3656 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3657 return -ENODEV;
3658 }
3659
3660
3661 if (tg3_flag(tp, NVRAM))
3662 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3663 return 0;
3664}
3665
3666static int tg3_fw_data_len(struct tg3 *tp,
3667 const struct tg3_firmware_hdr *fw_hdr)
3668{
3669 int fw_len;
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685 if (tp->fw_len == 0xffffffff)
3686 fw_len = be32_to_cpu(fw_hdr->len);
3687 else
3688 fw_len = tp->fw->size;
3689
3690 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3691}
3692
3693
3694static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3695 u32 cpu_scratch_base, int cpu_scratch_size,
3696 const struct tg3_firmware_hdr *fw_hdr)
3697{
3698 int err, i;
3699 void (*write_op)(struct tg3 *, u32, u32);
3700 int total_len = tp->fw->size;
3701
3702 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3703 netdev_err(tp->dev,
3704 "%s: Trying to load TX cpu firmware which is 5705\n",
3705 __func__);
3706 return -EINVAL;
3707 }
3708
3709 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3710 write_op = tg3_write_mem;
3711 else
3712 write_op = tg3_write_indirect_reg32;
3713
3714 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3715
3716
3717
3718 int lock_err = tg3_nvram_lock(tp);
3719 err = tg3_halt_cpu(tp, cpu_base);
3720 if (!lock_err)
3721 tg3_nvram_unlock(tp);
3722 if (err)
3723 goto out;
3724
3725 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3726 write_op(tp, cpu_scratch_base + i, 0);
3727 tw32(cpu_base + CPU_STATE, 0xffffffff);
3728 tw32(cpu_base + CPU_MODE,
3729 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3730 } else {
3731
3732
3733
3734 total_len -= TG3_FW_HDR_LEN;
3735 fw_hdr++;
3736 }
3737
3738 do {
3739 u32 *fw_data = (u32 *)(fw_hdr + 1);
3740 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3741 write_op(tp, cpu_scratch_base +
3742 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3743 (i * sizeof(u32)),
3744 be32_to_cpu(fw_data[i]));
3745
3746 total_len -= be32_to_cpu(fw_hdr->len);
3747
3748
3749 fw_hdr = (struct tg3_firmware_hdr *)
3750 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3751 } while (total_len > 0);
3752
3753 err = 0;
3754
3755out:
3756 return err;
3757}
3758
3759
3760static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3761{
3762 int i;
3763 const int iters = 5;
3764
3765 tw32(cpu_base + CPU_STATE, 0xffffffff);
3766 tw32_f(cpu_base + CPU_PC, pc);
3767
3768 for (i = 0; i < iters; i++) {
3769 if (tr32(cpu_base + CPU_PC) == pc)
3770 break;
3771 tw32(cpu_base + CPU_STATE, 0xffffffff);
3772 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3773 tw32_f(cpu_base + CPU_PC, pc);
3774 udelay(1000);
3775 }
3776
3777 return (i == iters) ? -EBUSY : 0;
3778}
3779
3780
3781static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3782{
3783 const struct tg3_firmware_hdr *fw_hdr;
3784 int err;
3785
3786 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3787
3788
3789
3790
3791
3792
3793
3794 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3795 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3796 fw_hdr);
3797 if (err)
3798 return err;
3799
3800 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3801 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3802 fw_hdr);
3803 if (err)
3804 return err;
3805
3806
3807 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3808 be32_to_cpu(fw_hdr->base_addr));
3809 if (err) {
3810 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3811 "should be %08x\n", __func__,
3812 tr32(RX_CPU_BASE + CPU_PC),
3813 be32_to_cpu(fw_hdr->base_addr));
3814 return -ENODEV;
3815 }
3816
3817 tg3_rxcpu_resume(tp);
3818
3819 return 0;
3820}
3821
3822static int tg3_validate_rxcpu_state(struct tg3 *tp)
3823{
3824 const int iters = 1000;
3825 int i;
3826 u32 val;
3827
3828
3829
3830
3831 for (i = 0; i < iters; i++) {
3832 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3833 break;
3834
3835 udelay(10);
3836 }
3837
3838 if (i == iters) {
3839 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3840 return -EBUSY;
3841 }
3842
3843 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3844 if (val & 0xff) {
3845 netdev_warn(tp->dev,
3846 "Other patches exist. Not downloading EEE patch\n");
3847 return -EEXIST;
3848 }
3849
3850 return 0;
3851}
3852
3853
3854static void tg3_load_57766_firmware(struct tg3 *tp)
3855{
3856 struct tg3_firmware_hdr *fw_hdr;
3857
3858 if (!tg3_flag(tp, NO_NVRAM))
3859 return;
3860
3861 if (tg3_validate_rxcpu_state(tp))
3862 return;
3863
3864 if (!tp->fw)
3865 return;
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3882 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3883 return;
3884
3885 if (tg3_rxcpu_pause(tp))
3886 return;
3887
3888
3889 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3890
3891 tg3_rxcpu_resume(tp);
3892}
3893
3894
3895static int tg3_load_tso_firmware(struct tg3 *tp)
3896{
3897 const struct tg3_firmware_hdr *fw_hdr;
3898 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3899 int err;
3900
3901 if (!tg3_flag(tp, FW_TSO))
3902 return 0;
3903
3904 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3905
3906
3907
3908
3909
3910
3911
3912 cpu_scratch_size = tp->fw_len;
3913
3914 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3915 cpu_base = RX_CPU_BASE;
3916 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3917 } else {
3918 cpu_base = TX_CPU_BASE;
3919 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3920 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3921 }
3922
3923 err = tg3_load_firmware_cpu(tp, cpu_base,
3924 cpu_scratch_base, cpu_scratch_size,
3925 fw_hdr);
3926 if (err)
3927 return err;
3928
3929
3930 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3931 be32_to_cpu(fw_hdr->base_addr));
3932 if (err) {
3933 netdev_err(tp->dev,
3934 "%s fails to set CPU PC, is %08x should be %08x\n",
3935 __func__, tr32(cpu_base + CPU_PC),
3936 be32_to_cpu(fw_hdr->base_addr));
3937 return -ENODEV;
3938 }
3939
3940 tg3_resume_cpu(tp, cpu_base);
3941 return 0;
3942}
3943
3944
3945static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3946{
3947 u32 addr_high, addr_low;
3948
3949 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3950 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3951 (mac_addr[4] << 8) | mac_addr[5]);
3952
3953 if (index < 4) {
3954 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3955 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3956 } else {
3957 index -= 4;
3958 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3959 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3960 }
3961}
3962
3963
3964static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3965{
3966 u32 addr_high;
3967 int i;
3968
3969 for (i = 0; i < 4; i++) {
3970 if (i == 1 && skip_mac_1)
3971 continue;
3972 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3973 }
3974
3975 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3976 tg3_asic_rev(tp) == ASIC_REV_5704) {
3977 for (i = 4; i < 16; i++)
3978 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3979 }
3980
3981 addr_high = (tp->dev->dev_addr[0] +
3982 tp->dev->dev_addr[1] +
3983 tp->dev->dev_addr[2] +
3984 tp->dev->dev_addr[3] +
3985 tp->dev->dev_addr[4] +
3986 tp->dev->dev_addr[5]) &
3987 TX_BACKOFF_SEED_MASK;
3988 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3989}
3990
3991static void tg3_enable_register_access(struct tg3 *tp)
3992{
3993
3994
3995
3996
3997 pci_write_config_dword(tp->pdev,
3998 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3999}
4000
4001static int tg3_power_up(struct tg3 *tp)
4002{
4003 int err;
4004
4005 tg3_enable_register_access(tp);
4006
4007 err = pci_set_power_state(tp->pdev, PCI_D0);
4008 if (!err) {
4009
4010 tg3_pwrsrc_switch_to_vmain(tp);
4011 } else {
4012 netdev_err(tp->dev, "Transition to D0 failed\n");
4013 }
4014
4015 return err;
4016}
4017
4018static int tg3_setup_phy(struct tg3 *, bool);
4019
4020static int tg3_power_down_prepare(struct tg3 *tp)
4021{
4022 u32 misc_host_ctrl;
4023 bool device_should_wake, do_low_power;
4024
4025 tg3_enable_register_access(tp);
4026
4027
4028 if (tg3_flag(tp, CLKREQ_BUG))
4029 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4030 PCI_EXP_LNKCTL_CLKREQ_EN);
4031
4032 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4033 tw32(TG3PCI_MISC_HOST_CTRL,
4034 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4035
4036 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4037 tg3_flag(tp, WOL_ENABLE);
4038
4039 if (tg3_flag(tp, USE_PHYLIB)) {
4040 do_low_power = false;
4041 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4042 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4043 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, };
4044 struct phy_device *phydev;
4045 u32 phyid;
4046
4047 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);
4048
4049 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4050
4051 tp->link_config.speed = phydev->speed;
4052 tp->link_config.duplex = phydev->duplex;
4053 tp->link_config.autoneg = phydev->autoneg;
4054 ethtool_convert_link_mode_to_legacy_u32(
4055 &tp->link_config.advertising,
4056 phydev->advertising);
4057
4058 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, advertising);
4059 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
4060 advertising);
4061 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
4062 advertising);
4063 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT,
4064 advertising);
4065
4066 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4067 if (tg3_flag(tp, WOL_SPEED_100MB)) {
4068 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
4069 advertising);
4070 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT,
4071 advertising);
4072 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4073 advertising);
4074 } else {
4075 linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT,
4076 advertising);
4077 }
4078 }
4079
4080 linkmode_copy(phydev->advertising, advertising);
4081 phy_start_aneg(phydev);
4082
4083 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4084 if (phyid != PHY_ID_BCMAC131) {
4085 phyid &= PHY_BCM_OUI_MASK;
4086 if (phyid == PHY_BCM_OUI_1 ||
4087 phyid == PHY_BCM_OUI_2 ||
4088 phyid == PHY_BCM_OUI_3)
4089 do_low_power = true;
4090 }
4091 }
4092 } else {
4093 do_low_power = true;
4094
4095 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4096 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4097
4098 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4099 tg3_setup_phy(tp, false);
4100 }
4101
4102 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4103 u32 val;
4104
4105 val = tr32(GRC_VCPU_EXT_CTRL);
4106 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4107 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4108 int i;
4109 u32 val;
4110
4111 for (i = 0; i < 200; i++) {
4112 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4113 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4114 break;
4115 msleep(1);
4116 }
4117 }
4118 if (tg3_flag(tp, WOL_CAP))
4119 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4120 WOL_DRV_STATE_SHUTDOWN |
4121 WOL_DRV_WOL |
4122 WOL_SET_MAGIC_PKT);
4123
4124 if (device_should_wake) {
4125 u32 mac_mode;
4126
4127 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4128 if (do_low_power &&
4129 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4130 tg3_phy_auxctl_write(tp,
4131 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4132 MII_TG3_AUXCTL_PCTL_WOL_EN |
4133 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4134 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4135 udelay(40);
4136 }
4137
4138 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4140 else if (tp->phy_flags &
4141 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4142 if (tp->link_config.active_speed == SPEED_1000)
4143 mac_mode = MAC_MODE_PORT_MODE_GMII;
4144 else
4145 mac_mode = MAC_MODE_PORT_MODE_MII;
4146 } else
4147 mac_mode = MAC_MODE_PORT_MODE_MII;
4148
4149 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4150 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4151 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4152 SPEED_100 : SPEED_10;
4153 if (tg3_5700_link_polarity(tp, speed))
4154 mac_mode |= MAC_MODE_LINK_POLARITY;
4155 else
4156 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4157 }
4158 } else {
4159 mac_mode = MAC_MODE_PORT_MODE_TBI;
4160 }
4161
4162 if (!tg3_flag(tp, 5750_PLUS))
4163 tw32(MAC_LED_CTRL, tp->led_ctrl);
4164
4165 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4166 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4167 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4168 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4169
4170 if (tg3_flag(tp, ENABLE_APE))
4171 mac_mode |= MAC_MODE_APE_TX_EN |
4172 MAC_MODE_APE_RX_EN |
4173 MAC_MODE_TDE_ENABLE;
4174
4175 tw32_f(MAC_MODE, mac_mode);
4176 udelay(100);
4177
4178 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4179 udelay(10);
4180 }
4181
4182 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4183 (tg3_asic_rev(