linux/drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h
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   1/* Broadcom NetXtreme-C/E network driver.
   2 *
   3 * Copyright (c) 2014-2016 Broadcom Corporation
   4 * Copyright (c) 2014-2018 Broadcom Limited
   5 * Copyright (c) 2018-2021 Broadcom Inc.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation.
  10 *
  11 * DO NOT MODIFY!!! This file is automatically generated.
  12 */
  13
  14#ifndef _BNXT_HSI_H_
  15#define _BNXT_HSI_H_
  16
  17/* hwrm_cmd_hdr (size:128b/16B) */
  18struct hwrm_cmd_hdr {
  19        __le16  req_type;
  20        __le16  cmpl_ring;
  21        __le16  seq_id;
  22        __le16  target_id;
  23        __le64  resp_addr;
  24};
  25
  26/* hwrm_resp_hdr (size:64b/8B) */
  27struct hwrm_resp_hdr {
  28        __le16  error_code;
  29        __le16  req_type;
  30        __le16  seq_id;
  31        __le16  resp_len;
  32};
  33
  34#define CMD_DISCR_TLV_ENCAP 0x8000UL
  35#define CMD_DISCR_LAST     CMD_DISCR_TLV_ENCAP
  36
  37
  38#define TLV_TYPE_HWRM_REQUEST                    0x1UL
  39#define TLV_TYPE_HWRM_RESPONSE                   0x2UL
  40#define TLV_TYPE_ROCE_SP_COMMAND                 0x3UL
  41#define TLV_TYPE_QUERY_ROCE_CC_GEN1              0x4UL
  42#define TLV_TYPE_MODIFY_ROCE_CC_GEN1             0x5UL
  43#define TLV_TYPE_ENGINE_CKV_ALIAS_ECC_PUBLIC_KEY 0x8001UL
  44#define TLV_TYPE_ENGINE_CKV_IV                   0x8003UL
  45#define TLV_TYPE_ENGINE_CKV_AUTH_TAG             0x8004UL
  46#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT           0x8005UL
  47#define TLV_TYPE_ENGINE_CKV_HOST_ALGORITHMS      0x8006UL
  48#define TLV_TYPE_ENGINE_CKV_HOST_ECC_PUBLIC_KEY  0x8007UL
  49#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE      0x8008UL
  50#define TLV_TYPE_ENGINE_CKV_FW_ECC_PUBLIC_KEY    0x8009UL
  51#define TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS        0x800aUL
  52#define TLV_TYPE_LAST                           TLV_TYPE_ENGINE_CKV_FW_ALGORITHMS
  53
  54
  55/* tlv (size:64b/8B) */
  56struct tlv {
  57        __le16  cmd_discr;
  58        u8      reserved_8b;
  59        u8      flags;
  60        #define TLV_FLAGS_MORE         0x1UL
  61        #define TLV_FLAGS_MORE_LAST      0x0UL
  62        #define TLV_FLAGS_MORE_NOT_LAST  0x1UL
  63        #define TLV_FLAGS_REQUIRED     0x2UL
  64        #define TLV_FLAGS_REQUIRED_NO    (0x0UL << 1)
  65        #define TLV_FLAGS_REQUIRED_YES   (0x1UL << 1)
  66        #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES
  67        __le16  tlv_type;
  68        __le16  length;
  69};
  70
  71/* input (size:128b/16B) */
  72struct input {
  73        __le16  req_type;
  74        __le16  cmpl_ring;
  75        __le16  seq_id;
  76        __le16  target_id;
  77        __le64  resp_addr;
  78};
  79
  80/* output (size:64b/8B) */
  81struct output {
  82        __le16  error_code;
  83        __le16  req_type;
  84        __le16  seq_id;
  85        __le16  resp_len;
  86};
  87
  88/* hwrm_short_input (size:128b/16B) */
  89struct hwrm_short_input {
  90        __le16  req_type;
  91        __le16  signature;
  92        #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL
  93        #define SHORT_REQ_SIGNATURE_LAST     SHORT_REQ_SIGNATURE_SHORT_CMD
  94        __le16  target_id;
  95        #define SHORT_REQ_TARGET_ID_DEFAULT 0x0UL
  96        #define SHORT_REQ_TARGET_ID_TOOLS   0xfffdUL
  97        #define SHORT_REQ_TARGET_ID_LAST   SHORT_REQ_TARGET_ID_TOOLS
  98        __le16  size;
  99        __le64  req_addr;
 100};
 101
 102/* cmd_nums (size:64b/8B) */
 103struct cmd_nums {
 104        __le16  req_type;
 105        #define HWRM_VER_GET                              0x0UL
 106        #define HWRM_FUNC_ECHO_RESPONSE                   0xbUL
 107        #define HWRM_ERROR_RECOVERY_QCFG                  0xcUL
 108        #define HWRM_FUNC_DRV_IF_CHANGE                   0xdUL
 109        #define HWRM_FUNC_BUF_UNRGTR                      0xeUL
 110        #define HWRM_FUNC_VF_CFG                          0xfUL
 111        #define HWRM_RESERVED1                            0x10UL
 112        #define HWRM_FUNC_RESET                           0x11UL
 113        #define HWRM_FUNC_GETFID                          0x12UL
 114        #define HWRM_FUNC_VF_ALLOC                        0x13UL
 115        #define HWRM_FUNC_VF_FREE                         0x14UL
 116        #define HWRM_FUNC_QCAPS                           0x15UL
 117        #define HWRM_FUNC_QCFG                            0x16UL
 118        #define HWRM_FUNC_CFG                             0x17UL
 119        #define HWRM_FUNC_QSTATS                          0x18UL
 120        #define HWRM_FUNC_CLR_STATS                       0x19UL
 121        #define HWRM_FUNC_DRV_UNRGTR                      0x1aUL
 122        #define HWRM_FUNC_VF_RESC_FREE                    0x1bUL
 123        #define HWRM_FUNC_VF_VNIC_IDS_QUERY               0x1cUL
 124        #define HWRM_FUNC_DRV_RGTR                        0x1dUL
 125        #define HWRM_FUNC_DRV_QVER                        0x1eUL
 126        #define HWRM_FUNC_BUF_RGTR                        0x1fUL
 127        #define HWRM_PORT_PHY_CFG                         0x20UL
 128        #define HWRM_PORT_MAC_CFG                         0x21UL
 129        #define HWRM_PORT_TS_QUERY                        0x22UL
 130        #define HWRM_PORT_QSTATS                          0x23UL
 131        #define HWRM_PORT_LPBK_QSTATS                     0x24UL
 132        #define HWRM_PORT_CLR_STATS                       0x25UL
 133        #define HWRM_PORT_LPBK_CLR_STATS                  0x26UL
 134        #define HWRM_PORT_PHY_QCFG                        0x27UL
 135        #define HWRM_PORT_MAC_QCFG                        0x28UL
 136        #define HWRM_PORT_MAC_PTP_QCFG                    0x29UL
 137        #define HWRM_PORT_PHY_QCAPS                       0x2aUL
 138        #define HWRM_PORT_PHY_I2C_WRITE                   0x2bUL
 139        #define HWRM_PORT_PHY_I2C_READ                    0x2cUL
 140        #define HWRM_PORT_LED_CFG                         0x2dUL
 141        #define HWRM_PORT_LED_QCFG                        0x2eUL
 142        #define HWRM_PORT_LED_QCAPS                       0x2fUL
 143        #define HWRM_QUEUE_QPORTCFG                       0x30UL
 144        #define HWRM_QUEUE_QCFG                           0x31UL
 145        #define HWRM_QUEUE_CFG                            0x32UL
 146        #define HWRM_FUNC_VLAN_CFG                        0x33UL
 147        #define HWRM_FUNC_VLAN_QCFG                       0x34UL
 148        #define HWRM_QUEUE_PFCENABLE_QCFG                 0x35UL
 149        #define HWRM_QUEUE_PFCENABLE_CFG                  0x36UL
 150        #define HWRM_QUEUE_PRI2COS_QCFG                   0x37UL
 151        #define HWRM_QUEUE_PRI2COS_CFG                    0x38UL
 152        #define HWRM_QUEUE_COS2BW_QCFG                    0x39UL
 153        #define HWRM_QUEUE_COS2BW_CFG                     0x3aUL
 154        #define HWRM_QUEUE_DSCP_QCAPS                     0x3bUL
 155        #define HWRM_QUEUE_DSCP2PRI_QCFG                  0x3cUL
 156        #define HWRM_QUEUE_DSCP2PRI_CFG                   0x3dUL
 157        #define HWRM_VNIC_ALLOC                           0x40UL
 158        #define HWRM_VNIC_FREE                            0x41UL
 159        #define HWRM_VNIC_CFG                             0x42UL
 160        #define HWRM_VNIC_QCFG                            0x43UL
 161        #define HWRM_VNIC_TPA_CFG                         0x44UL
 162        #define HWRM_VNIC_TPA_QCFG                        0x45UL
 163        #define HWRM_VNIC_RSS_CFG                         0x46UL
 164        #define HWRM_VNIC_RSS_QCFG                        0x47UL
 165        #define HWRM_VNIC_PLCMODES_CFG                    0x48UL
 166        #define HWRM_VNIC_PLCMODES_QCFG                   0x49UL
 167        #define HWRM_VNIC_QCAPS                           0x4aUL
 168        #define HWRM_VNIC_UPDATE                          0x4bUL
 169        #define HWRM_RING_ALLOC                           0x50UL
 170        #define HWRM_RING_FREE                            0x51UL
 171        #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        0x52UL
 172        #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS     0x53UL
 173        #define HWRM_RING_AGGINT_QCAPS                    0x54UL
 174        #define HWRM_RING_SCHQ_ALLOC                      0x55UL
 175        #define HWRM_RING_SCHQ_CFG                        0x56UL
 176        #define HWRM_RING_SCHQ_FREE                       0x57UL
 177        #define HWRM_RING_RESET                           0x5eUL
 178        #define HWRM_RING_GRP_ALLOC                       0x60UL
 179        #define HWRM_RING_GRP_FREE                        0x61UL
 180        #define HWRM_RING_CFG                             0x62UL
 181        #define HWRM_RING_QCFG                            0x63UL
 182        #define HWRM_RESERVED5                            0x64UL
 183        #define HWRM_RESERVED6                            0x65UL
 184        #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC            0x70UL
 185        #define HWRM_VNIC_RSS_COS_LB_CTX_FREE             0x71UL
 186        #define HWRM_QUEUE_MPLS_QCAPS                     0x80UL
 187        #define HWRM_QUEUE_MPLSTC2PRI_QCFG                0x81UL
 188        #define HWRM_QUEUE_MPLSTC2PRI_CFG                 0x82UL
 189        #define HWRM_QUEUE_VLANPRI_QCAPS                  0x83UL
 190        #define HWRM_QUEUE_VLANPRI2PRI_QCFG               0x84UL
 191        #define HWRM_QUEUE_VLANPRI2PRI_CFG                0x85UL
 192        #define HWRM_QUEUE_GLOBAL_CFG                     0x86UL
 193        #define HWRM_QUEUE_GLOBAL_QCFG                    0x87UL
 194        #define HWRM_CFA_L2_FILTER_ALLOC                  0x90UL
 195        #define HWRM_CFA_L2_FILTER_FREE                   0x91UL
 196        #define HWRM_CFA_L2_FILTER_CFG                    0x92UL
 197        #define HWRM_CFA_L2_SET_RX_MASK                   0x93UL
 198        #define HWRM_CFA_VLAN_ANTISPOOF_CFG               0x94UL
 199        #define HWRM_CFA_TUNNEL_FILTER_ALLOC              0x95UL
 200        #define HWRM_CFA_TUNNEL_FILTER_FREE               0x96UL
 201        #define HWRM_CFA_ENCAP_RECORD_ALLOC               0x97UL
 202        #define HWRM_CFA_ENCAP_RECORD_FREE                0x98UL
 203        #define HWRM_CFA_NTUPLE_FILTER_ALLOC              0x99UL
 204        #define HWRM_CFA_NTUPLE_FILTER_FREE               0x9aUL
 205        #define HWRM_CFA_NTUPLE_FILTER_CFG                0x9bUL
 206        #define HWRM_CFA_EM_FLOW_ALLOC                    0x9cUL
 207        #define HWRM_CFA_EM_FLOW_FREE                     0x9dUL
 208        #define HWRM_CFA_EM_FLOW_CFG                      0x9eUL
 209        #define HWRM_TUNNEL_DST_PORT_QUERY                0xa0UL
 210        #define HWRM_TUNNEL_DST_PORT_ALLOC                0xa1UL
 211        #define HWRM_TUNNEL_DST_PORT_FREE                 0xa2UL
 212        #define HWRM_STAT_CTX_ENG_QUERY                   0xafUL
 213        #define HWRM_STAT_CTX_ALLOC                       0xb0UL
 214        #define HWRM_STAT_CTX_FREE                        0xb1UL
 215        #define HWRM_STAT_CTX_QUERY                       0xb2UL
 216        #define HWRM_STAT_CTX_CLR_STATS                   0xb3UL
 217        #define HWRM_PORT_QSTATS_EXT                      0xb4UL
 218        #define HWRM_PORT_PHY_MDIO_WRITE                  0xb5UL
 219        #define HWRM_PORT_PHY_MDIO_READ                   0xb6UL
 220        #define HWRM_PORT_PHY_MDIO_BUS_ACQUIRE            0xb7UL
 221        #define HWRM_PORT_PHY_MDIO_BUS_RELEASE            0xb8UL
 222        #define HWRM_PORT_QSTATS_EXT_PFC_WD               0xb9UL
 223        #define HWRM_RESERVED7                            0xbaUL
 224        #define HWRM_PORT_TX_FIR_CFG                      0xbbUL
 225        #define HWRM_PORT_TX_FIR_QCFG                     0xbcUL
 226        #define HWRM_PORT_ECN_QSTATS                      0xbdUL
 227        #define HWRM_FW_LIVEPATCH_QUERY                   0xbeUL
 228        #define HWRM_FW_LIVEPATCH                         0xbfUL
 229        #define HWRM_FW_RESET                             0xc0UL
 230        #define HWRM_FW_QSTATUS                           0xc1UL
 231        #define HWRM_FW_HEALTH_CHECK                      0xc2UL
 232        #define HWRM_FW_SYNC                              0xc3UL
 233        #define HWRM_FW_STATE_QCAPS                       0xc4UL
 234        #define HWRM_FW_STATE_QUIESCE                     0xc5UL
 235        #define HWRM_FW_STATE_BACKUP                      0xc6UL
 236        #define HWRM_FW_STATE_RESTORE                     0xc7UL
 237        #define HWRM_FW_SET_TIME                          0xc8UL
 238        #define HWRM_FW_GET_TIME                          0xc9UL
 239        #define HWRM_FW_SET_STRUCTURED_DATA               0xcaUL
 240        #define HWRM_FW_GET_STRUCTURED_DATA               0xcbUL
 241        #define HWRM_FW_IPC_MAILBOX                       0xccUL
 242        #define HWRM_FW_ECN_CFG                           0xcdUL
 243        #define HWRM_FW_ECN_QCFG                          0xceUL
 244        #define HWRM_FW_SECURE_CFG                        0xcfUL
 245        #define HWRM_EXEC_FWD_RESP                        0xd0UL
 246        #define HWRM_REJECT_FWD_RESP                      0xd1UL
 247        #define HWRM_FWD_RESP                             0xd2UL
 248        #define HWRM_FWD_ASYNC_EVENT_CMPL                 0xd3UL
 249        #define HWRM_OEM_CMD                              0xd4UL
 250        #define HWRM_PORT_PRBS_TEST                       0xd5UL
 251        #define HWRM_PORT_SFP_SIDEBAND_CFG                0xd6UL
 252        #define HWRM_PORT_SFP_SIDEBAND_QCFG               0xd7UL
 253        #define HWRM_FW_STATE_UNQUIESCE                   0xd8UL
 254        #define HWRM_PORT_DSC_DUMP                        0xd9UL
 255        #define HWRM_PORT_EP_TX_QCFG                      0xdaUL
 256        #define HWRM_PORT_EP_TX_CFG                       0xdbUL
 257        #define HWRM_TEMP_MONITOR_QUERY                   0xe0UL
 258        #define HWRM_REG_POWER_QUERY                      0xe1UL
 259        #define HWRM_CORE_FREQUENCY_QUERY                 0xe2UL
 260        #define HWRM_REG_POWER_HISTOGRAM                  0xe3UL
 261        #define HWRM_WOL_FILTER_ALLOC                     0xf0UL
 262        #define HWRM_WOL_FILTER_FREE                      0xf1UL
 263        #define HWRM_WOL_FILTER_QCFG                      0xf2UL
 264        #define HWRM_WOL_REASON_QCFG                      0xf3UL
 265        #define HWRM_CFA_METER_QCAPS                      0xf4UL
 266        #define HWRM_CFA_METER_PROFILE_ALLOC              0xf5UL
 267        #define HWRM_CFA_METER_PROFILE_FREE               0xf6UL
 268        #define HWRM_CFA_METER_PROFILE_CFG                0xf7UL
 269        #define HWRM_CFA_METER_INSTANCE_ALLOC             0xf8UL
 270        #define HWRM_CFA_METER_INSTANCE_FREE              0xf9UL
 271        #define HWRM_CFA_METER_INSTANCE_CFG               0xfaUL
 272        #define HWRM_CFA_VFR_ALLOC                        0xfdUL
 273        #define HWRM_CFA_VFR_FREE                         0xfeUL
 274        #define HWRM_CFA_VF_PAIR_ALLOC                    0x100UL
 275        #define HWRM_CFA_VF_PAIR_FREE                     0x101UL
 276        #define HWRM_CFA_VF_PAIR_INFO                     0x102UL
 277        #define HWRM_CFA_FLOW_ALLOC                       0x103UL
 278        #define HWRM_CFA_FLOW_FREE                        0x104UL
 279        #define HWRM_CFA_FLOW_FLUSH                       0x105UL
 280        #define HWRM_CFA_FLOW_STATS                       0x106UL
 281        #define HWRM_CFA_FLOW_INFO                        0x107UL
 282        #define HWRM_CFA_DECAP_FILTER_ALLOC               0x108UL
 283        #define HWRM_CFA_DECAP_FILTER_FREE                0x109UL
 284        #define HWRM_CFA_VLAN_ANTISPOOF_QCFG              0x10aUL
 285        #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC       0x10bUL
 286        #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE        0x10cUL
 287        #define HWRM_CFA_PAIR_ALLOC                       0x10dUL
 288        #define HWRM_CFA_PAIR_FREE                        0x10eUL
 289        #define HWRM_CFA_PAIR_INFO                        0x10fUL
 290        #define HWRM_FW_IPC_MSG                           0x110UL
 291        #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO        0x111UL
 292        #define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE       0x112UL
 293        #define HWRM_CFA_FLOW_AGING_TIMER_RESET           0x113UL
 294        #define HWRM_CFA_FLOW_AGING_CFG                   0x114UL
 295        #define HWRM_CFA_FLOW_AGING_QCFG                  0x115UL
 296        #define HWRM_CFA_FLOW_AGING_QCAPS                 0x116UL
 297        #define HWRM_CFA_CTX_MEM_RGTR                     0x117UL
 298        #define HWRM_CFA_CTX_MEM_UNRGTR                   0x118UL
 299        #define HWRM_CFA_CTX_MEM_QCTX                     0x119UL
 300        #define HWRM_CFA_CTX_MEM_QCAPS                    0x11aUL
 301        #define HWRM_CFA_COUNTER_QCAPS                    0x11bUL
 302        #define HWRM_CFA_COUNTER_CFG                      0x11cUL
 303        #define HWRM_CFA_COUNTER_QCFG                     0x11dUL
 304        #define HWRM_CFA_COUNTER_QSTATS                   0x11eUL
 305        #define HWRM_CFA_TCP_FLAG_PROCESS_QCFG            0x11fUL
 306        #define HWRM_CFA_EEM_QCAPS                        0x120UL
 307        #define HWRM_CFA_EEM_CFG                          0x121UL
 308        #define HWRM_CFA_EEM_QCFG                         0x122UL
 309        #define HWRM_CFA_EEM_OP                           0x123UL
 310        #define HWRM_CFA_ADV_FLOW_MGNT_QCAPS              0x124UL
 311        #define HWRM_CFA_TFLIB                            0x125UL
 312        #define HWRM_CFA_LAG_GROUP_MEMBER_RGTR            0x126UL
 313        #define HWRM_CFA_LAG_GROUP_MEMBER_UNRGTR          0x127UL
 314        #define HWRM_ENGINE_CKV_STATUS                    0x12eUL
 315        #define HWRM_ENGINE_CKV_CKEK_ADD                  0x12fUL
 316        #define HWRM_ENGINE_CKV_CKEK_DELETE               0x130UL
 317        #define HWRM_ENGINE_CKV_KEY_ADD                   0x131UL
 318        #define HWRM_ENGINE_CKV_KEY_DELETE                0x132UL
 319        #define HWRM_ENGINE_CKV_FLUSH                     0x133UL
 320        #define HWRM_ENGINE_CKV_RNG_GET                   0x134UL
 321        #define HWRM_ENGINE_CKV_KEY_GEN                   0x135UL
 322        #define HWRM_ENGINE_CKV_KEY_LABEL_CFG             0x136UL
 323        #define HWRM_ENGINE_CKV_KEY_LABEL_QCFG            0x137UL
 324        #define HWRM_ENGINE_QG_CONFIG_QUERY               0x13cUL
 325        #define HWRM_ENGINE_QG_QUERY                      0x13dUL
 326        #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL
 327        #define HWRM_ENGINE_QG_METER_PROFILE_QUERY        0x13fUL
 328        #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC        0x140UL
 329        #define HWRM_ENGINE_QG_METER_PROFILE_FREE         0x141UL
 330        #define HWRM_ENGINE_QG_METER_QUERY                0x142UL
 331        #define HWRM_ENGINE_QG_METER_BIND                 0x143UL
 332        #define HWRM_ENGINE_QG_METER_UNBIND               0x144UL
 333        #define HWRM_ENGINE_QG_FUNC_BIND                  0x145UL
 334        #define HWRM_ENGINE_SG_CONFIG_QUERY               0x146UL
 335        #define HWRM_ENGINE_SG_QUERY                      0x147UL
 336        #define HWRM_ENGINE_SG_METER_QUERY                0x148UL
 337        #define HWRM_ENGINE_SG_METER_CONFIG               0x149UL
 338        #define HWRM_ENGINE_SG_QG_BIND                    0x14aUL
 339        #define HWRM_ENGINE_QG_SG_UNBIND                  0x14bUL
 340        #define HWRM_ENGINE_CONFIG_QUERY                  0x154UL
 341        #define HWRM_ENGINE_STATS_CONFIG                  0x155UL
 342        #define HWRM_ENGINE_STATS_CLEAR                   0x156UL
 343        #define HWRM_ENGINE_STATS_QUERY                   0x157UL
 344        #define HWRM_ENGINE_STATS_QUERY_CONTINUOUS_ERROR  0x158UL
 345        #define HWRM_ENGINE_RQ_ALLOC                      0x15eUL
 346        #define HWRM_ENGINE_RQ_FREE                       0x15fUL
 347        #define HWRM_ENGINE_CQ_ALLOC                      0x160UL
 348        #define HWRM_ENGINE_CQ_FREE                       0x161UL
 349        #define HWRM_ENGINE_NQ_ALLOC                      0x162UL
 350        #define HWRM_ENGINE_NQ_FREE                       0x163UL
 351        #define HWRM_ENGINE_ON_DIE_RQE_CREDITS            0x164UL
 352        #define HWRM_ENGINE_FUNC_QCFG                     0x165UL
 353        #define HWRM_FUNC_RESOURCE_QCAPS                  0x190UL
 354        #define HWRM_FUNC_VF_RESOURCE_CFG                 0x191UL
 355        #define HWRM_FUNC_BACKING_STORE_QCAPS             0x192UL
 356        #define HWRM_FUNC_BACKING_STORE_CFG               0x193UL
 357        #define HWRM_FUNC_BACKING_STORE_QCFG              0x194UL
 358        #define HWRM_FUNC_VF_BW_CFG                       0x195UL
 359        #define HWRM_FUNC_VF_BW_QCFG                      0x196UL
 360        #define HWRM_FUNC_HOST_PF_IDS_QUERY               0x197UL
 361        #define HWRM_FUNC_QSTATS_EXT                      0x198UL
 362        #define HWRM_STAT_EXT_CTX_QUERY                   0x199UL
 363        #define HWRM_FUNC_SPD_CFG                         0x19aUL
 364        #define HWRM_FUNC_SPD_QCFG                        0x19bUL
 365        #define HWRM_FUNC_PTP_PIN_QCFG                    0x19cUL
 366        #define HWRM_FUNC_PTP_PIN_CFG                     0x19dUL
 367        #define HWRM_FUNC_PTP_CFG                         0x19eUL
 368        #define HWRM_FUNC_PTP_TS_QUERY                    0x19fUL
 369        #define HWRM_FUNC_PTP_EXT_CFG                     0x1a0UL
 370        #define HWRM_FUNC_PTP_EXT_QCFG                    0x1a1UL
 371        #define HWRM_FUNC_KEY_CTX_ALLOC                   0x1a2UL
 372        #define HWRM_SELFTEST_QLIST                       0x200UL
 373        #define HWRM_SELFTEST_EXEC                        0x201UL
 374        #define HWRM_SELFTEST_IRQ                         0x202UL
 375        #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA        0x203UL
 376        #define HWRM_PCIE_QSTATS                          0x204UL
 377        #define HWRM_MFG_FRU_WRITE_CONTROL                0x205UL
 378        #define HWRM_MFG_TIMERS_QUERY                     0x206UL
 379        #define HWRM_MFG_OTP_CFG                          0x207UL
 380        #define HWRM_MFG_OTP_QCFG                         0x208UL
 381        #define HWRM_MFG_HDMA_TEST                        0x209UL
 382        #define HWRM_MFG_FRU_EEPROM_WRITE                 0x20aUL
 383        #define HWRM_MFG_FRU_EEPROM_READ                  0x20bUL
 384        #define HWRM_MFG_SOC_IMAGE                        0x20cUL
 385        #define HWRM_MFG_SOC_QSTATUS                      0x20dUL
 386        #define HWRM_MFG_PARAM_SEEPROM_SYNC               0x20eUL
 387        #define HWRM_MFG_PARAM_SEEPROM_READ               0x20fUL
 388        #define HWRM_MFG_PARAM_SEEPROM_HEALTH             0x210UL
 389        #define HWRM_MFG_PRVSN_EXPORT_CSR                 0x211UL
 390        #define HWRM_MFG_PRVSN_IMPORT_CERT                0x212UL
 391        #define HWRM_MFG_PRVSN_GET_STATE                  0x213UL
 392        #define HWRM_MFG_GET_NVM_MEASUREMENT              0x214UL
 393        #define HWRM_TF                                   0x2bcUL
 394        #define HWRM_TF_VERSION_GET                       0x2bdUL
 395        #define HWRM_TF_SESSION_OPEN                      0x2c6UL
 396        #define HWRM_TF_SESSION_ATTACH                    0x2c7UL
 397        #define HWRM_TF_SESSION_REGISTER                  0x2c8UL
 398        #define HWRM_TF_SESSION_UNREGISTER                0x2c9UL
 399        #define HWRM_TF_SESSION_CLOSE                     0x2caUL
 400        #define HWRM_TF_SESSION_QCFG                      0x2cbUL
 401        #define HWRM_TF_SESSION_RESC_QCAPS                0x2ccUL
 402        #define HWRM_TF_SESSION_RESC_ALLOC                0x2cdUL
 403        #define HWRM_TF_SESSION_RESC_FREE                 0x2ceUL
 404        #define HWRM_TF_SESSION_RESC_FLUSH                0x2cfUL
 405        #define HWRM_TF_SESSION_RESC_INFO                 0x2d0UL
 406        #define HWRM_TF_TBL_TYPE_GET                      0x2daUL
 407        #define HWRM_TF_TBL_TYPE_SET                      0x2dbUL
 408        #define HWRM_TF_TBL_TYPE_BULK_GET                 0x2dcUL
 409        #define HWRM_TF_CTXT_MEM_ALLOC                    0x2e2UL
 410        #define HWRM_TF_CTXT_MEM_FREE                     0x2e3UL
 411        #define HWRM_TF_CTXT_MEM_RGTR                     0x2e4UL
 412        #define HWRM_TF_CTXT_MEM_UNRGTR                   0x2e5UL
 413        #define HWRM_TF_EXT_EM_QCAPS                      0x2e6UL
 414        #define HWRM_TF_EXT_EM_OP                         0x2e7UL
 415        #define HWRM_TF_EXT_EM_CFG                        0x2e8UL
 416        #define HWRM_TF_EXT_EM_QCFG                       0x2e9UL
 417        #define HWRM_TF_EM_INSERT                         0x2eaUL
 418        #define HWRM_TF_EM_DELETE                         0x2ebUL
 419        #define HWRM_TF_EM_HASH_INSERT                    0x2ecUL
 420        #define HWRM_TF_EM_MOVE                           0x2edUL
 421        #define HWRM_TF_TCAM_SET                          0x2f8UL
 422        #define HWRM_TF_TCAM_GET                          0x2f9UL
 423        #define HWRM_TF_TCAM_MOVE                         0x2faUL
 424        #define HWRM_TF_TCAM_FREE                         0x2fbUL
 425        #define HWRM_TF_GLOBAL_CFG_SET                    0x2fcUL
 426        #define HWRM_TF_GLOBAL_CFG_GET                    0x2fdUL
 427        #define HWRM_TF_IF_TBL_SET                        0x2feUL
 428        #define HWRM_TF_IF_TBL_GET                        0x2ffUL
 429        #define HWRM_SV                                   0x400UL
 430        #define HWRM_DBG_READ_DIRECT                      0xff10UL
 431        #define HWRM_DBG_READ_INDIRECT                    0xff11UL
 432        #define HWRM_DBG_WRITE_DIRECT                     0xff12UL
 433        #define HWRM_DBG_WRITE_INDIRECT                   0xff13UL
 434        #define HWRM_DBG_DUMP                             0xff14UL
 435        #define HWRM_DBG_ERASE_NVM                        0xff15UL
 436        #define HWRM_DBG_CFG                              0xff16UL
 437        #define HWRM_DBG_COREDUMP_LIST                    0xff17UL
 438        #define HWRM_DBG_COREDUMP_INITIATE                0xff18UL
 439        #define HWRM_DBG_COREDUMP_RETRIEVE                0xff19UL
 440        #define HWRM_DBG_FW_CLI                           0xff1aUL
 441        #define HWRM_DBG_I2C_CMD                          0xff1bUL
 442        #define HWRM_DBG_RING_INFO_GET                    0xff1cUL
 443        #define HWRM_DBG_CRASHDUMP_HEADER                 0xff1dUL
 444        #define HWRM_DBG_CRASHDUMP_ERASE                  0xff1eUL
 445        #define HWRM_DBG_DRV_TRACE                        0xff1fUL
 446        #define HWRM_DBG_QCAPS                            0xff20UL
 447        #define HWRM_DBG_QCFG                             0xff21UL
 448        #define HWRM_DBG_CRASHDUMP_MEDIUM_CFG             0xff22UL
 449        #define HWRM_DBG_USEQ_ALLOC                       0xff23UL
 450        #define HWRM_DBG_USEQ_FREE                        0xff24UL
 451        #define HWRM_DBG_USEQ_FLUSH                       0xff25UL
 452        #define HWRM_DBG_USEQ_QCAPS                       0xff26UL
 453        #define HWRM_DBG_USEQ_CW_CFG                      0xff27UL
 454        #define HWRM_DBG_USEQ_SCHED_CFG                   0xff28UL
 455        #define HWRM_DBG_USEQ_RUN                         0xff29UL
 456        #define HWRM_DBG_USEQ_DELIVERY_REQ                0xff2aUL
 457        #define HWRM_DBG_USEQ_RESP_HDR                    0xff2bUL
 458        #define HWRM_NVM_DEFRAG                           0xffecUL
 459        #define HWRM_NVM_REQ_ARBITRATION                  0xffedUL
 460        #define HWRM_NVM_FACTORY_DEFAULTS                 0xffeeUL
 461        #define HWRM_NVM_VALIDATE_OPTION                  0xffefUL
 462        #define HWRM_NVM_FLUSH                            0xfff0UL
 463        #define HWRM_NVM_GET_VARIABLE                     0xfff1UL
 464        #define HWRM_NVM_SET_VARIABLE                     0xfff2UL
 465        #define HWRM_NVM_INSTALL_UPDATE                   0xfff3UL
 466        #define HWRM_NVM_MODIFY                           0xfff4UL
 467        #define HWRM_NVM_VERIFY_UPDATE                    0xfff5UL
 468        #define HWRM_NVM_GET_DEV_INFO                     0xfff6UL
 469        #define HWRM_NVM_ERASE_DIR_ENTRY                  0xfff7UL
 470        #define HWRM_NVM_MOD_DIR_ENTRY                    0xfff8UL
 471        #define HWRM_NVM_FIND_DIR_ENTRY                   0xfff9UL
 472        #define HWRM_NVM_GET_DIR_ENTRIES                  0xfffaUL
 473        #define HWRM_NVM_GET_DIR_INFO                     0xfffbUL
 474        #define HWRM_NVM_RAW_DUMP                         0xfffcUL
 475        #define HWRM_NVM_READ                             0xfffdUL
 476        #define HWRM_NVM_WRITE                            0xfffeUL
 477        #define HWRM_NVM_RAW_WRITE_BLK                    0xffffUL
 478        #define HWRM_LAST                                HWRM_NVM_RAW_WRITE_BLK
 479        __le16  unused_0[3];
 480};
 481
 482/* ret_codes (size:64b/8B) */
 483struct ret_codes {
 484        __le16  error_code;
 485        #define HWRM_ERR_CODE_SUCCESS                      0x0UL
 486        #define HWRM_ERR_CODE_FAIL                         0x1UL
 487        #define HWRM_ERR_CODE_INVALID_PARAMS               0x2UL
 488        #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED       0x3UL
 489        #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR         0x4UL
 490        #define HWRM_ERR_CODE_INVALID_FLAGS                0x5UL
 491        #define HWRM_ERR_CODE_INVALID_ENABLES              0x6UL
 492        #define HWRM_ERR_CODE_UNSUPPORTED_TLV              0x7UL
 493        #define HWRM_ERR_CODE_NO_BUFFER                    0x8UL
 494        #define HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR       0x9UL
 495        #define HWRM_ERR_CODE_HOT_RESET_PROGRESS           0xaUL
 496        #define HWRM_ERR_CODE_HOT_RESET_FAIL               0xbUL
 497        #define HWRM_ERR_CODE_NO_FLOW_COUNTER_DURING_ALLOC 0xcUL
 498        #define HWRM_ERR_CODE_KEY_HASH_COLLISION           0xdUL
 499        #define HWRM_ERR_CODE_KEY_ALREADY_EXISTS           0xeUL
 500        #define HWRM_ERR_CODE_HWRM_ERROR                   0xfUL
 501        #define HWRM_ERR_CODE_BUSY                         0x10UL
 502        #define HWRM_ERR_CODE_RESOURCE_LOCKED              0x11UL
 503        #define HWRM_ERR_CODE_PF_UNAVAILABLE               0x12UL
 504        #define HWRM_ERR_CODE_TLV_ENCAPSULATED_RESPONSE    0x8000UL
 505        #define HWRM_ERR_CODE_UNKNOWN_ERR                  0xfffeUL
 506        #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED            0xffffUL
 507        #define HWRM_ERR_CODE_LAST                        HWRM_ERR_CODE_CMD_NOT_SUPPORTED
 508        __le16  unused_0[3];
 509};
 510
 511/* hwrm_err_output (size:128b/16B) */
 512struct hwrm_err_output {
 513        __le16  error_code;
 514        __le16  req_type;
 515        __le16  seq_id;
 516        __le16  resp_len;
 517        __le32  opaque_0;
 518        __le16  opaque_1;
 519        u8      cmd_err;
 520        u8      valid;
 521};
 522#define HWRM_NA_SIGNATURE ((__le32)(-1))
 523#define HWRM_MAX_REQ_LEN 128
 524#define HWRM_MAX_RESP_LEN 704
 525#define HW_HASH_INDEX_SIZE 0x80
 526#define HW_HASH_KEY_SIZE 40
 527#define HWRM_RESP_VALID_KEY 1
 528#define HWRM_TARGET_ID_BONO 0xFFF8
 529#define HWRM_TARGET_ID_KONG 0xFFF9
 530#define HWRM_TARGET_ID_APE 0xFFFA
 531#define HWRM_TARGET_ID_TOOLS 0xFFFD
 532#define HWRM_VERSION_MAJOR 1
 533#define HWRM_VERSION_MINOR 10
 534#define HWRM_VERSION_UPDATE 2
 535#define HWRM_VERSION_RSVD 52
 536#define HWRM_VERSION_STR "1.10.2.52"
 537
 538/* hwrm_ver_get_input (size:192b/24B) */
 539struct hwrm_ver_get_input {
 540        __le16  req_type;
 541        __le16  cmpl_ring;
 542        __le16  seq_id;
 543        __le16  target_id;
 544        __le64  resp_addr;
 545        u8      hwrm_intf_maj;
 546        u8      hwrm_intf_min;
 547        u8      hwrm_intf_upd;
 548        u8      unused_0[5];
 549};
 550
 551/* hwrm_ver_get_output (size:1408b/176B) */
 552struct hwrm_ver_get_output {
 553        __le16  error_code;
 554        __le16  req_type;
 555        __le16  seq_id;
 556        __le16  resp_len;
 557        u8      hwrm_intf_maj_8b;
 558        u8      hwrm_intf_min_8b;
 559        u8      hwrm_intf_upd_8b;
 560        u8      hwrm_intf_rsvd_8b;
 561        u8      hwrm_fw_maj_8b;
 562        u8      hwrm_fw_min_8b;
 563        u8      hwrm_fw_bld_8b;
 564        u8      hwrm_fw_rsvd_8b;
 565        u8      mgmt_fw_maj_8b;
 566        u8      mgmt_fw_min_8b;
 567        u8      mgmt_fw_bld_8b;
 568        u8      mgmt_fw_rsvd_8b;
 569        u8      netctrl_fw_maj_8b;
 570        u8      netctrl_fw_min_8b;
 571        u8      netctrl_fw_bld_8b;
 572        u8      netctrl_fw_rsvd_8b;
 573        __le32  dev_caps_cfg;
 574        #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED                  0x1UL
 575        #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED                  0x2UL
 576        #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED                      0x4UL
 577        #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED                       0x8UL
 578        #define VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED                   0x10UL
 579        #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED              0x20UL
 580        #define VER_GET_RESP_DEV_CAPS_CFG_L2_FILTER_TYPES_ROCE_OR_L2_SUPPORTED     0x40UL
 581        #define VER_GET_RESP_DEV_CAPS_CFG_VIRTIO_VSWITCH_OFFLOAD_SUPPORTED         0x80UL
 582        #define VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED                     0x100UL
 583        #define VER_GET_RESP_DEV_CAPS_CFG_FLOW_AGING_SUPPORTED                     0x200UL
 584        #define VER_GET_RESP_DEV_CAPS_CFG_ADV_FLOW_COUNTERS_SUPPORTED              0x400UL
 585        #define VER_GET_RESP_DEV_CAPS_CFG_CFA_EEM_SUPPORTED                        0x800UL
 586        #define VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED              0x1000UL
 587        #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED                      0x2000UL
 588        #define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED                    0x4000UL
 589        #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE                      0x8000UL
 590        u8      roce_fw_maj_8b;
 591        u8      roce_fw_min_8b;
 592        u8      roce_fw_bld_8b;
 593        u8      roce_fw_rsvd_8b;
 594        char    hwrm_fw_name[16];
 595        char    mgmt_fw_name[16];
 596        char    netctrl_fw_name[16];
 597        char    active_pkg_name[16];
 598        char    roce_fw_name[16];
 599        __le16  chip_num;
 600        u8      chip_rev;
 601        u8      chip_metal;
 602        u8      chip_bond_id;
 603        u8      chip_platform_type;
 604        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC      0x0UL
 605        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA      0x1UL
 606        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL
 607        #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST     VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM
 608        __le16  max_req_win_len;
 609        __le16  max_resp_len;
 610        __le16  def_req_timeout;
 611        u8      flags;
 612        #define VER_GET_RESP_FLAGS_DEV_NOT_RDY                   0x1UL
 613        #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL                 0x2UL
 614        #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE     0x4UL
 615        u8      unused_0[2];
 616        u8      always_1;
 617        __le16  hwrm_intf_major;
 618        __le16  hwrm_intf_minor;
 619        __le16  hwrm_intf_build;
 620        __le16  hwrm_intf_patch;
 621        __le16  hwrm_fw_major;
 622        __le16  hwrm_fw_minor;
 623        __le16  hwrm_fw_build;
 624        __le16  hwrm_fw_patch;
 625        __le16  mgmt_fw_major;
 626        __le16  mgmt_fw_minor;
 627        __le16  mgmt_fw_build;
 628        __le16  mgmt_fw_patch;
 629        __le16  netctrl_fw_major;
 630        __le16  netctrl_fw_minor;
 631        __le16  netctrl_fw_build;
 632        __le16  netctrl_fw_patch;
 633        __le16  roce_fw_major;
 634        __le16  roce_fw_minor;
 635        __le16  roce_fw_build;
 636        __le16  roce_fw_patch;
 637        __le16  max_ext_req_len;
 638        __le16  max_req_timeout;
 639        u8      unused_1[3];
 640        u8      valid;
 641};
 642
 643/* eject_cmpl (size:128b/16B) */
 644struct eject_cmpl {
 645        __le16  type;
 646        #define EJECT_CMPL_TYPE_MASK       0x3fUL
 647        #define EJECT_CMPL_TYPE_SFT        0
 648        #define EJECT_CMPL_TYPE_STAT_EJECT   0x1aUL
 649        #define EJECT_CMPL_TYPE_LAST        EJECT_CMPL_TYPE_STAT_EJECT
 650        #define EJECT_CMPL_FLAGS_MASK      0xffc0UL
 651        #define EJECT_CMPL_FLAGS_SFT       6
 652        #define EJECT_CMPL_FLAGS_ERROR      0x40UL
 653        __le16  len;
 654        __le32  opaque;
 655        __le16  v;
 656        #define EJECT_CMPL_V                              0x1UL
 657        #define EJECT_CMPL_ERRORS_MASK                    0xfffeUL
 658        #define EJECT_CMPL_ERRORS_SFT                     1
 659        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_MASK        0xeUL
 660        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_SFT         1
 661        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER     (0x0UL << 1)
 662        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT   (0x1UL << 1)
 663        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT    (0x3UL << 1)
 664        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH         (0x5UL << 1)
 665        #define EJECT_CMPL_ERRORS_BUFFER_ERROR_LAST         EJECT_CMPL_ERRORS_BUFFER_ERROR_FLUSH
 666        __le16  reserved16;
 667        __le32  unused_2;
 668};
 669
 670/* hwrm_cmpl (size:128b/16B) */
 671struct hwrm_cmpl {
 672        __le16  type;
 673        #define CMPL_TYPE_MASK     0x3fUL
 674        #define CMPL_TYPE_SFT      0
 675        #define CMPL_TYPE_HWRM_DONE  0x20UL
 676        #define CMPL_TYPE_LAST      CMPL_TYPE_HWRM_DONE
 677        __le16  sequence_id;
 678        __le32  unused_1;
 679        __le32  v;
 680        #define CMPL_V     0x1UL
 681        __le32  unused_3;
 682};
 683
 684/* hwrm_fwd_req_cmpl (size:128b/16B) */
 685struct hwrm_fwd_req_cmpl {
 686        __le16  req_len_type;
 687        #define FWD_REQ_CMPL_TYPE_MASK        0x3fUL
 688        #define FWD_REQ_CMPL_TYPE_SFT         0
 689        #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ  0x22UL
 690        #define FWD_REQ_CMPL_TYPE_LAST         FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ
 691        #define FWD_REQ_CMPL_REQ_LEN_MASK     0xffc0UL
 692        #define FWD_REQ_CMPL_REQ_LEN_SFT      6
 693        __le16  source_id;
 694        __le32  unused0;
 695        __le32  req_buf_addr_v[2];
 696        #define FWD_REQ_CMPL_V                0x1UL
 697        #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL
 698        #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1
 699};
 700
 701/* hwrm_fwd_resp_cmpl (size:128b/16B) */
 702struct hwrm_fwd_resp_cmpl {
 703        __le16  type;
 704        #define FWD_RESP_CMPL_TYPE_MASK         0x3fUL
 705        #define FWD_RESP_CMPL_TYPE_SFT          0
 706        #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP  0x24UL
 707        #define FWD_RESP_CMPL_TYPE_LAST          FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP
 708        __le16  source_id;
 709        __le16  resp_len;
 710        __le16  unused_1;
 711        __le32  resp_buf_addr_v[2];
 712        #define FWD_RESP_CMPL_V                 0x1UL
 713        #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL
 714        #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1
 715};
 716
 717/* hwrm_async_event_cmpl (size:128b/16B) */
 718struct hwrm_async_event_cmpl {
 719        __le16  type;
 720        #define ASYNC_EVENT_CMPL_TYPE_MASK            0x3fUL
 721        #define ASYNC_EVENT_CMPL_TYPE_SFT             0
 722        #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 723        #define ASYNC_EVENT_CMPL_TYPE_LAST             ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT
 724        __le16  event_id;
 725        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE         0x0UL
 726        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE            0x1UL
 727        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE          0x2UL
 728        #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE          0x3UL
 729        #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED      0x4UL
 730        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL
 731        #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE      0x6UL
 732        #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE        0x7UL
 733        #define ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY               0x8UL
 734        #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY             0x9UL
 735        #define ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG           0xaUL
 736        #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD           0x10UL
 737        #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD             0x11UL
 738        #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT        0x12UL
 739        #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD             0x20UL
 740        #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD               0x21UL
 741        #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR                     0x30UL
 742        #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE         0x31UL
 743        #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE   0x32UL
 744        #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE              0x33UL
 745        #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE            0x34UL
 746        #define ASYNC_EVENT_CMPL_EVENT_ID_DEFAULT_VNIC_CHANGE        0x35UL
 747        #define ASYNC_EVENT_CMPL_EVENT_ID_HW_FLOW_AGED               0x36UL
 748        #define ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION         0x37UL
 749        #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_REQ        0x38UL
 750        #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CACHE_FLUSH_DONE       0x39UL
 751        #define ASYNC_EVENT_CMPL_EVENT_ID_TCP_FLAG_ACTION_CHANGE     0x3aUL
 752        #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_FLOW_ACTIVE            0x3bUL
 753        #define ASYNC_EVENT_CMPL_EVENT_ID_EEM_CFG_CHANGE             0x3cUL
 754        #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_DEFAULT_VNIC_CHANGE  0x3dUL
 755        #define ASYNC_EVENT_CMPL_EVENT_ID_TFLIB_LINK_STATUS_CHANGE   0x3eUL
 756        #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE               0x3fUL
 757        #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE          0x40UL
 758        #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE    0x41UL
 759        #define ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST               0x42UL
 760        #define ASYNC_EVENT_CMPL_EVENT_ID_PHC_MASTER                 0x43UL
 761        #define ASYNC_EVENT_CMPL_EVENT_ID_PPS_TIMESTAMP              0x44UL
 762        #define ASYNC_EVENT_CMPL_EVENT_ID_ERROR_REPORT               0x45UL
 763        #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID          0x46UL
 764        #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG               0xfeUL
 765        #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                 0xffUL
 766        #define ASYNC_EVENT_CMPL_EVENT_ID_LAST                      ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
 767        __le32  event_data2;
 768        u8      opaque_v;
 769        #define ASYNC_EVENT_CMPL_V          0x1UL
 770        #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL
 771        #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1
 772        u8      timestamp_lo;
 773        __le16  timestamp_hi;
 774        __le32  event_data1;
 775};
 776
 777/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */
 778struct hwrm_async_event_cmpl_link_status_change {
 779        __le16  type;
 780        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK            0x3fUL
 781        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT             0
 782        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 783        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT
 784        __le16  event_id;
 785        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL
 786        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST              ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE
 787        __le32  event_data2;
 788        u8      opaque_v;
 789        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V          0x1UL
 790        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL
 791        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1
 792        u8      timestamp_lo;
 793        __le16  timestamp_hi;
 794        __le32  event_data1;
 795        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE     0x1UL
 796        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN  0x0UL
 797        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP    0x1UL
 798        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP
 799        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK       0xeUL
 800        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT        1
 801        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK    0xffff0UL
 802        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT     4
 803        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_MASK      0xff00000UL
 804        #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PF_ID_SFT       20
 805};
 806
 807/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */
 808struct hwrm_async_event_cmpl_port_conn_not_allowed {
 809        __le16  type;
 810        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK            0x3fUL
 811        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT             0
 812        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 813        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST             ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT
 814        __le16  event_id;
 815        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL
 816        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED
 817        __le32  event_data2;
 818        u8      opaque_v;
 819        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V          0x1UL
 820        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL
 821        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1
 822        u8      timestamp_lo;
 823        __le16  timestamp_hi;
 824        __le32  event_data1;
 825        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK                 0xffffUL
 826        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT                  0
 827        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK      0xff0000UL
 828        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT       16
 829        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE        (0x0UL << 16)
 830        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX   (0x1UL << 16)
 831        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG  (0x2UL << 16)
 832        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN     (0x3UL << 16)
 833        #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST       ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN
 834};
 835
 836/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */
 837struct hwrm_async_event_cmpl_link_speed_cfg_change {
 838        __le16  type;
 839        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK            0x3fUL
 840        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT             0
 841        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 842        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 843        __le16  event_id;
 844        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL
 845        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST                 ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE
 846        __le32  event_data2;
 847        u8      opaque_v;
 848        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V          0x1UL
 849        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL
 850        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1
 851        u8      timestamp_lo;
 852        __le16  timestamp_hi;
 853        __le32  event_data1;
 854        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK                     0xffffUL
 855        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT                      0
 856        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE     0x10000UL
 857        #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG           0x20000UL
 858};
 859
 860/* hwrm_async_event_cmpl_reset_notify (size:128b/16B) */
 861struct hwrm_async_event_cmpl_reset_notify {
 862        __le16  type;
 863        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_MASK            0x3fUL
 864        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_SFT             0
 865        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 866        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_LAST             ASYNC_EVENT_CMPL_RESET_NOTIFY_TYPE_HWRM_ASYNC_EVENT
 867        __le16  event_id;
 868        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL
 869        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST        ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY
 870        __le32  event_data2;
 871        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL
 872        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0
 873        u8      opaque_v;
 874        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V          0x1UL
 875        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL
 876        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_SFT 1
 877        u8      timestamp_lo;
 878        __le16  timestamp_hi;
 879        __le32  event_data1;
 880        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_MASK                  0xffUL
 881        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_SFT                   0
 882        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_STOP_TX_QUEUE    0x1UL
 883        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN           0x2UL
 884        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_LAST                   ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DRIVER_ACTION_DRIVER_IFDOWN
 885        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK                    0xff00UL
 886        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_SFT                     8
 887        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST  (0x1UL << 8)
 888        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL        (0x2UL << 8)
 889        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL    (0x3UL << 8)
 890        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET                (0x4UL << 8)
 891        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION             (0x5UL << 8)
 892        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST                     ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION
 893        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK           0xffff0000UL
 894        #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT            16
 895};
 896
 897/* hwrm_async_event_cmpl_error_recovery (size:128b/16B) */
 898struct hwrm_async_event_cmpl_error_recovery {
 899        __le16  type;
 900        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_MASK            0x3fUL
 901        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_SFT             0
 902        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 903        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_RECOVERY_TYPE_HWRM_ASYNC_EVENT
 904        __le16  event_id;
 905        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY 0x9UL
 906        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_LAST          ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_ID_ERROR_RECOVERY
 907        __le32  event_data2;
 908        u8      opaque_v;
 909        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_V          0x1UL
 910        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_MASK 0xfeUL
 911        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_OPAQUE_SFT 1
 912        u8      timestamp_lo;
 913        __le16  timestamp_hi;
 914        __le32  event_data1;
 915        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASK                 0xffUL
 916        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_SFT                  0
 917        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC           0x1UL
 918        #define ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED      0x2UL
 919};
 920
 921/* hwrm_async_event_cmpl_ring_monitor_msg (size:128b/16B) */
 922struct hwrm_async_event_cmpl_ring_monitor_msg {
 923        __le16  type;
 924        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_MASK            0x3fUL
 925        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_SFT             0
 926        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 927        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_LAST             ASYNC_EVENT_CMPL_RING_MONITOR_MSG_TYPE_HWRM_ASYNC_EVENT
 928        __le16  event_id;
 929        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG 0xaUL
 930        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_LAST            ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_ID_RING_MONITOR_MSG
 931        __le32  event_data2;
 932        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK 0xffUL
 933        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_SFT 0
 934        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_TX    0x0UL
 935        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX    0x1UL
 936        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL  0x2UL
 937        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_LAST ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_CMPL
 938        u8      opaque_v;
 939        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_V          0x1UL
 940        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_MASK 0xfeUL
 941        #define ASYNC_EVENT_CMPL_RING_MONITOR_MSG_OPAQUE_SFT 1
 942        u8      timestamp_lo;
 943        __le16  timestamp_hi;
 944        __le32  event_data1;
 945};
 946
 947/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */
 948struct hwrm_async_event_cmpl_vf_cfg_change {
 949        __le16  type;
 950        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK            0x3fUL
 951        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT             0
 952        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 953        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT
 954        __le16  event_id;
 955        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL
 956        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST         ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE
 957        __le32  event_data2;
 958        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_MASK 0xffffUL
 959        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA2_VF_ID_SFT 0
 960        u8      opaque_v;
 961        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V          0x1UL
 962        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL
 963        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1
 964        u8      timestamp_lo;
 965        __le16  timestamp_hi;
 966        __le32  event_data1;
 967        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE                0x1UL
 968        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE                0x2UL
 969        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE      0x4UL
 970        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE          0x8UL
 971        #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_TRUSTED_VF_CFG_CHANGE     0x10UL
 972};
 973
 974/* hwrm_async_event_cmpl_default_vnic_change (size:128b/16B) */
 975struct hwrm_async_event_cmpl_default_vnic_change {
 976        __le16  type;
 977        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_MASK            0x3fUL
 978        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_SFT             0
 979        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
 980        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_TYPE_HWRM_ASYNC_EVENT
 981        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_MASK         0xffc0UL
 982        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_UNUSED1_SFT          6
 983        __le16  event_id;
 984        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION 0x35UL
 985        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_LAST                   ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_ID_ALLOC_FREE_NOTIFICATION
 986        __le32  event_data2;
 987        u8      opaque_v;
 988        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_V          0x1UL
 989        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_MASK 0xfeUL
 990        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_OPAQUE_SFT 1
 991        u8      timestamp_lo;
 992        __le16  timestamp_hi;
 993        __le32  event_data1;
 994        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_MASK          0x3UL
 995        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_SFT           0
 996        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_ALLOC  0x1UL
 997        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE   0x2UL
 998        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_LAST           ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_DEF_VNIC_STATE_DEF_VNIC_FREE
 999        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_MASK                   0x3fcUL
1000        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_PF_ID_SFT                    2
1001        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_MASK                   0x3fffc00UL
1002        #define ASYNC_EVENT_CMPL_DEFAULT_VNIC_CHANGE_EVENT_DATA1_VF_ID_SFT                    10
1003};
1004
1005/* hwrm_async_event_cmpl_hw_flow_aged (size:128b/16B) */
1006struct hwrm_async_event_cmpl_hw_flow_aged {
1007        __le16  type;
1008        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_MASK            0x3fUL
1009        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_SFT             0
1010        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1011        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_LAST             ASYNC_EVENT_CMPL_HW_FLOW_AGED_TYPE_HWRM_ASYNC_EVENT
1012        __le16  event_id;
1013        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED 0x36UL
1014        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_LAST        ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_ID_HW_FLOW_AGED
1015        __le32  event_data2;
1016        u8      opaque_v;
1017        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_V          0x1UL
1018        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_MASK 0xfeUL
1019        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_OPAQUE_SFT 1
1020        u8      timestamp_lo;
1021        __le16  timestamp_hi;
1022        __le32  event_data1;
1023        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_MASK       0x7fffffffUL
1024        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_ID_SFT        0
1025        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION     0x80000000UL
1026        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_RX    (0x0UL << 31)
1027        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX    (0x1UL << 31)
1028        #define ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_LAST ASYNC_EVENT_CMPL_HW_FLOW_AGED_EVENT_DATA1_FLOW_DIRECTION_TX
1029};
1030
1031/* hwrm_async_event_cmpl_eem_cache_flush_req (size:128b/16B) */
1032struct hwrm_async_event_cmpl_eem_cache_flush_req {
1033        __le16  type;
1034        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_MASK            0x3fUL
1035        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_SFT             0
1036        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1037        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_TYPE_HWRM_ASYNC_EVENT
1038        __le16  event_id;
1039        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ 0x38UL
1040        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_LAST               ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_EVENT_ID_EEM_CACHE_FLUSH_REQ
1041        __le32  event_data2;
1042        u8      opaque_v;
1043        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_V          0x1UL
1044        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_MASK 0xfeUL
1045        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_REQ_OPAQUE_SFT 1
1046        u8      timestamp_lo;
1047        __le16  timestamp_hi;
1048        __le32  event_data1;
1049};
1050
1051/* hwrm_async_event_cmpl_eem_cache_flush_done (size:128b/16B) */
1052struct hwrm_async_event_cmpl_eem_cache_flush_done {
1053        __le16  type;
1054        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_MASK            0x3fUL
1055        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_SFT             0
1056        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1057        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_LAST             ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_TYPE_HWRM_ASYNC_EVENT
1058        __le16  event_id;
1059        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE 0x39UL
1060        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_LAST                ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_ID_EEM_CACHE_FLUSH_DONE
1061        __le32  event_data2;
1062        u8      opaque_v;
1063        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_V          0x1UL
1064        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_MASK 0xfeUL
1065        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_OPAQUE_SFT 1
1066        u8      timestamp_lo;
1067        __le16  timestamp_hi;
1068        __le32  event_data1;
1069        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_MASK 0xffffUL
1070        #define ASYNC_EVENT_CMPL_EEM_CACHE_FLUSH_DONE_EVENT_DATA1_FID_SFT 0
1071};
1072
1073/* hwrm_async_event_cmpl_deferred_response (size:128b/16B) */
1074struct hwrm_async_event_cmpl_deferred_response {
1075        __le16  type;
1076        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_MASK            0x3fUL
1077        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_SFT             0
1078        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1079        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_TYPE_HWRM_ASYNC_EVENT
1080        __le16  event_id;
1081        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE 0x40UL
1082        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_LAST             ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_ID_DEFERRED_RESPONSE
1083        __le32  event_data2;
1084        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_MASK 0xffffUL
1085        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_EVENT_DATA2_SEQ_ID_SFT 0
1086        u8      opaque_v;
1087        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_V          0x1UL
1088        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_MASK 0xfeUL
1089        #define ASYNC_EVENT_CMPL_DEFERRED_RESPONSE_OPAQUE_SFT 1
1090        u8      timestamp_lo;
1091        __le16  timestamp_hi;
1092        __le32  event_data1;
1093};
1094
1095/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */
1096struct hwrm_async_event_cmpl_echo_request {
1097        __le16  type;
1098        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK            0x3fUL
1099        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT             0
1100        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1101        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST             ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT
1102        __le16  event_id;
1103        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST 0x42UL
1104        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST
1105        __le32  event_data2;
1106        u8      opaque_v;
1107        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_V          0x1UL
1108        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK 0xfeUL
1109        #define ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1
1110        u8      timestamp_lo;
1111        __le16  timestamp_hi;
1112        __le32  event_data1;
1113};
1114
1115/* hwrm_async_event_cmpl_phc_master (size:128b/16B) */
1116struct hwrm_async_event_cmpl_phc_master {
1117        __le16  type;
1118        #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_MASK            0x3fUL
1119        #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_SFT             0
1120        #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1121        #define ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_LAST             ASYNC_EVENT_CMPL_PHC_MASTER_TYPE_HWRM_ASYNC_EVENT
1122        __le16  event_id;
1123        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER 0x43UL
1124        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_LAST      ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_ID_PHC_MASTER
1125        __le32  event_data2;
1126        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_MASK 0xffffUL
1127        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_MASTER_FID_SFT 0
1128        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_MASK   0xffff0000UL
1129        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA2_PHC_SEC_FID_SFT    16
1130        u8      opaque_v;
1131        #define ASYNC_EVENT_CMPL_PHC_MASTER_V          0x1UL
1132        #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_MASK 0xfeUL
1133        #define ASYNC_EVENT_CMPL_PHC_MASTER_OPAQUE_SFT 1
1134        u8      timestamp_lo;
1135        __le16  timestamp_hi;
1136        __le32  event_data1;
1137        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_MASK         0xfUL
1138        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_SFT          0
1139        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_MASTER     0x1UL
1140        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_SECONDARY  0x2UL
1141        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER   0x3UL
1142        #define ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_LAST          ASYNC_EVENT_CMPL_PHC_MASTER_EVENT_DATA1_FLAGS_PHC_FAILOVER
1143};
1144
1145/* hwrm_async_event_cmpl_pps_timestamp (size:128b/16B) */
1146struct hwrm_async_event_cmpl_pps_timestamp {
1147        __le16  type;
1148        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_MASK            0x3fUL
1149        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_SFT             0
1150        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1151        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_LAST             ASYNC_EVENT_CMPL_PPS_TIMESTAMP_TYPE_HWRM_ASYNC_EVENT
1152        __le16  event_id;
1153        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP 0x44UL
1154        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_LAST         ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_ID_PPS_TIMESTAMP
1155        __le32  event_data2;
1156        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE              0x1UL
1157        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_INTERNAL       0x0UL
1158        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL       0x1UL
1159        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_LAST          ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE_EXTERNAL
1160        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK         0xeUL
1161        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT          1
1162        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK 0xffff0UL
1163        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT 4
1164        u8      opaque_v;
1165        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_V          0x1UL
1166        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_MASK 0xfeUL
1167        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_OPAQUE_SFT 1
1168        u8      timestamp_lo;
1169        __le16  timestamp_hi;
1170        __le32  event_data1;
1171        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK 0xffffffffUL
1172        #define ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT 0
1173};
1174
1175/* hwrm_async_event_cmpl_error_report (size:128b/16B) */
1176struct hwrm_async_event_cmpl_error_report {
1177        __le16  type;
1178        #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_MASK            0x3fUL
1179        #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_SFT             0
1180        #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1181        #define ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_TYPE_HWRM_ASYNC_EVENT
1182        __le16  event_id;
1183        #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT 0x45UL
1184        #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_ID_ERROR_REPORT
1185        __le32  event_data2;
1186        u8      opaque_v;
1187        #define ASYNC_EVENT_CMPL_ERROR_REPORT_V          0x1UL
1188        #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_MASK 0xfeUL
1189        #define ASYNC_EVENT_CMPL_ERROR_REPORT_OPAQUE_SFT 1
1190        u8      timestamp_lo;
1191        __le16  timestamp_hi;
1192        __le32  event_data1;
1193        #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_MASK 0xffUL
1194        #define ASYNC_EVENT_CMPL_ERROR_REPORT_EVENT_DATA1_ERROR_TYPE_SFT 0
1195};
1196
1197/* hwrm_async_event_cmpl_hwrm_error (size:128b/16B) */
1198struct hwrm_async_event_cmpl_hwrm_error {
1199        __le16  type;
1200        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_MASK            0x3fUL
1201        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_SFT             0
1202        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1203        #define ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_LAST             ASYNC_EVENT_CMPL_HWRM_ERROR_TYPE_HWRM_ASYNC_EVENT
1204        __le16  event_id;
1205        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR 0xffUL
1206        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_LAST      ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_ID_HWRM_ERROR
1207        __le32  event_data2;
1208        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_MASK    0xffUL
1209        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_SFT     0
1210        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_WARNING   0x0UL
1211        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_NONFATAL  0x1UL
1212        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL     0x2UL
1213        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_LAST     ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA2_SEVERITY_FATAL
1214        u8      opaque_v;
1215        #define ASYNC_EVENT_CMPL_HWRM_ERROR_V          0x1UL
1216        #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_MASK 0xfeUL
1217        #define ASYNC_EVENT_CMPL_HWRM_ERROR_OPAQUE_SFT 1
1218        u8      timestamp_lo;
1219        __le16  timestamp_hi;
1220        __le32  event_data1;
1221        #define ASYNC_EVENT_CMPL_HWRM_ERROR_EVENT_DATA1_TIMESTAMP     0x1UL
1222};
1223
1224/* hwrm_async_event_cmpl_error_report_base (size:128b/16B) */
1225struct hwrm_async_event_cmpl_error_report_base {
1226        __le16  type;
1227        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_MASK            0x3fUL
1228        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_SFT             0
1229        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1230        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_TYPE_HWRM_ASYNC_EVENT
1231        __le16  event_id;
1232        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT 0x45UL
1233        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_ID_ERROR_REPORT
1234        __le32  event_data2;
1235        u8      opaque_v;
1236        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_V          0x1UL
1237        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_MASK 0xfeUL
1238        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_OPAQUE_SFT 1
1239        u8      timestamp_lo;
1240        __le16  timestamp_hi;
1241        __le32  event_data1;
1242        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK                   0xffUL
1243        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT                    0
1244        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_RESERVED                 0x0UL
1245        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM              0x1UL
1246        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL           0x2UL
1247        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_NVM                      0x3UL
1248        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD  0x4UL
1249        #define ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_LAST                    ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_DOORBELL_DROP_THRESHOLD
1250};
1251
1252/* hwrm_async_event_cmpl_error_report_pause_storm (size:128b/16B) */
1253struct hwrm_async_event_cmpl_error_report_pause_storm {
1254        __le16  type;
1255        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_MASK            0x3fUL
1256        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_SFT             0
1257        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1258        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_TYPE_HWRM_ASYNC_EVENT
1259        __le16  event_id;
1260        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT 0x45UL
1261        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_ID_ERROR_REPORT
1262        __le32  event_data2;
1263        u8      opaque_v;
1264        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_V          0x1UL
1265        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_MASK 0xfeUL
1266        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_OPAQUE_SFT 1
1267        u8      timestamp_lo;
1268        __le16  timestamp_hi;
1269        __le32  event_data1;
1270        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_MASK       0xffUL
1271        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_SFT        0
1272        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM  0x1UL
1273        #define ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_PAUSE_STORM_EVENT_DATA1_ERROR_TYPE_PAUSE_STORM
1274};
1275
1276/* hwrm_async_event_cmpl_error_report_invalid_signal (size:128b/16B) */
1277struct hwrm_async_event_cmpl_error_report_invalid_signal {
1278        __le16  type;
1279        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_MASK            0x3fUL
1280        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_SFT             0
1281        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1282        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_TYPE_HWRM_ASYNC_EVENT
1283        __le16  event_id;
1284        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT 0x45UL
1285        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_ID_ERROR_REPORT
1286        __le32  event_data2;
1287        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK 0xffUL
1288        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT 0
1289        u8      opaque_v;
1290        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_V          0x1UL
1291        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_MASK 0xfeUL
1292        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_OPAQUE_SFT 1
1293        u8      timestamp_lo;
1294        __le16  timestamp_hi;
1295        __le32  event_data1;
1296        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_MASK          0xffUL
1297        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_SFT           0
1298        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL  0x2UL
1299        #define ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_LAST           ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA1_ERROR_TYPE_INVALID_SIGNAL
1300};
1301
1302/* hwrm_async_event_cmpl_error_report_nvm (size:128b/16B) */
1303struct hwrm_async_event_cmpl_error_report_nvm {
1304        __le16  type;
1305        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_MASK            0x3fUL
1306        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_SFT             0
1307        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT  0x2eUL
1308        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_LAST             ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_TYPE_HWRM_ASYNC_EVENT
1309        __le16  event_id;
1310        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT 0x45UL
1311        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_LAST        ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_ID_ERROR_REPORT
1312        __le32  event_data2;
1313        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK 0xffffffffUL
1314        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT 0
1315        u8      opaque_v;
1316        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_V          0x1UL
1317        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_MASK 0xfeUL
1318        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_OPAQUE_SFT 1
1319        u8      timestamp_lo;
1320        __le16  timestamp_hi;
1321        __le32  event_data1;
1322        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_MASK     0xffUL
1323        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_SFT      0
1324        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR  0x3UL
1325        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_LAST      ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_ERROR_TYPE_NVM_ERROR
1326        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK   0xff00UL
1327        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_SFT    8
1328        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE    (0x1UL << 8)
1329        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE    (0x2UL << 8)
1330        #define ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_LAST    ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE
1331};
1332
1333/* hwrm_func_reset_input (size:192b/24B) */
1334struct hwrm_func_reset_input {
1335        __le16  req_type;
1336        __le16  cmpl_ring;
1337        __le16  seq_id;
1338        __le16  target_id;
1339        __le64  resp_addr;
1340        __le32  enables;
1341        #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID     0x1UL
1342        __le16  vf_id;
1343        u8      func_reset_level;
1344        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL      0x0UL
1345        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME       0x1UL
1346        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL
1347        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF       0x3UL
1348        #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST         FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF
1349        u8      unused_0;
1350};
1351
1352/* hwrm_func_reset_output (size:128b/16B) */
1353struct hwrm_func_reset_output {
1354        __le16  error_code;
1355        __le16  req_type;
1356        __le16  seq_id;
1357        __le16  resp_len;
1358        u8      unused_0[7];
1359        u8      valid;
1360};
1361
1362/* hwrm_func_getfid_input (size:192b/24B) */
1363struct hwrm_func_getfid_input {
1364        __le16  req_type;
1365        __le16  cmpl_ring;
1366        __le16  seq_id;
1367        __le16  target_id;
1368        __le64  resp_addr;
1369        __le32  enables;
1370        #define FUNC_GETFID_REQ_ENABLES_PCI_ID     0x1UL
1371        __le16  pci_id;
1372        u8      unused_0[2];
1373};
1374
1375/* hwrm_func_getfid_output (size:128b/16B) */
1376struct hwrm_func_getfid_output {
1377        __le16  error_code;
1378        __le16  req_type;
1379        __le16  seq_id;
1380        __le16  resp_len;
1381        __le16  fid;
1382        u8      unused_0[5];
1383        u8      valid;
1384};
1385
1386/* hwrm_func_vf_alloc_input (size:192b/24B) */
1387struct hwrm_func_vf_alloc_input {
1388        __le16  req_type;
1389        __le16  cmpl_ring;
1390        __le16  seq_id;
1391        __le16  target_id;
1392        __le64  resp_addr;
1393        __le32  enables;
1394        #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID     0x1UL
1395        __le16  first_vf_id;
1396        __le16  num_vfs;
1397};
1398
1399/* hwrm_func_vf_alloc_output (size:128b/16B) */
1400struct hwrm_func_vf_alloc_output {
1401        __le16  error_code;
1402        __le16  req_type;
1403        __le16  seq_id;
1404        __le16  resp_len;
1405        __le16  first_vf_id;
1406        u8      unused_0[5];
1407        u8      valid;
1408};
1409
1410/* hwrm_func_vf_free_input (size:192b/24B) */
1411struct hwrm_func_vf_free_input {
1412        __le16  req_type;
1413        __le16  cmpl_ring;
1414        __le16  seq_id;
1415        __le16  target_id;
1416        __le64  resp_addr;
1417        __le32  enables;
1418        #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID     0x1UL
1419        __le16  first_vf_id;
1420        __le16  num_vfs;
1421};
1422
1423/* hwrm_func_vf_free_output (size:128b/16B) */
1424struct hwrm_func_vf_free_output {
1425        __le16  error_code;
1426        __le16  req_type;
1427        __le16  seq_id;
1428        __le16  resp_len;
1429        u8      unused_0[7];
1430        u8      valid;
1431};
1432
1433/* hwrm_func_vf_cfg_input (size:448b/56B) */
1434struct hwrm_func_vf_cfg_input {
1435        __le16  req_type;
1436        __le16  cmpl_ring;
1437        __le16  seq_id;
1438        __le16  target_id;
1439        __le64  resp_addr;
1440        __le32  enables;
1441        #define FUNC_VF_CFG_REQ_ENABLES_MTU                  0x1UL
1442        #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN           0x2UL
1443        #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR       0x4UL
1444        #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR        0x8UL
1445        #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS      0x10UL
1446        #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS       0x20UL
1447        #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS         0x40UL
1448        #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS         0x80UL
1449        #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS          0x100UL
1450        #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS            0x200UL
1451        #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS        0x400UL
1452        #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS     0x800UL
1453        #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_KEY_CTXS      0x1000UL
1454        #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_KEY_CTXS      0x2000UL
1455        __le16  mtu;
1456        __le16  guest_vlan;
1457        __le16  async_event_cr;
1458        u8      dflt_mac_addr[6];
1459        __le32  flags;
1460        #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST             0x1UL
1461        #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST             0x2UL
1462        #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST           0x4UL
1463        #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST     0x8UL
1464        #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST       0x10UL
1465        #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST       0x20UL
1466        #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST           0x40UL
1467        #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST         0x80UL
1468        #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE       0x100UL
1469        #define FUNC_VF_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE      0x200UL
1470        __le16  num_rsscos_ctxs;
1471        __le16  num_cmpl_rings;
1472        __le16  num_tx_rings;
1473        __le16  num_rx_rings;
1474        __le16  num_l2_ctxs;
1475        __le16  num_vnics;
1476        __le16  num_stat_ctxs;
1477        __le16  num_hw_ring_grps;
1478        __le16  num_tx_key_ctxs;
1479        __le16  num_rx_key_ctxs;
1480};
1481
1482/* hwrm_func_vf_cfg_output (size:128b/16B) */
1483struct hwrm_func_vf_cfg_output {
1484        __le16  error_code;
1485        __le16  req_type;
1486        __le16  seq_id;
1487        __le16  resp_len;
1488        u8      unused_0[7];
1489        u8      valid;
1490};
1491
1492/* hwrm_func_qcaps_input (size:192b/24B) */
1493struct hwrm_func_qcaps_input {
1494        __le16  req_type;
1495        __le16  cmpl_ring;
1496        __le16  seq_id;
1497        __le16  target_id;
1498        __le64  resp_addr;
1499        __le16  fid;
1500        u8      unused_0[6];
1501};
1502
1503/* hwrm_func_qcaps_output (size:768b/96B) */
1504struct hwrm_func_qcaps_output {
1505        __le16  error_code;
1506        __le16  req_type;
1507        __le16  seq_id;
1508        __le16  resp_len;
1509        __le16  fid;
1510        __le16  port_id;
1511        __le32  flags;
1512        #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED                   0x1UL
1513        #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING               0x2UL
1514        #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED                         0x4UL
1515        #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED                     0x8UL
1516        #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED                     0x10UL
1517        #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED                0x20UL
1518        #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED                     0x40UL
1519        #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED                  0x80UL
1520        #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED                   0x100UL
1521        #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED               0x200UL
1522        #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED                   0x400UL
1523        #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED            0x800UL
1524        #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED            0x1000UL
1525        #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED             0x2000UL
1526        #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED               0x4000UL
1527        #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED              0x8000UL
1528        #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED                  0x10000UL
1529        #define FUNC_QCAPS_RESP_FLAGS_ADOPTED_PF_SUPPORTED                  0x20000UL
1530        #define FUNC_QCAPS_RESP_FLAGS_ADMIN_PF_SUPPORTED                    0x40000UL
1531        #define FUNC_QCAPS_RESP_FLAGS_LINK_ADMIN_STATUS_SUPPORTED           0x80000UL
1532        #define FUNC_QCAPS_RESP_FLAGS_WCB_PUSH_MODE                         0x100000UL
1533        #define FUNC_QCAPS_RESP_FLAGS_DYNAMIC_TX_RING_ALLOC                 0x200000UL
1534        #define FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE                     0x400000UL
1535        #define FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE                0x800000UL
1536        #define FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED                   0x1000000UL
1537        #define FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD                    0x2000000UL
1538        #define FUNC_QCAPS_RESP_FLAGS_NOTIFY_VF_DEF_VNIC_CHNG_SUPPORTED     0x4000000UL
1539        #define FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED         0x8000000UL
1540        #define FUNC_QCAPS_RESP_FLAGS_COREDUMP_CMD_SUPPORTED                0x10000000UL
1541        #define FUNC_QCAPS_RESP_FLAGS_CRASHDUMP_CMD_SUPPORTED               0x20000000UL
1542        #define FUNC_QCAPS_RESP_FLAGS_PFC_WD_STATS_SUPPORTED                0x40000000UL
1543        #define FUNC_QCAPS_RESP_FLAGS_DBG_QCAPS_CMD_SUPPORTED               0x80000000UL
1544        u8      mac_address[6];
1545        __le16  max_rsscos_ctx;
1546        __le16  max_cmpl_rings;
1547        __le16  max_tx_rings;
1548        __le16  max_rx_rings;
1549        __le16  max_l2_ctxs;
1550        __le16  max_vnics;
1551        __le16  first_vf_id;
1552        __le16  max_vfs;
1553        __le16  max_stat_ctx;
1554        __le32  max_encap_records;
1555        __le32  max_decap_records;
1556        __le32  max_tx_em_flows;
1557        __le32  max_tx_wm_flows;
1558        __le32  max_rx_em_flows;
1559        __le32  max_rx_wm_flows;
1560        __le32  max_mcast_filters;
1561        __le32  max_flow_id;
1562        __le32  max_hw_ring_grps;
1563        __le16  max_sp_tx_rings;
1564        __le16  max_msix_vfs;
1565        __le32  flags_ext;
1566        #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_MARK_SUPPORTED                     0x1UL
1567        #define FUNC_QCAPS_RESP_FLAGS_EXT_ECN_STATS_SUPPORTED                    0x2UL
1568        #define FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED                 0x4UL
1569        #define FUNC_QCAPS_RESP_FLAGS_EXT_HOT_RESET_IF_SUPPORT                   0x8UL
1570        #define FUNC_QCAPS_RESP_FLAGS_EXT_PROXY_MODE_SUPPORT                     0x10UL
1571        #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT     0x20UL
1572        #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED                         0x40UL
1573        #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED                0x80UL
1574        #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED             0x100UL
1575        #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED                      0x200UL
1576        #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED                 0x400UL
1577        #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE                     0x800UL
1578        #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_METADATA_CFG_CAPABLE                0x1000UL
1579        #define FUNC_QCAPS_RESP_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED            0x2000UL
1580        #define FUNC_QCAPS_RESP_FLAGS_EXT_BD_METADATA_SUPPORTED                  0x4000UL
1581        #define FUNC_QCAPS_RESP_FLAGS_EXT_ECHO_REQUEST_SUPPORTED                 0x8000UL
1582        #define FUNC_QCAPS_RESP_FLAGS_EXT_NPAR_1_2_SUPPORTED                     0x10000UL
1583        #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PTM_SUPPORTED                      0x20000UL
1584        #define FUNC_QCAPS_RESP_FLAGS_EXT_PTP_PPS_SUPPORTED                      0x40000UL
1585        #define FUNC_QCAPS_RESP_FLAGS_EXT_VF_CFG_ASYNC_FOR_PF_SUPPORTED          0x80000UL
1586        #define FUNC_QCAPS_RESP_FLAGS_EXT_PARTITION_BW_SUPPORTED                 0x100000UL
1587        #define FUNC_QCAPS_RESP_FLAGS_EXT_DFLT_VLAN_TPID_PCP_SUPPORTED           0x200000UL
1588        #define FUNC_QCAPS_RESP_FLAGS_EXT_KTLS_SUPPORTED                         0x400000UL
1589        #define FUNC_QCAPS_RESP_FLAGS_EXT_EP_RATE_CONTROL                        0x800000UL
1590        u8      max_schqs;
1591        u8      mpc_chnls_cap;
1592        #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE         0x1UL
1593        #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RCE         0x2UL
1594        #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TE_CFA      0x4UL
1595        #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_RE_CFA      0x8UL
1596        #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_PRIMATE     0x10UL
1597        __le16  max_key_ctxs_alloc;
1598        u8      unused_1[7];
1599        u8      valid;
1600};
1601
1602/* hwrm_func_qcfg_input (size:192b/24B) */
1603struct hwrm_func_qcfg_input {
1604        __le16  req_type;
1605        __le16  cmpl_ring;
1606        __le16  seq_id;
1607        __le16  target_id;
1608        __le64  resp_addr;
1609        __le16  fid;
1610        u8      unused_0[6];
1611};
1612
1613/* hwrm_func_qcfg_output (size:896b/112B) */
1614struct hwrm_func_qcfg_output {
1615        __le16  error_code;
1616        __le16  req_type;
1617        __le16  seq_id;
1618        __le16  resp_len;
1619        __le16  fid;
1620        __le16  port_id;
1621        __le16  vlan;
1622        __le16  flags;
1623        #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED     0x1UL
1624        #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED          0x2UL
1625        #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED        0x4UL
1626        #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED     0x8UL
1627        #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED        0x10UL
1628        #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST                   0x20UL
1629        #define FUNC_QCFG_RESP_FLAGS_TRUSTED_VF                   0x40UL
1630        #define FUNC_QCFG_RESP_FLAGS_SECURE_MODE_ENABLED          0x80UL
1631        #define FUNC_QCFG_RESP_FLAGS_PREBOOT_LEGACY_L2_RINGS      0x100UL
1632        #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED            0x200UL
1633        #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED        0x400UL
1634        #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED         0x800UL
1635        #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED           0x1000UL
1636        #define FUNC_QCFG_RESP_FLAGS_MULTI_ROOT                   0x2000UL
1637        #define FUNC_QCFG_RESP_FLAGS_ENABLE_RDMA_SRIOV            0x4000UL
1638        u8      mac_address[6];
1639        __le16  pci_id;
1640        __le16  alloc_rsscos_ctx;
1641        __le16  alloc_cmpl_rings;
1642        __le16  alloc_tx_rings;
1643        __le16  alloc_rx_rings;
1644        __le16  alloc_l2_ctx;
1645        __le16  alloc_vnics;
1646        __le16  admin_mtu;
1647        __le16  mru;
1648        __le16  stat_ctx_id;
1649        u8      port_partition_type;
1650        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF     0x0UL
1651        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS    0x1UL
1652        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL
1653        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL
1654        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL
1655        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_2 0x5UL
1656        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL
1657        #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST   FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN
1658        u8      port_pf_cnt;
1659        #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL
1660        #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST   FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL
1661        __le16  dflt_vnic_id;
1662        __le16  max_mtu_configured;
1663        __le32  min_bw;
1664        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1665        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT              0
1666        #define FUNC_QCFG_RESP_MIN_BW_SCALE                     0x10000000UL
1667        #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1668        #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1669        #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES
1670        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1671        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT         29
1672        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1673        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1674        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1675        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1676        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1677        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1678        #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID
1679        __le32  max_bw;
1680        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1681        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT              0
1682        #define FUNC_QCFG_RESP_MAX_BW_SCALE                     0x10000000UL
1683        #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1684        #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1685        #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES
1686        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1687        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT         29
1688        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1689        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1690        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1691        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1692        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1693        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1694        #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID
1695        u8      evb_mode;
1696        #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL
1697        #define FUNC_QCFG_RESP_EVB_MODE_VEB    0x1UL
1698        #define FUNC_QCFG_RESP_EVB_MODE_VEPA   0x2UL
1699        #define FUNC_QCFG_RESP_EVB_MODE_LAST  FUNC_QCFG_RESP_EVB_MODE_VEPA
1700        u8      options;
1701        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
1702        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT          0
1703        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
1704        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
1705        #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST          FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128
1706        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
1707        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_SFT        2
1708        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
1709        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
1710        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
1711        #define FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_QCFG_RESP_OPTIONS_LINK_ADMIN_STATE_AUTO
1712        #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK                   0xf0UL
1713        #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT                    4
1714        __le16  alloc_vfs;
1715        __le32  alloc_mcast_filters;
1716        __le32  alloc_hw_ring_grps;
1717        __le16  alloc_sp_tx_rings;
1718        __le16  alloc_stat_ctx;
1719        __le16  alloc_msix;
1720        __le16  registered_vfs;
1721        __le16  l2_doorbell_bar_size_kb;
1722        u8      unused_1;
1723        u8      always_1;
1724        __le32  reset_addr_poll;
1725        __le16  legacy_l2_db_size_kb;
1726        __le16  svif_info;
1727        #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_MASK      0x7fffUL
1728        #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_SFT       0
1729        #define FUNC_QCFG_RESP_SVIF_INFO_SVIF_VALID     0x8000UL
1730        u8      mpc_chnls;
1731        #define FUNC_QCFG_RESP_MPC_CHNLS_TCE_ENABLED         0x1UL
1732        #define FUNC_QCFG_RESP_MPC_CHNLS_RCE_ENABLED         0x2UL
1733        #define FUNC_QCFG_RESP_MPC_CHNLS_TE_CFA_ENABLED      0x4UL
1734        #define FUNC_QCFG_RESP_MPC_CHNLS_RE_CFA_ENABLED      0x8UL
1735        #define FUNC_QCFG_RESP_MPC_CHNLS_PRIMATE_ENABLED     0x10UL
1736        u8      unused_2[3];
1737        __le32  partition_min_bw;
1738        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1739        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_SFT              0
1740        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE                     0x10000000UL
1741        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1742        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1743        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_LAST                 FUNC_QCFG_RESP_PARTITION_MIN_BW_SCALE_BYTES
1744        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1745        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT         29
1746        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1747        #define FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
1748        __le32  partition_max_bw;
1749        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1750        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_SFT              0
1751        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE                     0x10000000UL
1752        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1753        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1754        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_LAST                 FUNC_QCFG_RESP_PARTITION_MAX_BW_SCALE_BYTES
1755        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1756        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT         29
1757        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1758        #define FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_QCFG_RESP_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
1759        __le16  host_mtu;
1760        __le16  alloc_tx_key_ctxs;
1761        __le16  alloc_rx_key_ctxs;
1762        u8      unused_3[5];
1763        u8      valid;
1764};
1765
1766/* hwrm_func_cfg_input (size:896b/112B) */
1767struct hwrm_func_cfg_input {
1768        __le16  req_type;
1769        __le16  cmpl_ring;
1770        __le16  seq_id;
1771        __le16  target_id;
1772        __le64  resp_addr;
1773        __le16  fid;
1774        __le16  num_msix;
1775        __le32  flags;
1776        #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE     0x1UL
1777        #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE      0x2UL
1778        #define FUNC_CFG_REQ_FLAGS_RSVD_MASK                      0x1fcUL
1779        #define FUNC_CFG_REQ_FLAGS_RSVD_SFT                       2
1780        #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE        0x200UL
1781        #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE       0x400UL
1782        #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST               0x800UL
1783        #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC         0x1000UL
1784        #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST                 0x2000UL
1785        #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST                 0x4000UL
1786        #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST               0x8000UL
1787        #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST         0x10000UL
1788        #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST           0x20000UL
1789        #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST           0x40000UL
1790        #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST               0x80000UL
1791        #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST             0x100000UL
1792        #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_ENABLE              0x200000UL
1793        #define FUNC_CFG_REQ_FLAGS_DYNAMIC_TX_RING_ALLOC          0x400000UL
1794        #define FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST                 0x800000UL
1795        #define FUNC_CFG_REQ_FLAGS_TRUSTED_VF_DISABLE             0x1000000UL
1796        #define FUNC_CFG_REQ_FLAGS_PREBOOT_LEGACY_L2_RINGS        0x2000000UL
1797        #define FUNC_CFG_REQ_FLAGS_HOT_RESET_IF_EN_DIS            0x4000000UL
1798        #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_ENABLE           0x8000000UL
1799        #define FUNC_CFG_REQ_FLAGS_PPP_PUSH_MODE_DISABLE          0x10000000UL
1800        #define FUNC_CFG_REQ_FLAGS_BD_METADATA_ENABLE             0x20000000UL
1801        #define FUNC_CFG_REQ_FLAGS_BD_METADATA_DISABLE            0x40000000UL
1802        __le32  enables;
1803        #define FUNC_CFG_REQ_ENABLES_ADMIN_MTU                0x1UL
1804        #define FUNC_CFG_REQ_ENABLES_MRU                      0x2UL
1805        #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS          0x4UL
1806        #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS           0x8UL
1807        #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS             0x10UL
1808        #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS             0x20UL
1809        #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS              0x40UL
1810        #define FUNC_CFG_REQ_ENABLES_NUM_VNICS                0x80UL
1811        #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS            0x100UL
1812        #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR            0x200UL
1813        #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN                0x400UL
1814        #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR             0x800UL
1815        #define FUNC_CFG_REQ_ENABLES_MIN_BW                   0x1000UL
1816        #define FUNC_CFG_REQ_ENABLES_MAX_BW                   0x2000UL
1817        #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR           0x4000UL
1818        #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE      0x8000UL
1819        #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS        0x10000UL
1820        #define FUNC_CFG_REQ_ENABLES_EVB_MODE                 0x20000UL
1821        #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS        0x40000UL
1822        #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS         0x80000UL
1823        #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE           0x100000UL
1824        #define FUNC_CFG_REQ_ENABLES_NUM_MSIX                 0x200000UL
1825        #define FUNC_CFG_REQ_ENABLES_ADMIN_LINK_STATE         0x400000UL
1826        #define FUNC_CFG_REQ_ENABLES_HOT_RESET_IF_SUPPORT     0x800000UL
1827        #define FUNC_CFG_REQ_ENABLES_SCHQ_ID                  0x1000000UL
1828        #define FUNC_CFG_REQ_ENABLES_MPC_CHNLS                0x2000000UL
1829        #define FUNC_CFG_REQ_ENABLES_PARTITION_MIN_BW         0x4000000UL
1830        #define FUNC_CFG_REQ_ENABLES_PARTITION_MAX_BW         0x8000000UL
1831        #define FUNC_CFG_REQ_ENABLES_TPID                     0x10000000UL
1832        #define FUNC_CFG_REQ_ENABLES_HOST_MTU                 0x20000000UL
1833        #define FUNC_CFG_REQ_ENABLES_TX_KEY_CTXS              0x40000000UL
1834        #define FUNC_CFG_REQ_ENABLES_RX_KEY_CTXS              0x80000000UL
1835        __le16  admin_mtu;
1836        __le16  mru;
1837        __le16  num_rsscos_ctxs;
1838        __le16  num_cmpl_rings;
1839        __le16  num_tx_rings;
1840        __le16  num_rx_rings;
1841        __le16  num_l2_ctxs;
1842        __le16  num_vnics;
1843        __le16  num_stat_ctxs;
1844        __le16  num_hw_ring_grps;
1845        u8      dflt_mac_addr[6];
1846        __le16  dflt_vlan;
1847        __be32  dflt_ip_addr[4];
1848        __le32  min_bw;
1849        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1850        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT              0
1851        #define FUNC_CFG_REQ_MIN_BW_SCALE                     0x10000000UL
1852        #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1853        #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1854        #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_MIN_BW_SCALE_BYTES
1855        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1856        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT         29
1857        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1858        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1859        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1860        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1861        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1862        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1863        #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID
1864        __le32  max_bw;
1865        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1866        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT              0
1867        #define FUNC_CFG_REQ_MAX_BW_SCALE                     0x10000000UL
1868        #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1869        #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1870        #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_MAX_BW_SCALE_BYTES
1871        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1872        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT         29
1873        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA          (0x0UL << 29)
1874        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO          (0x2UL << 29)
1875        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE          (0x4UL << 29)
1876        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA          (0x6UL << 29)
1877        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1878        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID       (0x7UL << 29)
1879        #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID
1880        __le16  async_event_cr;
1881        u8      vlan_antispoof_mode;
1882        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK                 0x0UL
1883        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN           0x1UL
1884        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE       0x2UL
1885        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL
1886        #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST                   FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN
1887        u8      allowed_vlan_pris;
1888        u8      evb_mode;
1889        #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL
1890        #define FUNC_CFG_REQ_EVB_MODE_VEB    0x1UL
1891        #define FUNC_CFG_REQ_EVB_MODE_VEPA   0x2UL
1892        #define FUNC_CFG_REQ_EVB_MODE_LAST  FUNC_CFG_REQ_EVB_MODE_VEPA
1893        u8      options;
1894        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK         0x3UL
1895        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT          0
1896        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64        0x0UL
1897        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128       0x1UL
1898        #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST          FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128
1899        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_MASK       0xcUL
1900        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_SFT        2
1901        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_DOWN  (0x0UL << 2)
1902        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_FORCED_UP    (0x1UL << 2)
1903        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO         (0x2UL << 2)
1904        #define FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_LAST        FUNC_CFG_REQ_OPTIONS_LINK_ADMIN_STATE_AUTO
1905        #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK                   0xf0UL
1906        #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT                    4
1907        __le16  num_mcast_filters;
1908        __le16  schq_id;
1909        __le16  mpc_chnls;
1910        #define FUNC_CFG_REQ_MPC_CHNLS_TCE_ENABLE          0x1UL
1911        #define FUNC_CFG_REQ_MPC_CHNLS_TCE_DISABLE         0x2UL
1912        #define FUNC_CFG_REQ_MPC_CHNLS_RCE_ENABLE          0x4UL
1913        #define FUNC_CFG_REQ_MPC_CHNLS_RCE_DISABLE         0x8UL
1914        #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_ENABLE       0x10UL
1915        #define FUNC_CFG_REQ_MPC_CHNLS_TE_CFA_DISABLE      0x20UL
1916        #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_ENABLE       0x40UL
1917        #define FUNC_CFG_REQ_MPC_CHNLS_RE_CFA_DISABLE      0x80UL
1918        #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_ENABLE      0x100UL
1919        #define FUNC_CFG_REQ_MPC_CHNLS_PRIMATE_DISABLE     0x200UL
1920        __le32  partition_min_bw;
1921        #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_MASK             0xfffffffUL
1922        #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_SFT              0
1923        #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE                     0x10000000UL
1924        #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BITS                  (0x0UL << 28)
1925        #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES                 (0x1UL << 28)
1926        #define FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_LAST                 FUNC_CFG_REQ_PARTITION_MIN_BW_SCALE_BYTES
1927        #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1928        #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_SFT         29
1929        #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1930        #define FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_PARTITION_MIN_BW_BW_VALUE_UNIT_PERCENT1_100
1931        __le32  partition_max_bw;
1932        #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_MASK             0xfffffffUL
1933        #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_SFT              0
1934        #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE                     0x10000000UL
1935        #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BITS                  (0x0UL << 28)
1936        #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES                 (0x1UL << 28)
1937        #define FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_LAST                 FUNC_CFG_REQ_PARTITION_MAX_BW_SCALE_BYTES
1938        #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_MASK        0xe0000000UL
1939        #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_SFT         29
1940        #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100  (0x1UL << 29)
1941        #define FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_LAST         FUNC_CFG_REQ_PARTITION_MAX_BW_BW_VALUE_UNIT_PERCENT1_100
1942        __be16  tpid;
1943        __le16  host_mtu;
1944        __le16  num_tx_key_ctxs;
1945        __le16  num_rx_key_ctxs;
1946        u8      unused_0[4];
1947};
1948
1949/* hwrm_func_cfg_output (size:128b/16B) */
1950struct hwrm_func_cfg_output {
1951        __le16  error_code;
1952        __le16  req_type;
1953        __le16  seq_id;
1954        __le16  resp_len;
1955        u8      unused_0[7];
1956        u8      valid;
1957};
1958
1959/* hwrm_func_qstats_input (size:192b/24B) */
1960struct hwrm_func_qstats_input {
1961        __le16  req_type;
1962        __le16  cmpl_ring;
1963        __le16  seq_id;
1964        __le16  target_id;
1965        __le64  resp_addr;
1966        __le16  fid;
1967        u8      flags;
1968        #define FUNC_QSTATS_REQ_FLAGS_UNUSED       0x0UL
1969        #define FUNC_QSTATS_REQ_FLAGS_ROCE_ONLY    0x1UL
1970        #define FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK 0x2UL
1971        #define FUNC_QSTATS_REQ_FLAGS_LAST        FUNC_QSTATS_REQ_FLAGS_COUNTER_MASK
1972        u8      unused_0[5];
1973};
1974
1975/* hwrm_func_qstats_output (size:1408b/176B) */
1976struct hwrm_func_qstats_output {
1977        __le16  error_code;
1978        __le16  req_type;
1979        __le16  seq_id;
1980        __le16  resp_len;
1981        __le64  tx_ucast_pkts;
1982        __le64  tx_mcast_pkts;
1983        __le64  tx_bcast_pkts;
1984        __le64  tx_discard_pkts;
1985        __le64  tx_drop_pkts;
1986        __le64  tx_ucast_bytes;
1987        __le64  tx_mcast_bytes;
1988        __le64  tx_bcast_bytes;
1989        __le64  rx_ucast_pkts;
1990        __le64  rx_mcast_pkts;
1991        __le64  rx_bcast_pkts;
1992        __le64  rx_discard_pkts;
1993        __le64  rx_drop_pkts;
1994        __le64  rx_ucast_bytes;
1995        __le64  rx_mcast_bytes;
1996        __le64  rx_bcast_bytes;
1997        __le64  rx_agg_pkts;
1998        __le64  rx_agg_bytes;
1999        __le64  rx_agg_events;
2000        __le64  rx_agg_aborts;
2001        u8      unused_0[7];
2002        u8      valid;
2003};
2004
2005/* hwrm_func_qstats_ext_input (size:256b/32B) */
2006struct hwrm_func_qstats_ext_input {
2007        __le16  req_type;
2008        __le16  cmpl_ring;
2009        __le16  seq_id;
2010        __le16  target_id;
2011        __le64  resp_addr;
2012        __le16  fid;
2013        u8      flags;
2014        #define FUNC_QSTATS_EXT_REQ_FLAGS_UNUSED       0x0UL
2015        #define FUNC_QSTATS_EXT_REQ_FLAGS_ROCE_ONLY    0x1UL
2016        #define FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK 0x2UL
2017        #define FUNC_QSTATS_EXT_REQ_FLAGS_LAST        FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK
2018        u8      unused_0[1];
2019        __le32  enables;
2020        #define FUNC_QSTATS_EXT_REQ_ENABLES_SCHQ_ID     0x1UL
2021        __le16  schq_id;
2022        __le16  traffic_class;
2023        u8      unused_1[4];
2024};
2025
2026/* hwrm_func_qstats_ext_output (size:1536b/192B) */
2027struct hwrm_func_qstats_ext_output {
2028        __le16  error_code;
2029        __le16  req_type;
2030        __le16  seq_id;
2031        __le16  resp_len;
2032        __le64  rx_ucast_pkts;
2033        __le64  rx_mcast_pkts;
2034        __le64  rx_bcast_pkts;
2035        __le64  rx_discard_pkts;
2036        __le64  rx_error_pkts;
2037        __le64  rx_ucast_bytes;
2038        __le64  rx_mcast_bytes;
2039        __le64  rx_bcast_bytes;
2040        __le64  tx_ucast_pkts;
2041        __le64  tx_mcast_pkts;
2042        __le64  tx_bcast_pkts;
2043        __le64  tx_error_pkts;
2044        __le64  tx_discard_pkts;
2045        __le64  tx_ucast_bytes;
2046        __le64  tx_mcast_bytes;
2047        __le64  tx_bcast_bytes;
2048        __le64  rx_tpa_eligible_pkt;
2049        __le64  rx_tpa_eligible_bytes;
2050        __le64  rx_tpa_pkt;
2051        __le64  rx_tpa_bytes;
2052        __le64  rx_tpa_errors;
2053        __le64  rx_tpa_events;
2054        u8      unused_0[7];
2055        u8      valid;
2056};
2057
2058/* hwrm_func_clr_stats_input (size:192b/24B) */
2059struct hwrm_func_clr_stats_input {
2060        __le16  req_type;
2061        __le16  cmpl_ring;
2062        __le16  seq_id;
2063        __le16  target_id;
2064        __le64  resp_addr;
2065        __le16  fid;
2066        u8      unused_0[6];
2067};
2068
2069/* hwrm_func_clr_stats_output (size:128b/16B) */
2070struct hwrm_func_clr_stats_output {
2071        __le16  error_code;
2072        __le16  req_type;
2073        __le16  seq_id;
2074        __le16  resp_len;
2075        u8      unused_0[7];
2076        u8      valid;
2077};
2078
2079/* hwrm_func_vf_resc_free_input (size:192b/24B) */
2080struct hwrm_func_vf_resc_free_input {
2081        __le16  req_type;
2082        __le16  cmpl_ring;
2083        __le16  seq_id;
2084        __le16  target_id;
2085        __le64  resp_addr;
2086        __le16  vf_id;
2087        u8      unused_0[6];
2088};
2089
2090/* hwrm_func_vf_resc_free_output (size:128b/16B) */
2091struct hwrm_func_vf_resc_free_output {
2092        __le16  error_code;
2093        __le16  req_type;
2094        __le16  seq_id;
2095        __le16  resp_len;
2096        u8      unused_0[7];
2097        u8      valid;
2098};
2099
2100/* hwrm_func_drv_rgtr_input (size:896b/112B) */
2101struct hwrm_func_drv_rgtr_input {
2102        __le16  req_type;
2103        __le16  cmpl_ring;
2104        __le16  seq_id;
2105        __le16  target_id;
2106        __le64  resp_addr;
2107        __le32  flags;
2108        #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE                     0x1UL
2109        #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE                    0x2UL
2110        #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE                   0x4UL
2111        #define FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE           0x8UL
2112        #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT                0x10UL
2113        #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT           0x20UL
2114        #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT                   0x40UL
2115        #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT               0x80UL
2116        #define FUNC_DRV_RGTR_REQ_FLAGS_RSS_STRICT_HASH_TYPE_SUPPORT     0x100UL
2117        #define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT                 0x200UL
2118        __le32  enables;
2119        #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL
2120        #define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL
2121        #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP           0x4UL
2122        #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD          0x8UL
2123        #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD     0x10UL
2124        __le16  os_type;
2125        #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN   0x0UL
2126        #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER     0x1UL
2127        #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS     0xeUL
2128        #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS   0x12UL
2129        #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS   0x1dUL
2130        #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX     0x24UL
2131        #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD   0x2aUL
2132        #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI      0x68UL
2133        #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864    0x73UL
2134        #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL
2135        #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI      0x8000UL
2136        #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST     FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI
2137        u8      ver_maj_8b;
2138        u8      ver_min_8b;
2139        u8      ver_upd_8b;
2140        u8      unused_0[3];
2141        __le32  timestamp;
2142        u8      unused_1[4];
2143        __le32  vf_req_fwd[8];
2144        __le32  async_event_fwd[8];
2145        __le16  ver_maj;
2146        __le16  ver_min;
2147        __le16  ver_upd;
2148        __le16  ver_patch;
2149};
2150
2151/* hwrm_func_drv_rgtr_output (size:128b/16B) */
2152struct hwrm_func_drv_rgtr_output {
2153        __le16  error_code;
2154        __le16  req_type;
2155        __le16  seq_id;
2156        __le16  resp_len;
2157        __le32  flags;
2158        #define FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED     0x1UL
2159        u8      unused_0[3];
2160        u8      valid;
2161};
2162
2163/* hwrm_func_drv_unrgtr_input (size:192b/24B) */
2164struct hwrm_func_drv_unrgtr_input {
2165        __le16  req_type;
2166        __le16  cmpl_ring;
2167        __le16  seq_id;
2168        __le16  target_id;
2169        __le64  resp_addr;
2170        __le32  flags;
2171        #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN     0x1UL
2172        u8      unused_0[4];
2173};
2174
2175/* hwrm_func_drv_unrgtr_output (size:128b/16B) */
2176struct hwrm_func_drv_unrgtr_output {
2177        __le16  error_code;
2178        __le16  req_type;
2179        __le16  seq_id;
2180        __le16  resp_len;
2181        u8      unused_0[7];
2182        u8      valid;
2183};
2184
2185/* hwrm_func_buf_rgtr_input (size:1024b/128B) */
2186struct hwrm_func_buf_rgtr_input {
2187        __le16  req_type;
2188        __le16  cmpl_ring;
2189        __le16  seq_id;
2190        __le16  target_id;
2191        __le64  resp_addr;
2192        __le32  enables;
2193        #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID            0x1UL
2194        #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR     0x2UL
2195        __le16  vf_id;
2196        __le16  req_buf_num_pages;
2197        __le16  req_buf_page_size;
2198        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL
2199        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K  0xcUL
2200        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K  0xdUL
2201        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL
2202        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M  0x15UL
2203        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M  0x16UL
2204        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G  0x1eUL
2205        #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G
2206        __le16  req_buf_len;
2207        __le16  resp_buf_len;
2208        u8      unused_0[2];
2209        __le64  req_buf_page_addr0;
2210        __le64  req_buf_page_addr1;
2211        __le64  req_buf_page_addr2;
2212        __le64  req_buf_page_addr3;
2213        __le64  req_buf_page_addr4;
2214        __le64  req_buf_page_addr5;
2215        __le64  req_buf_page_addr6;
2216        __le64  req_buf_page_addr7;
2217        __le64  req_buf_page_addr8;
2218        __le64  req_buf_page_addr9;
2219        __le64  error_buf_addr;
2220        __le64  resp_buf_addr;
2221};
2222
2223/* hwrm_func_buf_rgtr_output (size:128b/16B) */
2224struct hwrm_func_buf_rgtr_output {
2225        __le16  error_code;
2226        __le16  req_type;
2227        __le16  seq_id;
2228        __le16  resp_len;
2229        u8      unused_0[7];
2230        u8      valid;
2231};
2232
2233/* hwrm_func_drv_qver_input (size:192b/24B) */
2234struct hwrm_func_drv_qver_input {
2235        __le16  req_type;
2236        __le16  cmpl_ring;
2237        __le16  seq_id;
2238        __le16  target_id;
2239        __le64  resp_addr;
2240        __le32  reserved;
2241        __le16  fid;
2242        u8      unused_0[2];
2243};
2244
2245/* hwrm_func_drv_qver_output (size:256b/32B) */
2246struct hwrm_func_drv_qver_output {
2247        __le16  error_code;
2248        __le16  req_type;
2249        __le16  seq_id;
2250        __le16  resp_len;
2251        __le16  os_type;
2252        #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN   0x0UL
2253        #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER     0x1UL
2254        #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS     0xeUL
2255        #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS   0x12UL
2256        #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS   0x1dUL
2257        #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX     0x24UL
2258        #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD   0x2aUL
2259        #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI      0x68UL
2260        #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864    0x73UL
2261        #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL
2262        #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI      0x8000UL
2263        #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST     FUNC_DRV_QVER_RESP_OS_TYPE_UEFI
2264        u8      ver_maj_8b;
2265        u8      ver_min_8b;
2266        u8      ver_upd_8b;
2267        u8      unused_0[3];
2268        __le16  ver_maj;
2269        __le16  ver_min;
2270        __le16  ver_upd;
2271        __le16  ver_patch;
2272        u8      unused_1[7];
2273        u8      valid;
2274};
2275
2276/* hwrm_func_resource_qcaps_input (size:192b/24B) */
2277struct hwrm_func_resource_qcaps_input {
2278        __le16  req_type;
2279        __le16  cmpl_ring;
2280        __le16  seq_id;
2281        __le16  target_id;
2282        __le64  resp_addr;
2283        __le16  fid;
2284        u8      unused_0[6];
2285};
2286
2287/* hwrm_func_resource_qcaps_output (size:512b/64B) */
2288struct hwrm_func_resource_qcaps_output {
2289        __le16  error_code;
2290        __le16  req_type;
2291        __le16  seq_id;
2292        __le16  resp_len;
2293        __le16  max_vfs;
2294        __le16  max_msix;
2295        __le16  vf_reservation_strategy;
2296        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL        0x0UL
2297        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL        0x1UL
2298        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL
2299        #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST          FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC
2300        __le16  min_rsscos_ctx;
2301        __le16  max_rsscos_ctx;
2302        __le16  min_cmpl_rings;
2303        __le16  max_cmpl_rings;
2304        __le16  min_tx_rings;
2305        __le16  max_tx_rings;
2306        __le16  min_rx_rings;
2307        __le16  max_rx_rings;
2308        __le16  min_l2_ctxs;
2309        __le16  max_l2_ctxs;
2310        __le16  min_vnics;
2311        __le16  max_vnics;
2312        __le16  min_stat_ctx;
2313        __le16  max_stat_ctx;
2314        __le16  min_hw_ring_grps;
2315        __le16  max_hw_ring_grps;
2316        __le16  max_tx_scheduler_inputs;
2317        __le16  flags;
2318        #define FUNC_RESOURCE_QCAPS_RESP_FLAGS_MIN_GUARANTEED     0x1UL
2319        __le16  min_tx_key_ctxs;
2320        __le16  max_tx_key_ctxs;
2321        __le16  min_rx_key_ctxs;
2322        __le16  max_rx_key_ctxs;
2323        u8      unused_0[5];
2324        u8      valid;
2325};
2326
2327/* hwrm_func_vf_resource_cfg_input (size:512b/64B) */
2328struct hwrm_func_vf_resource_cfg_input {
2329        __le16  req_type;
2330        __le16  cmpl_ring;
2331        __le16  seq_id;
2332        __le16  target_id;
2333        __le64  resp_addr;
2334        __le16  vf_id;
2335        __le16  max_msix;
2336        __le16  min_rsscos_ctx;
2337        __le16  max_rsscos_ctx;
2338        __le16  min_cmpl_rings;
2339        __le16  max_cmpl_rings;
2340        __le16  min_tx_rings;
2341        __le16  max_tx_rings;
2342        __le16  min_rx_rings;
2343        __le16  max_rx_rings;
2344        __le16  min_l2_ctxs;
2345        __le16  max_l2_ctxs;
2346        __le16  min_vnics;
2347        __le16  max_vnics;
2348        __le16  min_stat_ctx;
2349        __le16  max_stat_ctx;
2350        __le16  min_hw_ring_grps;
2351        __le16  max_hw_ring_grps;
2352        __le16  flags;
2353        #define FUNC_VF_RESOURCE_CFG_REQ_FLAGS_MIN_GUARANTEED     0x1UL
2354        __le16  min_tx_key_ctxs;
2355        __le16  max_tx_key_ctxs;
2356        __le16  min_rx_key_ctxs;
2357        __le16  max_rx_key_ctxs;
2358        u8      unused_0[2];
2359};
2360
2361/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */
2362struct hwrm_func_vf_resource_cfg_output {
2363        __le16  error_code;
2364        __le16  req_type;
2365        __le16  seq_id;
2366        __le16  resp_len;
2367        __le16  reserved_rsscos_ctx;
2368        __le16  reserved_cmpl_rings;
2369        __le16  reserved_tx_rings;
2370        __le16  reserved_rx_rings;
2371        __le16  reserved_l2_ctxs;
2372        __le16  reserved_vnics;
2373        __le16  reserved_stat_ctx;
2374        __le16  reserved_hw_ring_grps;
2375        __le16  reserved_tx_key_ctxs;
2376        __le16  reserved_rx_key_ctxs;
2377        u8      unused_0[3];
2378        u8      valid;
2379};
2380
2381/* hwrm_func_backing_store_qcaps_input (size:128b/16B) */
2382struct hwrm_func_backing_store_qcaps_input {
2383        __le16  req_type;
2384        __le16  cmpl_ring;
2385        __le16  seq_id;
2386        __le16  target_id;
2387        __le64  resp_addr;
2388};
2389
2390/* hwrm_func_backing_store_qcaps_output (size:832b/104B) */
2391struct hwrm_func_backing_store_qcaps_output {
2392        __le16  error_code;
2393        __le16  req_type;
2394        __le16  seq_id;
2395        __le16  resp_len;
2396        __le32  qp_max_entries;
2397        __le16  qp_min_qp1_entries;
2398        __le16  qp_max_l2_entries;
2399        __le16  qp_entry_size;
2400        __le16  srq_max_l2_entries;
2401        __le32  srq_max_entries;
2402        __le16  srq_entry_size;
2403        __le16  cq_max_l2_entries;
2404        __le32  cq_max_entries;
2405        __le16  cq_entry_size;
2406        __le16  vnic_max_vnic_entries;
2407        __le16  vnic_max_ring_table_entries;
2408        __le16  vnic_entry_size;
2409        __le32  stat_max_entries;
2410        __le16  stat_entry_size;
2411        __le16  tqm_entry_size;
2412        __le32  tqm_min_entries_per_ring;
2413        __le32  tqm_max_entries_per_ring;
2414        __le32  mrav_max_entries;
2415        __le16  mrav_entry_size;
2416        __le16  tim_entry_size;
2417        __le32  tim_max_entries;
2418        __le16  mrav_num_entries_units;
2419        u8      tqm_entries_multiple;
2420        u8      ctx_kind_initializer;
2421        __le16  ctx_init_mask;
2422        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP       0x1UL
2423        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ      0x2UL
2424        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ       0x4UL
2425        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC     0x8UL
2426        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT     0x10UL
2427        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV     0x20UL
2428        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_TKC      0x40UL
2429        #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_RKC      0x80UL
2430        u8      qp_init_offset;
2431        u8      srq_init_offset;
2432        u8      cq_init_offset;
2433        u8      vnic_init_offset;
2434        u8      tqm_fp_rings_count;
2435        u8      stat_init_offset;
2436        u8      mrav_init_offset;
2437        u8      tqm_fp_rings_count_ext;
2438        u8      tkc_init_offset;
2439        u8      rkc_init_offset;
2440        __le16  tkc_entry_size;
2441        __le16  rkc_entry_size;
2442        __le32  tkc_max_entries;
2443        __le32  rkc_max_entries;
2444        u8      rsvd[7];
2445        u8      valid;
2446};
2447
2448/* tqm_fp_ring_cfg (size:128b/16B) */
2449struct tqm_fp_ring_cfg {
2450        u8      tqm_ring_pg_size_tqm_ring_lvl;
2451        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK      0xfUL
2452        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT       0
2453        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0       0x0UL
2454        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1       0x1UL
2455        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2       0x2UL
2456        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST       TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2
2457        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK  0xf0UL
2458        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT   4
2459        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
2460        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
2461        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
2462        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
2463        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
2464        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
2465        #define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST   TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G
2466        u8      unused[3];
2467        __le32  tqm_ring_num_entries;
2468        __le64  tqm_ring_page_dir;
2469};
2470
2471/* hwrm_func_backing_store_cfg_input (size:2688b/336B) */
2472struct hwrm_func_backing_store_cfg_input {
2473        __le16  req_type;
2474        __le16  cmpl_ring;
2475        __le16  seq_id;
2476        __le16  target_id;
2477        __le64  resp_addr;
2478        __le32  flags;
2479        #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE               0x1UL
2480        #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT     0x2UL
2481        __le32  enables;
2482        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP             0x1UL
2483        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ            0x2UL
2484        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ             0x4UL
2485        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC           0x8UL
2486        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT           0x10UL
2487        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP         0x20UL
2488        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0      0x40UL
2489        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1      0x80UL
2490        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2      0x100UL
2491        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3      0x200UL
2492        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4      0x400UL
2493        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5      0x800UL
2494        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6      0x1000UL
2495        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7      0x2000UL
2496        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV           0x4000UL
2497        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM            0x8000UL
2498        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8      0x10000UL
2499        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9      0x20000UL
2500        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10     0x40000UL
2501        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TKC            0x80000UL
2502        #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_RKC            0x100000UL
2503        u8      qpc_pg_size_qpc_lvl;
2504        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK      0xfUL
2505        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT       0
2506        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_0       0x0UL
2507        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_1       0x1UL
2508        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2       0x2UL
2509        #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_LVL_2
2510        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_MASK  0xf0UL
2511        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_SFT   4
2512        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_4K   (0x0UL << 4)
2513        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8K   (0x1UL << 4)
2514        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_64K  (0x2UL << 4)
2515        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_2M   (0x3UL << 4)
2516        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_8M   (0x4UL << 4)
2517        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G   (0x5UL << 4)
2518        #define FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_QPC_PG_SIZE_PG_1G
2519        u8      srq_pg_size_srq_lvl;
2520        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_MASK      0xfUL
2521        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_SFT       0
2522        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_0       0x0UL
2523        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_1       0x1UL
2524        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2       0x2UL
2525        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_SRQ_LVL_LVL_2
2526        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_MASK  0xf0UL
2527        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_SFT   4
2528        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_4K   (0x0UL << 4)
2529        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8K   (0x1UL << 4)
2530        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_64K  (0x2UL << 4)
2531        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_2M   (0x3UL << 4)
2532        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_8M   (0x4UL << 4)
2533        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G   (0x5UL << 4)
2534        #define FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_SRQ_PG_SIZE_PG_1G
2535        u8      cq_pg_size_cq_lvl;
2536        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_MASK      0xfUL
2537        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_SFT       0
2538        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_0       0x0UL
2539        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_1       0x1UL
2540        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2       0x2UL
2541        #define FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_CQ_LVL_LVL_2
2542        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_MASK  0xf0UL
2543        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_SFT   4
2544        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_4K   (0x0UL << 4)
2545        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8K   (0x1UL << 4)
2546        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_64K  (0x2UL << 4)
2547        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_2M   (0x3UL << 4)
2548        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_8M   (0x4UL << 4)
2549        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G   (0x5UL << 4)
2550        #define FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_CQ_PG_SIZE_PG_1G
2551        u8      vnic_pg_size_vnic_lvl;
2552        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_MASK      0xfUL
2553        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_SFT       0
2554        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_0       0x0UL
2555        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_1       0x1UL
2556        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2       0x2UL
2557        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_VNIC_LVL_LVL_2
2558        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_MASK  0xf0UL
2559        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_SFT   4
2560        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_4K   (0x0UL << 4)
2561        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8K   (0x1UL << 4)
2562        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_64K  (0x2UL << 4)
2563        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_2M   (0x3UL << 4)
2564        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_8M   (0x4UL << 4)
2565        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G   (0x5UL << 4)
2566        #define FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_VNIC_PG_SIZE_PG_1G
2567        u8      stat_pg_size_stat_lvl;
2568        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_MASK      0xfUL
2569        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_SFT       0
2570        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_0       0x0UL
2571        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_1       0x1UL
2572        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2       0x2UL
2573        #define FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_STAT_LVL_LVL_2
2574        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_MASK  0xf0UL
2575        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_SFT   4
2576        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_4K   (0x0UL << 4)
2577        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8K   (0x1UL << 4)
2578        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_64K  (0x2UL << 4)
2579        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_2M   (0x3UL << 4)
2580        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_8M   (0x4UL << 4)
2581        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G   (0x5UL << 4)
2582        #define FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_STAT_PG_SIZE_PG_1G
2583        u8      tqm_sp_pg_size_tqm_sp_lvl;
2584        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_MASK      0xfUL
2585        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_SFT       0
2586        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_0       0x0UL
2587        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_1       0x1UL
2588        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2       0x2UL
2589        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_SP_LVL_LVL_2
2590        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_MASK  0xf0UL
2591        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_SFT   4
2592        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_4K   (0x0UL << 4)
2593        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8K   (0x1UL << 4)
2594        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_64K  (0x2UL << 4)
2595        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_2M   (0x3UL << 4)
2596        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_8M   (0x4UL << 4)
2597        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G   (0x5UL << 4)
2598        #define FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_SP_PG_SIZE_PG_1G
2599        u8      tqm_ring0_pg_size_tqm_ring0_lvl;
2600        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_MASK      0xfUL
2601        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_SFT       0
2602        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_0       0x0UL
2603        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_1       0x1UL
2604        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2       0x2UL
2605        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_LVL_LVL_2
2606        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_MASK  0xf0UL
2607        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_SFT   4
2608        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_4K   (0x0UL << 4)
2609        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8K   (0x1UL << 4)
2610        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_64K  (0x2UL << 4)
2611        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_2M   (0x3UL << 4)
2612        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_8M   (0x4UL << 4)
2613        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G   (0x5UL << 4)
2614        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING0_PG_SIZE_PG_1G
2615        u8      tqm_ring1_pg_size_tqm_ring1_lvl;
2616        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_MASK      0xfUL
2617        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_SFT       0
2618        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_0       0x0UL
2619        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_1       0x1UL
2620        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2       0x2UL
2621        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_LVL_LVL_2
2622        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_MASK  0xf0UL
2623        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_SFT   4
2624        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_4K   (0x0UL << 4)
2625        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8K   (0x1UL << 4)
2626        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_64K  (0x2UL << 4)
2627        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_2M   (0x3UL << 4)
2628        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_8M   (0x4UL << 4)
2629        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G   (0x5UL << 4)
2630        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING1_PG_SIZE_PG_1G
2631        u8      tqm_ring2_pg_size_tqm_ring2_lvl;
2632        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_MASK      0xfUL
2633        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_SFT       0
2634        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_0       0x0UL
2635        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_1       0x1UL
2636        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2       0x2UL
2637        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_LVL_LVL_2
2638        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_MASK  0xf0UL
2639        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_SFT   4
2640        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_4K   (0x0UL << 4)
2641        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8K   (0x1UL << 4)
2642        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_64K  (0x2UL << 4)
2643        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_2M   (0x3UL << 4)
2644        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_8M   (0x4UL << 4)
2645        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G   (0x5UL << 4)
2646        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING2_PG_SIZE_PG_1G
2647        u8      tqm_ring3_pg_size_tqm_ring3_lvl;
2648        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_MASK      0xfUL
2649        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_SFT       0
2650        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_0       0x0UL
2651        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_1       0x1UL
2652        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2       0x2UL
2653        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_LVL_LVL_2
2654        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_MASK  0xf0UL
2655        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_SFT   4
2656        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_4K   (0x0UL << 4)
2657        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8K   (0x1UL << 4)
2658        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_64K  (0x2UL << 4)
2659        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_2M   (0x3UL << 4)
2660        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_8M   (0x4UL << 4)
2661        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G   (0x5UL << 4)
2662        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING3_PG_SIZE_PG_1G
2663        u8      tqm_ring4_pg_size_tqm_ring4_lvl;
2664        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_MASK      0xfUL
2665        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_SFT       0
2666        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_0       0x0UL
2667        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_1       0x1UL
2668        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2       0x2UL
2669        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_LVL_LVL_2
2670        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_MASK  0xf0UL
2671        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_SFT   4
2672        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_4K   (0x0UL << 4)
2673        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8K   (0x1UL << 4)
2674        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_64K  (0x2UL << 4)
2675        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_2M   (0x3UL << 4)
2676        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_8M   (0x4UL << 4)
2677        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G   (0x5UL << 4)
2678        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING4_PG_SIZE_PG_1G
2679        u8      tqm_ring5_pg_size_tqm_ring5_lvl;
2680        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_MASK      0xfUL
2681        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_SFT       0
2682        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_0       0x0UL
2683        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_1       0x1UL
2684        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2       0x2UL
2685        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_LVL_LVL_2
2686        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_MASK  0xf0UL
2687        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_SFT   4
2688        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_4K   (0x0UL << 4)
2689        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8K   (0x1UL << 4)
2690        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_64K  (0x2UL << 4)
2691        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_2M   (0x3UL << 4)
2692        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_8M   (0x4UL << 4)
2693        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G   (0x5UL << 4)
2694        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING5_PG_SIZE_PG_1G
2695        u8      tqm_ring6_pg_size_tqm_ring6_lvl;
2696        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_MASK      0xfUL
2697        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_SFT       0
2698        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_0       0x0UL
2699        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_1       0x1UL
2700        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2       0x2UL
2701        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_LVL_LVL_2
2702        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_MASK  0xf0UL
2703        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_SFT   4
2704        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_4K   (0x0UL << 4)
2705        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8K   (0x1UL << 4)
2706        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_64K  (0x2UL << 4)
2707        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_2M   (0x3UL << 4)
2708        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_8M   (0x4UL << 4)
2709        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G   (0x5UL << 4)
2710        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING6_PG_SIZE_PG_1G
2711        u8      tqm_ring7_pg_size_tqm_ring7_lvl;
2712        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_MASK      0xfUL
2713        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_SFT       0
2714        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_0       0x0UL
2715        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_1       0x1UL
2716        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2       0x2UL
2717        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_LVL_LVL_2
2718        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_MASK  0xf0UL
2719        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_SFT   4
2720        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_4K   (0x0UL << 4)
2721        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8K   (0x1UL << 4)
2722        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_64K  (0x2UL << 4)
2723        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_2M   (0x3UL << 4)
2724        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_8M   (0x4UL << 4)
2725        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G   (0x5UL << 4)
2726        #define FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TQM_RING7_PG_SIZE_PG_1G
2727        u8      mrav_pg_size_mrav_lvl;
2728        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_MASK      0xfUL
2729        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_SFT       0
2730        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_0       0x0UL
2731        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_1       0x1UL
2732        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2       0x2UL
2733        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_MRAV_LVL_LVL_2
2734        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_MASK  0xf0UL
2735        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_SFT   4
2736        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_4K   (0x0UL << 4)
2737        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8K   (0x1UL << 4)
2738        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_64K  (0x2UL << 4)
2739        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_2M   (0x3UL << 4)
2740        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_8M   (0x4UL << 4)
2741        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G   (0x5UL << 4)
2742        #define FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_MRAV_PG_SIZE_PG_1G
2743        u8      tim_pg_size_tim_lvl;
2744        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_MASK      0xfUL
2745        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_SFT       0
2746        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_0       0x0UL
2747        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_1       0x1UL
2748        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2       0x2UL
2749        #define FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TIM_LVL_LVL_2
2750        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_MASK  0xf0UL
2751        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_SFT   4
2752        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_4K   (0x0UL << 4)
2753        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8K   (0x1UL << 4)
2754        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_64K  (0x2UL << 4)
2755        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_2M   (0x3UL << 4)
2756        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_8M   (0x4UL << 4)
2757        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G   (0x5UL << 4)
2758        #define FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TIM_PG_SIZE_PG_1G
2759        __le64  qpc_page_dir;
2760        __le64  srq_page_dir;
2761        __le64  cq_page_dir;
2762        __le64  vnic_page_dir;
2763        __le64  stat_page_dir;
2764        __le64  tqm_sp_page_dir;
2765        __le64  tqm_ring0_page_dir;
2766        __le64  tqm_ring1_page_dir;
2767        __le64  tqm_ring2_page_dir;
2768        __le64  tqm_ring3_page_dir;
2769        __le64  tqm_ring4_page_dir;
2770        __le64  tqm_ring5_page_dir;
2771        __le64  tqm_ring6_page_dir;
2772        __le64  tqm_ring7_page_dir;
2773        __le64  mrav_page_dir;
2774        __le64  tim_page_dir;
2775        __le32  qp_num_entries;
2776        __le32  srq_num_entries;
2777        __le32  cq_num_entries;
2778        __le32  stat_num_entries;
2779        __le32  tqm_sp_num_entries;
2780        __le32  tqm_ring0_num_entries;
2781        __le32  tqm_ring1_num_entries;
2782        __le32  tqm_ring2_num_entries;
2783        __le32  tqm_ring3_num_entries;
2784        __le32  tqm_ring4_num_entries;
2785        __le32  tqm_ring5_num_entries;
2786        __le32  tqm_ring6_num_entries;
2787        __le32  tqm_ring7_num_entries;
2788        __le32  mrav_num_entries;
2789        __le32  tim_num_entries;
2790        __le16  qp_num_qp1_entries;
2791        __le16  qp_num_l2_entries;
2792        __le16  qp_entry_size;
2793        __le16  srq_num_l2_entries;
2794        __le16  srq_entry_size;
2795        __le16  cq_num_l2_entries;
2796        __le16  cq_entry_size;
2797        __le16  vnic_num_vnic_entries;
2798        __le16  vnic_num_ring_table_entries;
2799        __le16  vnic_entry_size;
2800        __le16  stat_entry_size;
2801        __le16  tqm_entry_size;
2802        __le16  mrav_entry_size;
2803        __le16  tim_entry_size;
2804        u8      tqm_ring8_pg_size_tqm_ring_lvl;
2805        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK      0xfUL
2806        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT       0
2807        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0       0x0UL
2808        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1       0x1UL
2809        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2       0x2UL
2810        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2
2811        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK  0xf0UL
2812        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT   4
2813        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
2814        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
2815        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
2816        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
2817        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
2818        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
2819        #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G
2820        u8      ring8_unused[3];
2821        __le32  tqm_ring8_num_entries;
2822        __le64  tqm_ring8_page_dir;
2823        u8      tqm_ring9_pg_size_tqm_ring_lvl;
2824        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK      0xfUL
2825        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT       0
2826        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0       0x0UL
2827        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1       0x1UL
2828        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2       0x2UL
2829        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2
2830        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK  0xf0UL
2831        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT   4
2832        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
2833        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
2834        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
2835        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
2836        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
2837        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
2838        #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G
2839        u8      ring9_unused[3];
2840        __le32  tqm_ring9_num_entries;
2841        __le64  tqm_ring9_page_dir;
2842        u8      tqm_ring10_pg_size_tqm_ring_lvl;
2843        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK      0xfUL
2844        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT       0
2845        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0       0x0UL
2846        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1       0x1UL
2847        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2       0x2UL
2848        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2
2849        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK  0xf0UL
2850        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT   4
2851        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K   (0x0UL << 4)
2852        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K   (0x1UL << 4)
2853        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K  (0x2UL << 4)
2854        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M   (0x3UL << 4)
2855        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M   (0x4UL << 4)
2856        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G   (0x5UL << 4)
2857        #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G
2858        u8      ring10_unused[3];
2859        __le32  tqm_ring10_num_entries;
2860        __le64  tqm_ring10_page_dir;
2861        __le32  tkc_num_entries;
2862        __le32  rkc_num_entries;
2863        __le64  tkc_page_dir;
2864        __le64  rkc_page_dir;
2865        __le16  tkc_entry_size;
2866        __le16  rkc_entry_size;
2867        u8      tkc_pg_size_tkc_lvl;
2868        #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_MASK      0xfUL
2869        #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_SFT       0
2870        #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_0       0x0UL
2871        #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_1       0x1UL
2872        #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2       0x2UL
2873        #define FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_TKC_LVL_LVL_2
2874        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_MASK  0xf0UL
2875        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_SFT   4
2876        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_4K   (0x0UL << 4)
2877        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8K   (0x1UL << 4)
2878        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_64K  (0x2UL << 4)
2879        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_2M   (0x3UL << 4)
2880        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_8M   (0x4UL << 4)
2881        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G   (0x5UL << 4)
2882        #define FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_TKC_PG_SIZE_PG_1G
2883        u8      rkc_pg_size_rkc_lvl;
2884        #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_MASK      0xfUL
2885        #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_SFT       0
2886        #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_0       0x0UL
2887        #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_1       0x1UL
2888        #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2       0x2UL
2889        #define FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LAST       FUNC_BACKING_STORE_CFG_REQ_RKC_LVL_LVL_2
2890        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_MASK  0xf0UL
2891        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_SFT   4
2892        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_4K   (0x0UL << 4)
2893        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8K   (0x1UL << 4)
2894        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_64K  (0x2UL << 4)
2895        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_2M   (0x3UL << 4)
2896        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_8M   (0x4UL << 4)
2897        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G   (0x5UL << 4)
2898        #define FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_LAST   FUNC_BACKING_STORE_CFG_REQ_RKC_PG_SIZE_PG_1G
2899        u8      rsvd[2];
2900};
2901
2902/* hwrm_func_backing_store_cfg_output (size:128b/16B) */
2903struct hwrm_func_backing_store_cfg_output {
2904        __le16  error_code;
2905        __le16  req_type;
2906        __le16  seq_id;
2907        __le16  resp_len;
2908        u8      unused_0[7];
2909        u8      valid;
2910};
2911
2912/* hwrm_error_recovery_qcfg_input (size:192b/24B) */
2913struct hwrm_error_recovery_qcfg_input {
2914        __le16  req_type;
2915        __le16  cmpl_ring;
2916        __le16  seq_id;
2917        __le16  target_id;
2918        __le64  resp_addr;
2919        u8      unused_0[8];
2920};
2921
2922/* hwrm_error_recovery_qcfg_output (size:1664b/208B) */
2923struct hwrm_error_recovery_qcfg_output {
2924        __le16  error_code;
2925        __le16  req_type;
2926        __le16  seq_id;
2927        __le16  resp_len;
2928        __le32  flags;
2929        #define ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST       0x1UL
2930        #define ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU     0x2UL
2931        __le32  driver_polling_freq;
2932        __le32  master_func_wait_period;
2933        __le32  normal_func_wait_period;
2934        __le32  master_func_wait_period_after_reset;
2935        __le32  max_bailout_time_after_reset;
2936        __le32  fw_health_status_reg;
2937        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_MASK    0x3UL
2938        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_SFT     0
2939        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2940        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_GRC       0x1UL
2941        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR0      0x2UL
2942        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1      0x3UL
2943        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SPACE_BAR1
2944        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_MASK          0xfffffffcUL
2945        #define ERROR_RECOVERY_QCFG_RESP_FW_HEALTH_STATUS_REG_ADDR_SFT           2
2946        __le32  fw_heartbeat_reg;
2947        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_MASK    0x3UL
2948        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_SFT     0
2949        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2950        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_GRC       0x1UL
2951        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR0      0x2UL
2952        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1      0x3UL
2953        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SPACE_BAR1
2954        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_MASK          0xfffffffcUL
2955        #define ERROR_RECOVERY_QCFG_RESP_FW_HEARTBEAT_REG_ADDR_SFT           2
2956        __le32  fw_reset_cnt_reg;
2957        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_MASK    0x3UL
2958        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_SFT     0
2959        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2960        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_GRC       0x1UL
2961        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR0      0x2UL
2962        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1      0x3UL
2963        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SPACE_BAR1
2964        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_MASK          0xfffffffcUL
2965        #define ERROR_RECOVERY_QCFG_RESP_FW_RESET_CNT_REG_ADDR_SFT           2
2966        __le32  reset_inprogress_reg;
2967        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_MASK    0x3UL
2968        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_SFT     0
2969        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2970        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_GRC       0x1UL
2971        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR0      0x2UL
2972        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1      0x3UL
2973        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SPACE_BAR1
2974        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_MASK          0xfffffffcUL
2975        #define ERROR_RECOVERY_QCFG_RESP_RESET_INPROGRESS_REG_ADDR_SFT           2
2976        __le32  reset_inprogress_reg_mask;
2977        u8      unused_0[3];
2978        u8      reg_array_cnt;
2979        __le32  reset_reg[16];
2980        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_MASK    0x3UL
2981        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_SFT     0
2982        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2983        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_GRC       0x1UL
2984        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR0      0x2UL
2985        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1      0x3UL
2986        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SPACE_BAR1
2987        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_MASK          0xfffffffcUL
2988        #define ERROR_RECOVERY_QCFG_RESP_RESET_REG_ADDR_SFT           2
2989        __le32  reset_reg_val[16];
2990        u8      delay_after_reset[16];
2991        __le32  err_recovery_cnt_reg;
2992        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_MASK    0x3UL
2993        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_SFT     0
2994        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_PCIE_CFG  0x0UL
2995        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_GRC       0x1UL
2996        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR0      0x2UL
2997        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1      0x3UL
2998        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_LAST     ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SPACE_BAR1
2999        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_MASK          0xfffffffcUL
3000        #define ERROR_RECOVERY_QCFG_RESP_ERR_RECOVERY_CNT_REG_ADDR_SFT           2
3001        u8      unused_1[3];
3002        u8      valid;
3003};
3004
3005/* hwrm_func_echo_response_input (size:192b/24B) */
3006struct hwrm_func_echo_response_input {
3007        __le16  req_type;
3008        __le16  cmpl_ring;
3009        __le16  seq_id;
3010        __le16  target_id;
3011        __le64  resp_addr;
3012        __le32  event_data1;
3013        __le32  event_data2;
3014};
3015
3016/* hwrm_func_echo_response_output (size:128b/16B) */
3017struct hwrm_func_echo_response_output {
3018        __le16  error_code;
3019        __le16  req_type;
3020        __le16  seq_id;
3021        __le16  resp_len;
3022        u8      unused_0[7];
3023        u8      valid;
3024};
3025
3026/* hwrm_func_ptp_pin_qcfg_input (size:192b/24B) */
3027struct hwrm_func_ptp_pin_qcfg_input {
3028        __le16  req_type;
3029        __le16  cmpl_ring;
3030        __le16  seq_id;
3031        __le16  target_id;
3032        __le64  resp_addr;
3033        u8      unused_0[8];
3034};
3035
3036/* hwrm_func_ptp_pin_qcfg_output (size:128b/16B) */
3037struct hwrm_func_ptp_pin_qcfg_output {
3038        __le16  error_code;
3039        __le16  req_type;
3040        __le16  seq_id;
3041        __le16  resp_len;
3042        u8      num_pins;
3043        u8      state;
3044        #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN0_ENABLED     0x1UL
3045        #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN1_ENABLED     0x2UL
3046        #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN2_ENABLED     0x4UL
3047        #define FUNC_PTP_PIN_QCFG_RESP_STATE_PIN3_ENABLED     0x8UL
3048        u8      pin0_usage;
3049        #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_NONE     0x0UL
3050        #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_IN   0x1UL
3051        #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_PPS_OUT  0x2UL
3052        #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_IN  0x3UL
3053        #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT 0x4UL
3054        #define FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN0_USAGE_SYNC_OUT
3055        u8      pin1_usage;
3056        #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_NONE     0x0UL
3057        #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_IN   0x1UL
3058        #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_PPS_OUT  0x2UL
3059        #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_IN  0x3UL
3060        #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT 0x4UL
3061        #define FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN1_USAGE_SYNC_OUT
3062        u8      pin2_usage;
3063        #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_NONE     0x0UL
3064        #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_IN   0x1UL
3065        #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_PPS_OUT  0x2UL
3066        #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_IN  0x3UL
3067        #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT 0x4UL
3068        #define FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN2_USAGE_SYNC_OUT
3069        u8      pin3_usage;
3070        #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_NONE     0x0UL
3071        #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_IN   0x1UL
3072        #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_PPS_OUT  0x2UL
3073        #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_IN  0x3UL
3074        #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT 0x4UL
3075        #define FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_LAST    FUNC_PTP_PIN_QCFG_RESP_PIN3_USAGE_SYNC_OUT
3076        u8      unused_0;
3077        u8      valid;
3078};
3079
3080/* hwrm_func_ptp_pin_cfg_input (size:256b/32B) */
3081struct hwrm_func_ptp_pin_cfg_input {
3082        __le16  req_type;
3083        __le16  cmpl_ring;
3084        __le16  seq_id;
3085        __le16  target_id;
3086        __le64  resp_addr;
3087        __le32  enables;
3088        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_STATE     0x1UL
3089        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN0_USAGE     0x2UL
3090        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_STATE     0x4UL
3091        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN1_USAGE     0x8UL
3092        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_STATE     0x10UL
3093        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN2_USAGE     0x20UL
3094        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_STATE     0x40UL
3095        #define FUNC_PTP_PIN_CFG_REQ_ENABLES_PIN3_USAGE     0x80UL
3096        u8      pin0_state;
3097        #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_DISABLED 0x0UL
3098        #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED  0x1UL
3099        #define FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN0_STATE_ENABLED
3100        u8      pin0_usage;
3101        #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_NONE     0x0UL
3102        #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_IN   0x1UL
3103        #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_PPS_OUT  0x2UL
3104        #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_IN  0x3UL
3105        #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT 0x4UL
3106        #define FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN0_USAGE_SYNC_OUT
3107        u8      pin1_state;
3108        #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_DISABLED 0x0UL
3109        #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED  0x1UL
3110        #define FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN1_STATE_ENABLED
3111        u8      pin1_usage;
3112        #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_NONE     0x0UL
3113        #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_IN   0x1UL
3114        #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_PPS_OUT  0x2UL
3115        #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_IN  0x3UL
3116        #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT 0x4UL
3117        #define FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN1_USAGE_SYNC_OUT
3118        u8      pin2_state;
3119        #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_DISABLED 0x0UL
3120        #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED  0x1UL
3121        #define FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN2_STATE_ENABLED
3122        u8      pin2_usage;
3123        #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_NONE     0x0UL
3124        #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_IN   0x1UL
3125        #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_PPS_OUT  0x2UL
3126        #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_IN  0x3UL
3127        #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT 0x4UL
3128        #define FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN2_USAGE_SYNC_OUT
3129        u8      pin3_state;
3130        #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_DISABLED 0x0UL
3131        #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED  0x1UL
3132        #define FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN3_STATE_ENABLED
3133        u8      pin3_usage;
3134        #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_NONE     0x0UL
3135        #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_IN   0x1UL
3136        #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_PPS_OUT  0x2UL
3137        #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_IN  0x3UL
3138        #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT 0x4UL
3139        #define FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_LAST    FUNC_PTP_PIN_CFG_REQ_PIN3_USAGE_SYNC_OUT
3140        u8      unused_0[4];
3141};
3142
3143/* hwrm_func_ptp_pin_cfg_output (size:128b/16B) */
3144struct hwrm_func_ptp_pin_cfg_output {
3145        __le16  error_code;
3146        __le16  req_type;
3147        __le16  seq_id;
3148        __le16  resp_len;
3149        u8      unused_0[7];
3150        u8      valid;
3151};
3152
3153/* hwrm_func_ptp_cfg_input (size:320b/40B) */
3154struct hwrm_func_ptp_cfg_input {
3155        __le16  req_type;
3156        __le16  cmpl_ring;
3157        __le16  seq_id;
3158        __le16  target_id;
3159        __le64  resp_addr;
3160        __le16  enables;
3161        #define FUNC_PTP_CFG_REQ_ENABLES_PTP_PPS_EVENT               0x1UL
3162        #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_SOURCE     0x2UL
3163        #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_DLL_PHASE      0x4UL
3164        #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PERIOD     0x8UL
3165        #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_UP         0x10UL
3166        #define FUNC_PTP_CFG_REQ_ENABLES_PTP_FREQ_ADJ_EXT_PHASE      0x20UL
3167        u8      ptp_pps_event;
3168        #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_INTERNAL     0x1UL
3169        #define FUNC_PTP_CFG_REQ_PTP_PPS_EVENT_EXTERNAL     0x2UL
3170        u8      ptp_freq_adj_dll_source;
3171        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_NONE    0x0UL
3172        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_0  0x1UL
3173        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_1  0x2UL
3174        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_2  0x3UL
3175        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_TSIO_3  0x4UL
3176        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_0  0x5UL
3177        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_1  0x6UL
3178        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_2  0x7UL
3179        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_PORT_3  0x8UL
3180        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID 0xffUL
3181        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_LAST   FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_SOURCE_INVALID
3182        u8      ptp_freq_adj_dll_phase;
3183        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_NONE 0x0UL
3184        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_4K   0x1UL
3185        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_8K   0x2UL
3186        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M  0x3UL
3187        #define FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_LAST FUNC_PTP_CFG_REQ_PTP_FREQ_ADJ_DLL_PHASE_10M
3188        u8      unused_0[3];
3189        __le32  ptp_freq_adj_ext_period;
3190        __le32  ptp_freq_adj_ext_up;
3191        __le32  ptp_freq_adj_ext_phase_lower;
3192        __le32  ptp_freq_adj_ext_phase_upper;
3193};
3194
3195/* hwrm_func_ptp_cfg_output (size:128b/16B) */
3196struct hwrm_func_ptp_cfg_output {
3197        __le16  error_code;
3198        __le16  req_type;
3199        __le16  seq_id;
3200        __le16  resp_len;
3201        u8      unused_0[7];
3202        u8      valid;
3203};
3204
3205/* hwrm_func_ptp_ts_query_input (size:192b/24B) */
3206struct hwrm_func_ptp_ts_query_input {
3207        __le16  req_type;
3208        __le16  cmpl_ring;
3209        __le16  seq_id;
3210        __le16  target_id;
3211        __le64  resp_addr;
3212        __le32  flags;
3213        #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PPS_TIME     0x1UL
3214        #define FUNC_PTP_TS_QUERY_REQ_FLAGS_PTM_TIME     0x2UL
3215        u8      unused_0[4];
3216};
3217
3218/* hwrm_func_ptp_ts_query_output (size:320b/40B) */
3219struct hwrm_func_ptp_ts_query_output {
3220        __le16  error_code;
3221        __le16  req_type;
3222        __le16  seq_id;
3223        __le16  resp_len;
3224        __le64  pps_event_ts;
3225        __le64  ptm_res_local_ts;
3226        __le64  ptm_pmstr_ts;
3227        __le32  ptm_mstr_prop_dly;
3228        u8      unused_0[3];
3229        u8      valid;
3230};
3231
3232/* hwrm_func_drv_if_change_input (size:192b/24B) */
3233struct hwrm_func_drv_if_change_input {
3234        __le16  req_type;
3235        __le16  cmpl_ring;
3236        __le16  seq_id;
3237        __le16  target_id;
3238        __le64  resp_addr;
3239        __le32  flags;
3240        #define FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP     0x1UL
3241        __le32  unused;
3242};
3243
3244/* hwrm_func_drv_if_change_output (size:128b/16B) */
3245struct hwrm_func_drv_if_change_output {
3246        __le16  error_code;
3247        __le16  req_type;
3248        __le16  seq_id;
3249        __le16  resp_len;
3250        __le32  flags;
3251        #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE           0x1UL
3252        #define FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE     0x2UL
3253        u8      unused_0[3];
3254        u8      valid;
3255};
3256
3257/* hwrm_port_phy_cfg_input (size:448b/56B) */
3258struct hwrm_port_phy_cfg_input {
3259        __le16  req_type;
3260        __le16  cmpl_ring;
3261        __le16  seq_id;
3262        __le16  target_id;
3263        __le64  resp_addr;
3264        __le32  flags;
3265        #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY                  0x1UL
3266        #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED                 0x2UL
3267        #define PORT_PHY_CFG_REQ_FLAGS_FORCE                      0x4UL
3268        #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG            0x8UL
3269        #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE                 0x10UL
3270        #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE                0x20UL
3271        #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE          0x40UL
3272        #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE         0x80UL
3273        #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE         0x100UL
3274        #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE        0x200UL
3275        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE        0x400UL
3276        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE       0x800UL
3277        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE        0x1000UL
3278        #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE       0x2000UL
3279        #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN             0x4000UL
3280        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE       0x8000UL
3281        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE      0x10000UL
3282        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE      0x20000UL
3283        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE     0x40000UL
3284        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE       0x80000UL
3285        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE      0x100000UL
3286        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE      0x200000UL
3287        #define PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE     0x400000UL
3288        __le32  enables;
3289        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE                     0x1UL
3290        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX                   0x2UL
3291        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE                    0x4UL
3292        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED               0x8UL
3293        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK          0x10UL
3294        #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED                     0x20UL
3295        #define PORT_PHY_CFG_REQ_ENABLES_LPBK                          0x40UL
3296        #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS                   0x80UL
3297        #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE                   0x100UL
3298        #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK           0x200UL
3299        #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER                  0x400UL
3300        #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED         0x800UL
3301        #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK     0x1000UL
3302        __le16  port_id;
3303        __le16  force_link_speed;
3304        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL
3305        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB   0xaUL
3306        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB   0x14UL
3307        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL
3308        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB  0x64UL
3309        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB  0xc8UL
3310        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB  0xfaUL
3311        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB  0x190UL
3312        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB  0x1f4UL
3313        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL
3314        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB  0xffffUL
3315        #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB
3316        u8      auto_mode;
3317        #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE         0x0UL
3318        #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS   0x1UL
3319        #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED    0x2UL
3320        #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL
3321        #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK   0x4UL
3322        #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST        PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK
3323        u8      auto_duplex;
3324        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL
3325        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL
3326        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL
3327        #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH
3328        u8      auto_pause;
3329        #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX                0x1UL
3330        #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX                0x2UL
3331        #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
3332        u8      unused_0;
3333        __le16  auto_link_speed;
3334        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL
3335        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB   0xaUL
3336        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB   0x14UL
3337        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL
3338        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB  0x64UL
3339        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB  0xc8UL
3340        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB  0xfaUL
3341        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB  0x190UL
3342        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB  0x1f4UL
3343        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL
3344        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB  0xffffUL
3345        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB
3346        __le16  auto_link_speed_mask;
3347        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
3348        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB       0x2UL
3349        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
3350        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB         0x8UL
3351        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB         0x10UL
3352        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
3353        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB        0x40UL
3354        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB        0x80UL
3355        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB        0x100UL
3356        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB        0x200UL
3357        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB        0x400UL
3358        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB       0x800UL
3359        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
3360        #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
3361        u8      wirespeed;
3362        #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL
3363        #define PORT_PHY_CFG_REQ_WIRESPEED_ON  0x1UL
3364        #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON
3365        u8      lpbk;
3366        #define PORT_PHY_CFG_REQ_LPBK_NONE     0x0UL
3367        #define PORT_PHY_CFG_REQ_LPBK_LOCAL    0x1UL
3368        #define PORT_PHY_CFG_REQ_LPBK_REMOTE   0x2UL
3369        #define PORT_PHY_CFG_REQ_LPBK_EXTERNAL 0x3UL
3370        #define PORT_PHY_CFG_REQ_LPBK_LAST    PORT_PHY_CFG_REQ_LPBK_EXTERNAL
3371        u8      force_pause;
3372        #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX     0x1UL
3373        #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX     0x2UL
3374        u8      unused_1;
3375        __le32  preemphasis;
3376        __le16  eee_link_speed_mask;
3377        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1     0x1UL
3378        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB     0x2UL
3379        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2     0x4UL
3380        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB       0x8UL
3381        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3     0x10UL
3382        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4     0x20UL
3383        #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB      0x40UL
3384        __le16  force_pam4_link_speed;
3385        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_50GB  0x1f4UL
3386        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_100GB 0x3e8UL
3387        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB 0x7d0UL
3388        #define PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_PAM4_LINK_SPEED_200GB
3389        __le32  tx_lpi_timer;
3390        #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL
3391        #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0
3392        __le16  auto_link_pam4_speed_mask;
3393        #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_50G      0x1UL
3394        #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_100G     0x2UL
3395        #define PORT_PHY_CFG_REQ_AUTO_LINK_PAM4_SPEED_MASK_200G     0x4UL
3396        u8      unused_2[2];
3397};
3398
3399/* hwrm_port_phy_cfg_output (size:128b/16B) */
3400struct hwrm_port_phy_cfg_output {
3401        __le16  error_code;
3402        __le16  req_type;
3403        __le16  seq_id;
3404        __le16  resp_len;
3405        u8      unused_0[7];
3406        u8      valid;
3407};
3408
3409/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */
3410struct hwrm_port_phy_cfg_cmd_err {
3411        u8      code;
3412        #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN       0x0UL
3413        #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL
3414        #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY         0x2UL
3415        #define PORT_PHY_CFG_CMD_ERR_CODE_LAST         PORT_PHY_CFG_CMD_ERR_CODE_RETRY
3416        u8      unused_0[7];
3417};
3418
3419/* hwrm_port_phy_qcfg_input (size:192b/24B) */
3420struct hwrm_port_phy_qcfg_input {
3421        __le16  req_type;
3422        __le16  cmpl_ring;
3423        __le16  seq_id;
3424        __le16  target_id;
3425        __le64  resp_addr;
3426        __le16  port_id;
3427        u8      unused_0[6];
3428};
3429
3430/* hwrm_port_phy_qcfg_output (size:768b/96B) */
3431struct hwrm_port_phy_qcfg_output {
3432        __le16  error_code;
3433        __le16  req_type;
3434        __le16  seq_id;
3435        __le16  resp_len;
3436        u8      link;
3437        #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL
3438        #define PORT_PHY_QCFG_RESP_LINK_SIGNAL  0x1UL
3439        #define PORT_PHY_QCFG_RESP_LINK_LINK    0x2UL
3440        #define PORT_PHY_QCFG_RESP_LINK_LAST   PORT_PHY_QCFG_RESP_LINK_LINK
3441        u8      active_fec_signal_mode;
3442        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_MASK                0xfUL
3443        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_SFT                 0
3444        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ                   0x0UL
3445        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4                  0x1UL
3446        #define PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST                 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4
3447        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK                 0xf0UL
3448        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_SFT                  4
3449        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE        (0x0UL << 4)
3450        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE    (0x1UL << 4)
3451        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE    (0x2UL << 4)
3452        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE   (0x3UL << 4)
3453        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE  (0x4UL << 4)
3454        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE   (0x5UL << 4)
3455        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE  (0x6UL << 4)
3456        #define PORT_PHY_QCFG_RESP_ACTIVE_FEC_LAST                  PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE
3457        __le16  link_speed;
3458        #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL
3459        #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB   0xaUL
3460        #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB   0x14UL
3461        #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL
3462        #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB  0x64UL
3463        #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB  0xc8UL
3464        #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB  0xfaUL
3465        #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB  0x190UL
3466        #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB  0x1f4UL
3467        #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL
3468        #define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL
3469        #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL
3470        #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB
3471        u8      duplex_cfg;
3472        #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL
3473        #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL
3474        #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL
3475        u8      pause;
3476        #define PORT_PHY_QCFG_RESP_PAUSE_TX     0x1UL
3477        #define PORT_PHY_QCFG_RESP_PAUSE_RX     0x2UL
3478        __le16  support_speeds;
3479        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD     0x1UL
3480        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB       0x2UL
3481        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD       0x4UL
3482        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB         0x8UL
3483        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB         0x10UL
3484        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB       0x20UL
3485        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB        0x40UL
3486        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB        0x80UL
3487        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB        0x100UL
3488        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB        0x200UL
3489        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB        0x400UL
3490        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB       0x800UL
3491        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD      0x1000UL
3492        #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB        0x2000UL
3493        __le16  force_link_speed;
3494        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL
3495        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB   0xaUL
3496        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB   0x14UL
3497        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL
3498        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB  0x64UL
3499        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB  0xc8UL
3500        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB  0xfaUL
3501        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB  0x190UL
3502        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB  0x1f4UL
3503        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL
3504        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB  0xffffUL
3505        #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB
3506        u8      auto_mode;
3507        #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE         0x0UL
3508        #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS   0x1UL
3509        #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED    0x2UL
3510        #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL
3511        #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK   0x4UL
3512        #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST        PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
3513        u8      auto_pause;
3514        #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX                0x1UL
3515        #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX                0x2UL
3516        #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE     0x4UL
3517        __le16  auto_link_speed;
3518        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL
3519        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB   0xaUL
3520        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB   0x14UL
3521        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL
3522        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB  0x64UL
3523        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB  0xc8UL
3524        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB  0xfaUL
3525        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB  0x190UL
3526        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB  0x1f4UL
3527        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL
3528        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB  0xffffUL
3529        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB
3530        __le16  auto_link_speed_mask;
3531        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD     0x1UL
3532        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB       0x2UL
3533        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD       0x4UL
3534        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB         0x8UL
3535        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB         0x10UL
3536        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB       0x20UL
3537        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB        0x40UL
3538        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB        0x80UL
3539        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB        0x100UL
3540        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB        0x200UL
3541        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB        0x400UL
3542        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB       0x800UL
3543        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD      0x1000UL
3544        #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB        0x2000UL
3545        u8      wirespeed;
3546        #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL
3547        #define PORT_PHY_QCFG_RESP_WIRESPEED_ON  0x1UL
3548        #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON
3549        u8      lpbk;
3550        #define PORT_PHY_QCFG_RESP_LPBK_NONE     0x0UL
3551        #define PORT_PHY_QCFG_RESP_LPBK_LOCAL    0x1UL
3552        #define PORT_PHY_QCFG_RESP_LPBK_REMOTE   0x2UL
3553        #define PORT_PHY_QCFG_RESP_LPBK_EXTERNAL 0x3UL
3554        #define PORT_PHY_QCFG_RESP_LPBK_LAST    PORT_PHY_QCFG_RESP_LPBK_EXTERNAL
3555        u8      force_pause;
3556        #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX     0x1UL
3557        #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX     0x2UL
3558        u8      module_status;
3559        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE          0x0UL
3560        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX     0x1UL
3561        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG    0x2UL
3562        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN       0x3UL
3563        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED   0x4UL
3564        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_CURRENTFAULT  0x5UL
3565        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL
3566        #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST         PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE
3567        __le32  preemphasis;
3568        u8      phy_maj;
3569        u8      phy_min;
3570        u8      phy_bld;
3571        u8      phy_type;
3572        #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN          0x0UL
3573        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR           0x1UL
3574        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4          0x2UL
3575        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR           0x3UL
3576        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR           0x4UL
3577        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2          0x5UL
3578        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX           0x6UL
3579        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR           0x7UL
3580        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET            0x8UL
3581        #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE           0x9UL
3582        #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY      0xaUL
3583        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L  0xbUL
3584        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S  0xcUL
3585        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N  0xdUL
3586        #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR       0xeUL
3587        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4     0xfUL
3588        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4     0x10UL
3589        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4     0x11UL
3590        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4     0x12UL
3591        #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10    0x13UL
3592        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4      0x14UL
3593        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4      0x15UL
3594        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4      0x16UL
3595        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4      0x17UL
3596        #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL
3597        #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET         0x19UL