1
2
3
4
5
6
7
8#ifndef ARC_EMAC_H
9#define ARC_EMAC_H
10
11#include <linux/device.h>
12#include <linux/dma-mapping.h>
13#include <linux/netdevice.h>
14#include <linux/phy.h>
15#include <linux/clk.h>
16
17
18#define TXINT_MASK (1 << 0)
19#define RXINT_MASK (1 << 1)
20#define ERR_MASK (1 << 2)
21#define TXCH_MASK (1 << 3)
22#define MSER_MASK (1 << 4)
23#define RXCR_MASK (1 << 8)
24#define RXFR_MASK (1 << 9)
25#define RXFL_MASK (1 << 10)
26#define MDIO_MASK (1 << 12)
27#define TXPL_MASK (1 << 31)
28
29
30#define EN_MASK (1 << 0)
31#define TXRN_MASK (1 << 3)
32#define RXRN_MASK (1 << 4)
33#define DSBC_MASK (1 << 8)
34#define ENFL_MASK (1 << 10)
35#define PROM_MASK (1 << 11)
36
37
38#define OWN_MASK (1 << 31)
39#define FIRST_MASK (1 << 16)
40#define LAST_MASK (1 << 17)
41#define LEN_MASK 0x000007FF
42#define CRLS (1 << 21)
43#define DEFR (1 << 22)
44#define DROP (1 << 23)
45#define RTRY (1 << 24)
46#define LTCL (1 << 28)
47#define UFLO (1 << 29)
48
49#define FOR_EMAC OWN_MASK
50#define FOR_CPU 0
51
52
53enum {
54 R_ID = 0,
55 R_STATUS,
56 R_ENABLE,
57 R_CTRL,
58 R_POLLRATE,
59 R_RXERR,
60 R_MISS,
61 R_TX_RING,
62 R_RX_RING,
63 R_ADDRL,
64 R_ADDRH,
65 R_LAFL,
66 R_LAFH,
67 R_MDIO,
68};
69
70#define TX_TIMEOUT (400 * HZ / 1000)
71
72#define ARC_EMAC_NAPI_WEIGHT 40
73
74#define EMAC_BUFFER_SIZE 1536
75
76
77
78
79
80
81
82struct arc_emac_bd {
83 __le32 info;
84 dma_addr_t data;
85};
86
87
88#define RX_BD_NUM 128
89#define TX_BD_NUM 128
90
91#define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
92#define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
93
94
95
96
97
98
99
100struct buffer_state {
101 struct sk_buff *skb;
102 DEFINE_DMA_UNMAP_ADDR(addr);
103 DEFINE_DMA_UNMAP_LEN(len);
104};
105
106struct arc_emac_mdio_bus_data {
107 struct gpio_desc *reset_gpio;
108 int msec;
109};
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131struct arc_emac_priv {
132 const char *drv_name;
133 void (*set_mac_speed)(void *priv, unsigned int speed);
134
135
136 struct device *dev;
137 struct mii_bus *bus;
138 struct arc_emac_mdio_bus_data bus_data;
139
140 void __iomem *regs;
141 struct clk *clk;
142
143 struct napi_struct napi;
144
145 struct arc_emac_bd *rxbd;
146 struct arc_emac_bd *txbd;
147
148 dma_addr_t rxbd_dma;
149 dma_addr_t txbd_dma;
150
151 struct buffer_state rx_buff[RX_BD_NUM];
152 struct buffer_state tx_buff[TX_BD_NUM];
153 unsigned int txbd_curr;
154 unsigned int txbd_dirty;
155
156 unsigned int last_rx_bd;
157
158 unsigned int link;
159 unsigned int duplex;
160 unsigned int speed;
161
162 unsigned int rx_missed_errors;
163};
164
165
166
167
168
169
170
171static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
172{
173 iowrite32(value, priv->regs + reg * sizeof(int));
174}
175
176
177
178
179
180
181
182
183static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
184{
185 return ioread32(priv->regs + reg * sizeof(int));
186}
187
188
189
190
191
192
193
194
195
196
197static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
198{
199 unsigned int value = arc_reg_get(priv, reg);
200
201 arc_reg_set(priv, reg, value | mask);
202}
203
204
205
206
207
208
209
210
211
212
213static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
214{
215 unsigned int value = arc_reg_get(priv, reg);
216
217 arc_reg_set(priv, reg, value & ~mask);
218}
219
220int arc_mdio_probe(struct arc_emac_priv *priv);
221int arc_mdio_remove(struct arc_emac_priv *priv);
222int arc_emac_probe(struct net_device *ndev, int interface);
223int arc_emac_remove(struct net_device *ndev);
224
225#endif
226