LXR linux/drivers/net/dsa/mv88e6xxx/chip.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Marvell 88E6xxx Ethernet switch single-chip definition
   4 *
   5 * Copyright (c) 2008 Marvell Semiconductor
   6 */
   7
   8#ifndef _MV88E6XXX_CHIP_H
   9#define _MV88E6XXX_CHIP_H
  10
  11#include <linux/idr.h>
  12#include <linux/if_vlan.h>
  13#include <linux/irq.h>
  14#include <linux/gpio/consumer.h>
  15#include <linux/kthread.h>
  16#include <linux/phy.h>
  17#include <linux/ptp_clock_kernel.h>
  18#include <linux/timecounter.h>
  19#include <net/dsa.h>
  20
  21#define MV88E6XXX_N_FID         4096
  22
  23/* PVT limits for 4-bit port and 5-bit switch */
  24#define MV88E6XXX_MAX_PVT_SWITCHES      32
  25#define MV88E6XXX_MAX_PVT_PORTS         16
  26#define MV88E6XXX_MAX_PVT_ENTRIES       \
  27        (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS)
  28
  29#define MV88E6XXX_MAX_GPIO      16
  30
  31enum mv88e6xxx_egress_mode {
  32        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
  33        MV88E6XXX_EGRESS_MODE_UNTAGGED,
  34        MV88E6XXX_EGRESS_MODE_TAGGED,
  35        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
  36};
  37
  38enum mv88e6xxx_egress_direction {
  39        MV88E6XXX_EGRESS_DIR_INGRESS,
  40        MV88E6XXX_EGRESS_DIR_EGRESS,
  41};
  42
  43enum mv88e6xxx_frame_mode {
  44        MV88E6XXX_FRAME_MODE_NORMAL,
  45        MV88E6XXX_FRAME_MODE_DSA,
  46        MV88E6XXX_FRAME_MODE_PROVIDER,
  47        MV88E6XXX_FRAME_MODE_ETHERTYPE,
  48};
  49
  50/* List of supported models */
  51enum mv88e6xxx_model {
  52        MV88E6085,
  53        MV88E6095,
  54        MV88E6097,
  55        MV88E6123,
  56        MV88E6131,
  57        MV88E6141,
  58        MV88E6161,
  59        MV88E6165,
  60        MV88E6171,
  61        MV88E6172,
  62        MV88E6175,
  63        MV88E6176,
  64        MV88E6185,
  65        MV88E6190,
  66        MV88E6190X,
  67        MV88E6191,
  68        MV88E6191X,
  69        MV88E6193X,
  70        MV88E6220,
  71        MV88E6240,
  72        MV88E6250,
  73        MV88E6290,
  74        MV88E6320,
  75        MV88E6321,
  76        MV88E6341,
  77        MV88E6350,
  78        MV88E6351,
  79        MV88E6352,
  80        MV88E6390,
  81        MV88E6390X,
  82        MV88E6393X,
  83};
  84
  85enum mv88e6xxx_family {
  86        MV88E6XXX_FAMILY_NONE,
  87        MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
  88        MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
  89        MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
  90        MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
  91        MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
  92        MV88E6XXX_FAMILY_6250,  /* 6220 6250 */
  93        MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
  94        MV88E6XXX_FAMILY_6341,  /* 6141 6341 */
  95        MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
  96        MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
  97        MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
  98        MV88E6XXX_FAMILY_6393,  /* 6191X 6193X 6393X */
  99};
 100
 101/**
 102 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
 103 * @MV88E6XXX_EDSA_UNSUPPORTED:  Device has no support for EDSA tags
 104 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that
 105 *                               egressing FORWARD frames with an EDSA
 106 *                               tag is reserved for future use, but
 107 *                               empirical data shows that this mode
 108 *                               is supported.
 109 * @MV88E6XXX_EDSA_SUPPORTED:    EDSA tags are fully supported.
 110 */
 111enum mv88e6xxx_edsa_support {
 112        MV88E6XXX_EDSA_UNSUPPORTED = 0,
 113        MV88E6XXX_EDSA_UNDOCUMENTED,
 114        MV88E6XXX_EDSA_SUPPORTED,
 115};
 116
 117struct mv88e6xxx_ops;
 118
 119struct mv88e6xxx_info {
 120        enum mv88e6xxx_family family;
 121        u16 prod_num;
 122        const char *name;
 123        unsigned int num_databases;
 124        unsigned int num_macs;
 125        unsigned int num_ports;
 126        unsigned int num_internal_phys;
 127        unsigned int num_gpio;
 128        unsigned int max_vid;
 129        unsigned int port_base_addr;
 130        unsigned int phy_base_addr;
 131        unsigned int global1_addr;
 132        unsigned int global2_addr;
 133        unsigned int age_time_coeff;
 134        unsigned int g1_irqs;
 135        unsigned int g2_irqs;
 136        bool pvt;
 137
 138        /* Mark certain ports as invalid. This is required for example for the
 139         * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
 140         * ports 2-4 are not routet to pins.
 141         */
 142        unsigned int invalid_port_mask;
 143        /* Multi-chip Addressing Mode.
 144         * Some chips respond to only 2 registers of its own SMI device address
 145         * when it is non-zero, and use indirect access to internal registers.
 146         */
 147        bool multi_chip;
 148        /* Dual-chip Addressing Mode
 149         * Some chips respond to only half of the 32 SMI addresses,
 150         * allowing two to coexist on the same SMI interface.
 151         */
 152        bool dual_chip;
 153
 154        enum mv88e6xxx_edsa_support edsa_support;
 155
 156        /* Mask for FromPort and ToPort value of PortVec used in ATU Move
 157         * operation. 0 means that the ATU Move operation is not supported.
 158         */
 159        u8 atu_move_port_mask;
 160        const struct mv88e6xxx_ops *ops;
 161
 162        /* Supports PTP */
 163        bool ptp_support;
 164};
 165
 166struct mv88e6xxx_atu_entry {
 167        u8      state;
 168        bool    trunk;
 169        u16     portvec;
 170        u8      mac[ETH_ALEN];
 171};
 172
 173struct mv88e6xxx_vtu_entry {
 174        u16     vid;
 175        u16     fid;
 176        u8      sid;
 177        bool    valid;
 178        u8      member[DSA_MAX_PORTS];
 179        u8      state[DSA_MAX_PORTS];
 180};
 181
 182struct mv88e6xxx_bus_ops;
 183struct mv88e6xxx_irq_ops;
 184struct mv88e6xxx_gpio_ops;
 185struct mv88e6xxx_avb_ops;
 186struct mv88e6xxx_ptp_ops;
 187
 188struct mv88e6xxx_irq {
 189        u16 masked;
 190        struct irq_chip chip;
 191        struct irq_domain *domain;
 192        int nirqs;
 193};
 194
 195/* state flags for mv88e6xxx_port_hwtstamp::state */
 196enum {
 197        MV88E6XXX_HWTSTAMP_ENABLED,
 198        MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
 199};
 200
 201struct mv88e6xxx_port_hwtstamp {
 202        /* Port index */
 203        int port_id;
 204
 205        /* Timestamping state */
 206        unsigned long state;
 207
 208        /* Resources for receive timestamping */
 209        struct sk_buff_head rx_queue;
 210        struct sk_buff_head rx_queue2;
 211
 212        /* Resources for transmit timestamping */
 213        unsigned long tx_tstamp_start;
 214        struct sk_buff *tx_skb;
 215        u16 tx_seq_id;
 216
 217        /* Current timestamp configuration */
 218        struct hwtstamp_config tstamp_config;
 219};
 220
 221enum mv88e6xxx_policy_mapping {
 222        MV88E6XXX_POLICY_MAPPING_DA,
 223        MV88E6XXX_POLICY_MAPPING_SA,
 224        MV88E6XXX_POLICY_MAPPING_VTU,
 225        MV88E6XXX_POLICY_MAPPING_ETYPE,
 226        MV88E6XXX_POLICY_MAPPING_PPPOE,
 227        MV88E6XXX_POLICY_MAPPING_VBAS,
 228        MV88E6XXX_POLICY_MAPPING_OPT82,
 229        MV88E6XXX_POLICY_MAPPING_UDP,
 230};
 231
 232enum mv88e6xxx_policy_action {
 233        MV88E6XXX_POLICY_ACTION_NORMAL,
 234        MV88E6XXX_POLICY_ACTION_MIRROR,
 235        MV88E6XXX_POLICY_ACTION_TRAP,
 236        MV88E6XXX_POLICY_ACTION_DISCARD,
 237};
 238
 239struct mv88e6xxx_policy {
 240        enum mv88e6xxx_policy_mapping mapping;
 241        enum mv88e6xxx_policy_action action;
 242        struct ethtool_rx_flow_spec fs;
 243        u8 addr[ETH_ALEN];
 244        int port;
 245        u16 vid;
 246};
 247
 248struct mv88e6xxx_port {
 249        struct mv88e6xxx_chip *chip;
 250        int port;
 251        u64 serdes_stats[2];
 252        u64 atu_member_violation;
 253        u64 atu_miss_violation;
 254        u64 atu_full_violation;
 255        u64 vtu_member_violation;
 256        u64 vtu_miss_violation;
 257        phy_interface_t interface;
 258        u8 cmode;
 259        bool mirror_ingress;
 260        bool mirror_egress;
 261        unsigned int serdes_irq;
 262        char serdes_irq_name[64];
 263        struct devlink_region *region;
 264};
 265
 266enum mv88e6xxx_region_id {
 267        MV88E6XXX_REGION_GLOBAL1 = 0,
 268        MV88E6XXX_REGION_GLOBAL2,
 269        MV88E6XXX_REGION_ATU,
 270        MV88E6XXX_REGION_VTU,
 271        MV88E6XXX_REGION_PVT,
 272
 273        _MV88E6XXX_REGION_MAX,
 274};
 275
 276struct mv88e6xxx_region_priv {
 277        enum mv88e6xxx_region_id id;
 278};
 279
 280struct mv88e6xxx_chip {
 281        const struct mv88e6xxx_info *info;
 282
 283        /* Currently configured tagging protocol */
 284        enum dsa_tag_protocol tag_protocol;
 285
 286        /* The dsa_switch this private structure is related to */
 287        struct dsa_switch *ds;
 288
 289        /* The device this structure is associated to */
 290        struct device *dev;
 291
 292        /* This mutex protects the access to the switch registers */
 293        struct mutex reg_lock;
 294
 295        /* The MII bus and the address on the bus that is used to
 296         * communication with the switch
 297         */
 298        const struct mv88e6xxx_bus_ops *smi_ops;
 299        struct mii_bus *bus;
 300        int sw_addr;
 301
 302        /* Handles automatic disabling and re-enabling of the PHY
 303         * polling unit.
 304         */
 305        const struct mv88e6xxx_bus_ops *phy_ops;
 306        struct mutex            ppu_mutex;
 307        int                     ppu_disabled;
 308        struct work_struct      ppu_work;
 309        struct timer_list       ppu_timer;
 310
 311        /* This mutex serialises access to the statistics unit.
 312         * Hold this mutex over snapshot + dump sequences.
 313         */
 314        struct mutex    stats_mutex;
 315
 316        /* A switch may have a GPIO line tied to its reset pin. Parse
 317         * this from the device tree, and use it before performing
 318         * switch soft reset.
 319         */
 320        struct gpio_desc *reset;
 321
 322        /* set to size of eeprom if supported by the switch */
 323        u32 eeprom_len;
 324
 325        /* List of mdio busses */
 326        struct list_head mdios;
 327
 328        /* Policy Control List IDs and rules */
 329        struct idr policies;
 330
 331        /* There can be two interrupt controllers, which are chained
 332         * off a GPIO as interrupt source
 333         */
 334        struct mv88e6xxx_irq g1_irq;
 335        struct mv88e6xxx_irq g2_irq;
 336        int irq;
 337        char irq_name[64];
 338        int device_irq;
 339        char device_irq_name[64];
 340        int watchdog_irq;
 341        char watchdog_irq_name[64];
 342
 343        int atu_prob_irq;
 344        char atu_prob_irq_name[64];
 345        int vtu_prob_irq;
 346        char vtu_prob_irq_name[64];
 347        struct kthread_worker *kworker;
 348        struct kthread_delayed_work irq_poll_work;
 349
 350        /* GPIO resources */
 351        u8 gpio_data[2];
 352
 353        /* This cyclecounter abstracts the switch PTP time.
 354         * reg_lock must be held for any operation that read()s.
 355         */
 356        struct cyclecounter     tstamp_cc;
 357        struct timecounter      tstamp_tc;
 358        struct delayed_work     overflow_work;
 359
 360        struct ptp_clock        *ptp_clock;
 361        struct ptp_clock_info   ptp_clock_info;
 362        struct delayed_work     tai_event_work;
 363        struct ptp_pin_desc     pin_config[MV88E6XXX_MAX_GPIO];
 364        u16 trig_config;
 365        u16 evcap_config;
 366        u16 enable_count;
 367
 368        /* Current ingress and egress monitor ports */
 369        int egress_dest_port;
 370        int ingress_dest_port;
 371
 372        /* Per-port timestamping resources. */
 373        struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
 374
 375        /* Array of port structures. */
 376        struct mv88e6xxx_port ports[DSA_MAX_PORTS];
 377
 378        /* devlink regions */
 379        struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
 380};
 381
 382struct mv88e6xxx_bus_ops {
 383        int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 384        int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 385};
 386
 387struct mv88e6xxx_mdio_bus {
 388        struct mii_bus *bus;
 389        struct mv88e6xxx_chip *chip;
 390        struct list_head list;
 391        bool external;
 392};
 393
 394struct mv88e6xxx_ops {
 395        /* Switch Setup Errata, called early in the switch setup to
 396         * allow any errata actions to be performed
 397         */
 398        int (*setup_errata)(struct mv88e6xxx_chip *chip);
 399
 400        int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
 401        int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
 402
 403        /* Ingress Rate Limit unit (IRL) operations */
 404        int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
 405
 406        int (*get_eeprom)(struct mv88e6xxx_chip *chip,
 407                          struct ethtool_eeprom *eeprom, u8 *data);
 408        int (*set_eeprom)(struct mv88e6xxx_chip *chip,
 409                          struct ethtool_eeprom *eeprom, u8 *data);
 410
 411        int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
 412
 413        int (*phy_read)(struct mv88e6xxx_chip *chip,
 414                        struct mii_bus *bus,
 415                        int addr, int reg, u16 *val);
 416        int (*phy_write)(struct mv88e6xxx_chip *chip,
 417                         struct mii_bus *bus,
 418                         int addr, int reg, u16 val);
 419
 420        /* Priority Override Table operations */
 421        int (*pot_clear)(struct mv88e6xxx_chip *chip);
 422
 423        /* PHY Polling Unit (PPU) operations */
 424        int (*ppu_enable)(struct mv88e6xxx_chip *chip);
 425        int (*ppu_disable)(struct mv88e6xxx_chip *chip);
 426
 427        /* Switch Software Reset */
 428        int (*reset)(struct mv88e6xxx_chip *chip);
 429
 430        /* RGMII Receive/Transmit Timing Control
 431         * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
 432         */
 433        int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
 434                                    phy_interface_t mode);
 435
 436#define LINK_FORCED_DOWN        0
 437#define LINK_FORCED_UP          1
 438#define LINK_UNFORCED           -2
 439
 440        /* Port's MAC link state
 441         * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
 442         * or LINK_UNFORCED for normal link detection.
 443         */
 444        int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
 445
 446        /* Synchronise the port link state with that of the SERDES
 447         */
 448        int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
 449
 450#define PAUSE_ON                1
 451#define PAUSE_OFF               0
 452
 453        /* Enable/disable sending Pause */
 454        int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
 455                              int pause);
 456
 457#define SPEED_MAX               INT_MAX
 458#define SPEED_UNFORCED          -2
 459#define DUPLEX_UNFORCED         -2
 460
 461        /* Port's MAC speed (in Mbps) and MAC duplex mode
 462         *
 463         * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
 464         * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
 465         *
 466         * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
 467         * or DUPLEX_UNFORCED for normal duplex detection.
 468         */
 469        int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
 470                                     int speed, int duplex);
 471
 472        /* What interface mode should be used for maximum speed? */
 473        phy_interface_t (*port_max_speed_mode)(int port);
 474
 475        int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
 476
 477        int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
 478                               enum mv88e6xxx_policy_mapping mapping,
 479                               enum mv88e6xxx_policy_action action);
 480
 481        int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
 482                                   enum mv88e6xxx_frame_mode mode);
 483        int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
 484                                    bool unicast);
 485        int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
 486                                    bool multicast);
 487        int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
 488                                   u16 etype);
 489        int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
 490                                   size_t size);
 491
 492        int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
 493        int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
 494                                u8 out);
 495        int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
 496        int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
 497        int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
 498
 499        /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
 500         * Some chips allow this to be configured on specific ports.
 501         */
 502        int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
 503                              phy_interface_t mode);
 504        int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 505
 506        /* Some devices have a per port register indicating what is
 507         * the upstream port this port should forward to.
 508         */
 509        int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
 510                                      int upstream_port);
 511
 512        /* Snapshot the statistics for a port. The statistics can then
 513         * be read back a leisure but still with a consistent view.
 514         */
 515        int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
 516
 517        /* Set the histogram mode for statistics, when the control registers
 518         * are separated out of the STATS_OP register.
 519         */
 520        int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
 521
 522        /* Return the number of strings describing statistics */
 523        int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
 524        int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
 525        int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 526                               uint64_t *data);
 527        int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
 528        int (*set_egress_port)(struct mv88e6xxx_chip *chip,
 529                               enum mv88e6xxx_egress_direction direction,
 530                               int port);
 531
 532#define MV88E6XXX_CASCADE_PORT_NONE             0xe
 533#define MV88E6XXX_CASCADE_PORT_MULTIPLE         0xf
 534
 535        int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
 536
 537        const struct mv88e6xxx_irq_ops *watchdog_ops;
 538
 539        int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
 540
 541        /* Power on/off a SERDES interface */
 542        int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane,
 543                            bool up);
 544
 545        /* SERDES lane mapping */
 546        int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
 547
 548        int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
 549                                    int lane, struct phylink_link_state *state);
 550        int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
 551                                 int lane, unsigned int mode,
 552                                 phy_interface_t interface,
 553                                 const unsigned long *advertise);
 554        int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
 555                                     int lane);
 556        int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
 557                                  int lane, int speed, int duplex);
 558
 559        /* SERDES interrupt handling */
 560        unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
 561                                           int port);
 562        int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane,
 563                                 bool enable);
 564        irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
 565                                         int lane);
 566
 567        /* Statistics from the SERDES interface */
 568        int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
 569        int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
 570                                  uint8_t *data);
 571        int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 572                                uint64_t *data);
 573
 574        /* SERDES registers for ethtool */
 575        int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip,  int port);
 576        void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
 577                                void *_p);
 578
 579        /* Address Translation Unit operations */
 580        int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
 581        int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
 582
 583        /* VLAN Translation Unit operations */
 584        int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
 585                           struct mv88e6xxx_vtu_entry *entry);
 586        int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
 587                             struct mv88e6xxx_vtu_entry *entry);
 588
 589        /* GPIO operations */
 590        const struct mv88e6xxx_gpio_ops *gpio_ops;
 591
 592        /* Interface to the AVB/PTP registers */
 593        const struct mv88e6xxx_avb_ops *avb_ops;
 594
 595        /* Remote Management Unit operations */
 596        int (*rmu_disable)(struct mv88e6xxx_chip *chip);
 597
 598        /* Precision Time Protocol operations */
 599        const struct mv88e6xxx_ptp_ops *ptp_ops;
 600
 601        /* Phylink */
 602        void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
 603                                 unsigned long *mask,
 604                                 struct phylink_link_state *state);
 605
 606        /* Max Frame Size */
 607        int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
 608};
 609
 610struct mv88e6xxx_irq_ops {
 611        /* Action to be performed when the interrupt happens */
 612        int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
 613        /* Setup the hardware to generate the interrupt */
 614        int (*irq_setup)(struct mv88e6xxx_chip *chip);
 615        /* Reset the hardware to stop generating the interrupt */
 616        void (*irq_free)(struct mv88e6xxx_chip *chip);
 617};
 618
 619struct mv88e6xxx_gpio_ops {
 620        /* Get/set data on GPIO pin */
 621        int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
 622        int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
 623                        int value);
 624
 625        /* get/set GPIO direction */
 626        int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
 627        int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
 628                       bool input);
 629
 630        /* get/set GPIO pin control */
 631        int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 632                        int *func);
 633        int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 634                        int func);
 635};
 636
 637struct mv88e6xxx_avb_ops {
 638        /* Access port-scoped Precision Time Protocol registers */
 639        int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
 640                             u16 *data, int len);
 641        int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
 642                              u16 data);
 643
 644        /* Access global Precision Time Protocol registers */
 645        int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 646                        int len);
 647        int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 648
 649        /* Access global Time Application Interface registers */
 650        int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 651                        int len);
 652        int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 653};
 654
 655struct mv88e6xxx_ptp_ops {
 656        u64 (*clock_read)(const struct cyclecounter *cc);
 657        int (*ptp_enable)(struct ptp_clock_info *ptp,
 658                          struct ptp_clock_request *rq, int on);
 659        int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
 660                          enum ptp_pin_function func, unsigned int chan);
 661        void (*event_work)(struct work_struct *ugly);
 662        int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
 663        int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
 664        int (*global_enable)(struct mv88e6xxx_chip *chip);
 665        int (*global_disable)(struct mv88e6xxx_chip *chip);
 666        int n_ext_ts;
 667        int arr0_sts_reg;
 668        int arr1_sts_reg;
 669        int dep_sts_reg;
 670        u32 rx_filters;
 671        u32 cc_shift;
 672        u32 cc_mult;
 673        u32 cc_mult_num;
 674        u32 cc_mult_dem;
 675};
 676
 677#define STATS_TYPE_PORT         BIT(0)
 678#define STATS_TYPE_BANK0        BIT(1)
 679#define STATS_TYPE_BANK1        BIT(2)
 680
 681struct mv88e6xxx_hw_stat {
 682        char string[ETH_GSTRING_LEN];
 683        size_t size;
 684        int reg;
 685        int type;
 686};
 687
 688static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
 689{
 690        return chip->info->pvt;
 691}
 692
 693static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
 694{
 695        return !!chip->info->global2_addr;
 696}
 697
 698static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 699{
 700        return chip->info->num_databases;
 701}
 702
 703static inline unsigned int mv88e6xxx_num_macs(struct  mv88e6xxx_chip *chip)
 704{
 705        return chip->info->num_macs;
 706}
 707
 708static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
 709{
 710        return chip->info->num_ports;
 711}
 712
 713static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
 714{
 715        return chip->info->max_vid;
 716}
 717
 718static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
 719{
 720        return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
 721}
 722
 723static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
 724{
 725        return chip->info->num_gpio;
 726}
 727
 728static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
 729{
 730        return (chip->info->invalid_port_mask & BIT(port)) != 0;
 731}
 732
 733int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 734int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 735int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
 736                        u16 mask, u16 val);
 737int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
 738                       int bit, int val);
 739struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
 740
 741static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
 742{
 743        mutex_lock(&chip->reg_lock);
 744}
 745
 746static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
 747{
 748        mutex_unlock(&chip->reg_lock);
 749}
 750
 751int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
 752
 753#endif /* _MV88E6XXX_CHIP_H */
 754