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8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/clk.h>
18#include <linux/of.h>
19#include <linux/of_irq.h>
20#include <linux/of_address.h>
21#include <linux/of_net.h>
22#include <linux/of_mdio.h>
23#include <net/dsa.h>
24#include <linux/ethtool.h>
25#include <linux/if_bridge.h>
26#include <linux/brcmphy.h>
27#include <linux/etherdevice.h>
28#include <linux/platform_data/b53.h>
29
30#include "bcm_sf2.h"
31#include "bcm_sf2_regs.h"
32#include "b53/b53_priv.h"
33#include "b53/b53_regs.h"
34
35static u16 bcm_sf2_reg_rgmii_cntrl(struct bcm_sf2_priv *priv, int port)
36{
37 switch (priv->type) {
38 case BCM4908_DEVICE_ID:
39 switch (port) {
40 case 7:
41 return REG_RGMII_11_CNTRL;
42 default:
43 break;
44 }
45 break;
46 default:
47 switch (port) {
48 case 0:
49 return REG_RGMII_0_CNTRL;
50 case 1:
51 return REG_RGMII_1_CNTRL;
52 case 2:
53 return REG_RGMII_2_CNTRL;
54 default:
55 break;
56 }
57 }
58
59 WARN_ONCE(1, "Unsupported port %d\n", port);
60
61
62 return REG_SWITCH_STATUS;
63}
64
65
66static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
67{
68 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
69 unsigned int port, count = 0;
70
71 for (port = 0; port < ARRAY_SIZE(priv->port_sts); port++) {
72 if (dsa_is_cpu_port(ds, port))
73 continue;
74 if (priv->port_sts[port].enabled)
75 count++;
76 }
77
78 return count;
79}
80
81static void bcm_sf2_recalc_clock(struct dsa_switch *ds)
82{
83 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
84 unsigned long new_rate;
85 unsigned int ports_active;
86
87 static const unsigned long rate_table[] = {
88 59220000,
89 60820000,
90 62500000,
91 62500000,
92 };
93
94 ports_active = bcm_sf2_num_active_ports(ds);
95 if (ports_active == 0 || !priv->clk_mdiv)
96 return;
97
98
99
100
101 if (ports_active > ARRAY_SIZE(rate_table))
102 new_rate = 90000000;
103 else
104 new_rate = rate_table[ports_active - 1];
105 clk_set_rate(priv->clk_mdiv, new_rate);
106}
107
108static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
109{
110 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
111 unsigned int i;
112 u32 reg, offset;
113
114
115 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
116 reg &= ~P_TXQ_PSM_VDD(port);
117 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
118
119
120 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
121
122
123 reg = core_readl(priv, CORE_SWITCH_CTRL);
124 reg |= MII_DUMB_FWDG_EN;
125 core_writel(priv, reg, CORE_SWITCH_CTRL);
126
127
128
129
130 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
131 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
132 reg |= i << (PRT_TO_QID_SHIFT * i);
133 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
134
135 b53_brcm_hdr_setup(ds, port);
136
137 if (port == 8) {
138 if (priv->type == BCM4908_DEVICE_ID ||
139 priv->type == BCM7445_DEVICE_ID)
140 offset = CORE_STS_OVERRIDE_IMP;
141 else
142 offset = CORE_STS_OVERRIDE_IMP2;
143
144
145 reg = core_readl(priv, offset);
146 reg |= (MII_SW_OR | LINK_STS);
147 if (priv->type == BCM4908_DEVICE_ID)
148 reg |= GMII_SPEED_UP_2G;
149 else
150 reg &= ~GMII_SPEED_UP_2G;
151 core_writel(priv, reg, offset);
152
153
154 reg = core_readl(priv, CORE_IMP_CTL);
155 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
156 reg &= ~(RX_DIS | TX_DIS);
157 core_writel(priv, reg, CORE_IMP_CTL);
158 } else {
159 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
160 reg &= ~(RX_DIS | TX_DIS);
161 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
162 }
163
164 priv->port_sts[port].enabled = true;
165}
166
167static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
168{
169 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
170 u32 reg;
171
172 reg = reg_readl(priv, REG_SPHY_CNTRL);
173 if (enable) {
174 reg |= PHY_RESET;
175 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
176 reg_writel(priv, reg, REG_SPHY_CNTRL);
177 udelay(21);
178 reg = reg_readl(priv, REG_SPHY_CNTRL);
179 reg &= ~PHY_RESET;
180 } else {
181 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
182 reg_writel(priv, reg, REG_SPHY_CNTRL);
183 mdelay(1);
184 reg |= CK25_DIS;
185 }
186 reg_writel(priv, reg, REG_SPHY_CNTRL);
187
188
189 if (!enable) {
190 reg = reg_readl(priv, REG_LED_CNTRL(0));
191 reg |= SPDLNK_SRC_SEL;
192 reg_writel(priv, reg, REG_LED_CNTRL(0));
193 }
194}
195
196static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
197 int port)
198{
199 unsigned int off;
200
201 switch (port) {
202 case 7:
203 off = P7_IRQ_OFF;
204 break;
205 case 0:
206
207 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
208 return;
209 default:
210 off = P_IRQ_OFF(port);
211 break;
212 }
213
214 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
215}
216
217static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
218 int port)
219{
220 unsigned int off;
221
222 switch (port) {
223 case 7:
224 off = P7_IRQ_OFF;
225 break;
226 case 0:
227
228 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
229 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
230 return;
231 default:
232 off = P_IRQ_OFF(port);
233 break;
234 }
235
236 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
237 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
238}
239
240static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
241 struct phy_device *phy)
242{
243 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
244 unsigned int i;
245 u32 reg;
246
247 if (!dsa_is_user_port(ds, port))
248 return 0;
249
250 priv->port_sts[port].enabled = true;
251
252 bcm_sf2_recalc_clock(ds);
253
254
255 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
256 reg &= ~P_TXQ_PSM_VDD(port);
257 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
258
259
260 if (priv->brcm_tag_mask & BIT(port))
261 b53_brcm_hdr_setup(ds, port);
262
263
264
265
266 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
267 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
268 reg |= i << (PRT_TO_QID_SHIFT * i);
269 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
270
271
272 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
273 bcm_sf2_gphy_enable_set(ds, true);
274 if (phy) {
275
276
277
278
279
280
281
282
283
284 phy->state = PHY_READY;
285 phy_init_hw(phy);
286 }
287 }
288
289
290 if (port == priv->moca_port)
291 bcm_sf2_port_intr_enable(priv, port);
292
293
294 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
295
296
297 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
298 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
299 SF2_NUM_EGRESS_QUEUES + i));
300 reg &= ~XOFF_THRESHOLD_MASK;
301 reg |= 24;
302 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
303 SF2_NUM_EGRESS_QUEUES + i));
304 }
305
306 return b53_enable_port(ds, port, phy);
307}
308
309static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
310{
311 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
312 u32 reg;
313
314
315 if (priv->wol_ports_mask & (1 << port)) {
316 reg = core_readl(priv, CORE_DIS_LEARN);
317 reg |= BIT(port);
318 core_writel(priv, reg, CORE_DIS_LEARN);
319 return;
320 }
321
322 if (port == priv->moca_port)
323 bcm_sf2_port_intr_disable(priv, port);
324
325 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
326 bcm_sf2_gphy_enable_set(ds, false);
327
328 b53_disable_port(ds, port);
329
330
331 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
332 reg |= P_TXQ_PSM_VDD(port);
333 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
334
335 priv->port_sts[port].enabled = false;
336
337 bcm_sf2_recalc_clock(ds);
338}
339
340
341static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
342 int regnum, u16 val)
343{
344 int ret = 0;
345 u32 reg;
346
347 reg = reg_readl(priv, REG_SWITCH_CNTRL);
348 reg |= MDIO_MASTER_SEL;
349 reg_writel(priv, reg, REG_SWITCH_CNTRL);
350
351
352 reg = 0x70;
353 reg <<= 2;
354 core_writel(priv, addr, reg);
355
356
357 reg = 0x80 << 8 | regnum << 1;
358 reg <<= 2;
359
360 if (op)
361 ret = core_readl(priv, reg);
362 else
363 core_writel(priv, val, reg);
364
365 reg = reg_readl(priv, REG_SWITCH_CNTRL);
366 reg &= ~MDIO_MASTER_SEL;
367 reg_writel(priv, reg, REG_SWITCH_CNTRL);
368
369 return ret & 0xffff;
370}
371
372static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
373{
374 struct bcm_sf2_priv *priv = bus->priv;
375
376
377
378
379 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
380 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
381 else
382 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
383}
384
385static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
386 u16 val)
387{
388 struct bcm_sf2_priv *priv = bus->priv;
389
390
391
392
393 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
394 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
395 else
396 return mdiobus_write_nested(priv->master_mii_bus, addr,
397 regnum, val);
398}
399
400static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
401{
402 struct dsa_switch *ds = dev_id;
403 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
404
405 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
406 ~priv->irq0_mask;
407 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
408
409 return IRQ_HANDLED;
410}
411
412static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
413{
414 struct dsa_switch *ds = dev_id;
415 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
416
417 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
418 ~priv->irq1_mask;
419 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
420
421 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
422 priv->port_sts[7].link = true;
423 dsa_port_phylink_mac_change(ds, 7, true);
424 }
425 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
426 priv->port_sts[7].link = false;
427 dsa_port_phylink_mac_change(ds, 7, false);
428 }
429
430 return IRQ_HANDLED;
431}
432
433static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
434{
435 unsigned int timeout = 1000;
436 u32 reg;
437 int ret;
438
439
440
441
442 if (priv->type == BCM7278_DEVICE_ID) {
443 ret = reset_control_assert(priv->rcdev);
444 if (ret)
445 return ret;
446
447 return reset_control_deassert(priv->rcdev);
448 }
449
450 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
451 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
452 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
453
454 do {
455 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
456 if (!(reg & SOFTWARE_RESET))
457 break;
458
459 usleep_range(1000, 2000);
460 } while (timeout-- > 0);
461
462 if (timeout == 0)
463 return -ETIMEDOUT;
464
465 return 0;
466}
467
468static void bcm_sf2_crossbar_setup(struct bcm_sf2_priv *priv)
469{
470 struct device *dev = priv->dev->ds->dev;
471 int shift;
472 u32 mask;
473 u32 reg;
474 int i;
475
476 mask = BIT(priv->num_crossbar_int_ports) - 1;
477
478 reg = reg_readl(priv, REG_CROSSBAR);
479 switch (priv->type) {
480 case BCM4908_DEVICE_ID:
481 shift = CROSSBAR_BCM4908_INT_P7 * priv->num_crossbar_int_ports;
482 reg &= ~(mask << shift);
483 if (0)
484 reg |= CROSSBAR_BCM4908_EXT_SERDES << shift;
485 else if (priv->int_phy_mask & BIT(7))
486 reg |= CROSSBAR_BCM4908_EXT_GPHY4 << shift;
487 else if (phy_interface_mode_is_rgmii(priv->port_sts[7].mode))
488 reg |= CROSSBAR_BCM4908_EXT_RGMII << shift;
489 else if (WARN(1, "Invalid port mode\n"))
490 return;
491 break;
492 default:
493 return;
494 }
495 reg_writel(priv, reg, REG_CROSSBAR);
496
497 reg = reg_readl(priv, REG_CROSSBAR);
498 for (i = 0; i < priv->num_crossbar_int_ports; i++) {
499 shift = i * priv->num_crossbar_int_ports;
500
501 dev_dbg(dev, "crossbar int port #%d - ext port #%d\n", i,
502 (reg >> shift) & mask);
503 }
504}
505
506static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
507{
508 intrl2_0_mask_set(priv, 0xffffffff);
509 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
510 intrl2_1_mask_set(priv, 0xffffffff);
511 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
512}
513
514static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
515 struct device_node *dn)
516{
517 struct device *dev = priv->dev->ds->dev;
518 struct bcm_sf2_port_status *port_st;
519 struct device_node *port;
520 unsigned int port_num;
521 struct property *prop;
522 int err;
523
524 priv->moca_port = -1;
525
526 for_each_available_child_of_node(dn, port) {
527 if (of_property_read_u32(port, "reg", &port_num))
528 continue;
529
530 if (port_num >= DSA_MAX_PORTS) {
531 dev_err(dev, "Invalid port number %d\n", port_num);
532 continue;
533 }
534
535 port_st = &priv->port_sts[port_num];
536
537
538
539
540
541
542 err = of_get_phy_mode(port, &port_st->mode);
543 if (err)
544 continue;
545
546 if (port_st->mode == PHY_INTERFACE_MODE_INTERNAL)
547 priv->int_phy_mask |= 1 << port_num;
548
549 if (port_st->mode == PHY_INTERFACE_MODE_MOCA)
550 priv->moca_port = port_num;
551
552 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
553 priv->brcm_tag_mask |= 1 << port_num;
554
555
556
557
558
559 if (port_num == 5 && priv->type == BCM7278_DEVICE_ID) {
560 prop = of_find_property(port, "ethernet", NULL);
561 if (prop)
562 of_remove_property(port, prop);
563 }
564 }
565}
566
567static int bcm_sf2_mdio_register(struct dsa_switch *ds)
568{
569 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
570 struct device_node *dn, *child;
571 struct phy_device *phydev;
572 struct property *prop;
573 static int index;
574 int err, reg;
575
576
577 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
578 priv->master_mii_bus = of_mdio_find_bus(dn);
579 if (!priv->master_mii_bus) {
580 of_node_put(dn);
581 return -EPROBE_DEFER;
582 }
583
584 get_device(&priv->master_mii_bus->dev);
585 priv->master_mii_dn = dn;
586
587 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
588 if (!priv->slave_mii_bus) {
589 of_node_put(dn);
590 return -ENOMEM;
591 }
592
593 priv->slave_mii_bus->priv = priv;
594 priv->slave_mii_bus->name = "sf2 slave mii";
595 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
596 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
597 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
598 index++);
599 priv->slave_mii_bus->dev.of_node = dn;
600
601
602
603
604
605
606
607
608
609
610
611 if (of_machine_is_compatible("brcm,bcm7445d0"))
612 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0);
613 else
614 priv->indir_phy_mask = 0;
615
616 ds->phys_mii_mask = priv->indir_phy_mask;
617 ds->slave_mii_bus = priv->slave_mii_bus;
618 priv->slave_mii_bus->parent = ds->dev->parent;
619 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
620
621
622
623
624
625 for_each_available_child_of_node(dn, child) {
626 if (of_property_read_u32(child, "reg", ®) ||
627 reg >= PHY_MAX_ADDR)
628 continue;
629
630 if (!(priv->indir_phy_mask & BIT(reg)))
631 continue;
632
633 prop = of_find_property(child, "phandle", NULL);
634 if (prop)
635 of_remove_property(child, prop);
636
637 prop = of_find_property(child, "linux,phandle", NULL);
638 if (prop)
639 of_remove_property(child, prop);
640
641 phydev = of_phy_find_device(child);
642 if (phydev)
643 phy_device_remove(phydev);
644 }
645
646 err = mdiobus_register(priv->slave_mii_bus);
647 if (err && dn)
648 of_node_put(dn);
649
650 return err;
651}
652
653static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
654{
655 mdiobus_unregister(priv->slave_mii_bus);
656 of_node_put(priv->master_mii_dn);
657}
658
659static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
660{
661 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
662
663
664
665
666
667 if (priv->int_phy_mask & BIT(port))
668 return priv->hw_params.gphy_rev;
669 else
670 return 0;
671}
672
673static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
674 unsigned long *supported,
675 struct phylink_link_state *state)
676{
677 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
678 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
679
680 if (!phy_interface_mode_is_rgmii(state->interface) &&
681 state->interface != PHY_INTERFACE_MODE_MII &&
682 state->interface != PHY_INTERFACE_MODE_REVMII &&
683 state->interface != PHY_INTERFACE_MODE_GMII &&
684 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
685 state->interface != PHY_INTERFACE_MODE_MOCA) {
686 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
687 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
688 dev_err(ds->dev,
689 "Unsupported interface: %d for port %d\n",
690 state->interface, port);
691 return;
692 }
693
694
695 phylink_set(mask, Autoneg);
696 phylink_set_port_modes(mask);
697 phylink_set(mask, Pause);
698 phylink_set(mask, Asym_Pause);
699
700
701
702
703 if (state->interface != PHY_INTERFACE_MODE_MII &&
704 state->interface != PHY_INTERFACE_MODE_REVMII) {
705 phylink_set(mask, 1000baseT_Full);
706 phylink_set(mask, 1000baseT_Half);
707 }
708
709 phylink_set(mask, 10baseT_Half);
710 phylink_set(mask, 10baseT_Full);
711 phylink_set(mask, 100baseT_Half);
712 phylink_set(mask, 100baseT_Full);
713
714 bitmap_and(supported, supported, mask,
715 __ETHTOOL_LINK_MODE_MASK_NBITS);
716 bitmap_and(state->advertising, state->advertising, mask,
717 __ETHTOOL_LINK_MODE_MASK_NBITS);
718}
719
720static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
721 unsigned int mode,
722 const struct phylink_link_state *state)
723{
724 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
725 u32 id_mode_dis = 0, port_mode;
726 u32 reg_rgmii_ctrl;
727 u32 reg;
728
729 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
730 return;
731
732 switch (state->interface) {
733 case PHY_INTERFACE_MODE_RGMII:
734 id_mode_dis = 1;
735 fallthrough;
736 case PHY_INTERFACE_MODE_RGMII_TXID:
737 port_mode = EXT_GPHY;
738 break;
739 case PHY_INTERFACE_MODE_MII:
740 port_mode = EXT_EPHY;
741 break;
742 case PHY_INTERFACE_MODE_REVMII:
743 port_mode = EXT_REVMII;
744 break;
745 default:
746
747 return;
748 }
749
750 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
751
752
753
754
755 reg = reg_readl(priv, reg_rgmii_ctrl);
756 reg &= ~ID_MODE_DIS;
757 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
758
759 reg |= port_mode;
760 if (id_mode_dis)
761 reg |= ID_MODE_DIS;
762
763 reg_writel(priv, reg, reg_rgmii_ctrl);
764}
765
766static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
767 phy_interface_t interface, bool link)
768{
769 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
770 u32 reg_rgmii_ctrl;
771 u32 reg;
772
773 if (!phy_interface_mode_is_rgmii(interface) &&
774 interface != PHY_INTERFACE_MODE_MII &&
775 interface != PHY_INTERFACE_MODE_REVMII)
776 return;
777
778 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
779
780
781 reg = reg_readl(priv, reg_rgmii_ctrl);
782 if (link)
783 reg |= RGMII_MODE_EN;
784 else
785 reg &= ~RGMII_MODE_EN;
786 reg_writel(priv, reg, reg_rgmii_ctrl);
787}
788
789static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
790 unsigned int mode,
791 phy_interface_t interface)
792{
793 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
794 u32 reg, offset;
795
796 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
797 if (priv->type == BCM4908_DEVICE_ID ||
798 priv->type == BCM7445_DEVICE_ID)
799 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
800 else
801 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
802
803 reg = core_readl(priv, offset);
804 reg &= ~LINK_STS;
805 core_writel(priv, reg, offset);
806 }
807
808 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
809}
810
811static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
812 unsigned int mode,
813 phy_interface_t interface,
814 struct phy_device *phydev,
815 int speed, int duplex,
816 bool tx_pause, bool rx_pause)
817{
818 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
819 struct ethtool_eee *p = &priv->dev->ports[port].eee;
820
821 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
822
823 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
824 u32 reg_rgmii_ctrl = 0;
825 u32 reg, offset;
826
827 if (priv->type == BCM4908_DEVICE_ID ||
828 priv->type == BCM7445_DEVICE_ID)
829 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
830 else
831 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
832
833 if (interface == PHY_INTERFACE_MODE_RGMII ||
834 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
835 interface == PHY_INTERFACE_MODE_MII ||
836 interface == PHY_INTERFACE_MODE_REVMII) {
837 reg_rgmii_ctrl = bcm_sf2_reg_rgmii_cntrl(priv, port);
838 reg = reg_readl(priv, reg_rgmii_ctrl);
839 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
840
841 if (tx_pause)
842 reg |= TX_PAUSE_EN;
843 if (rx_pause)
844 reg |= RX_PAUSE_EN;
845
846 reg_writel(priv, reg, reg_rgmii_ctrl);
847 }
848
849 reg = SW_OVERRIDE | LINK_STS;
850 switch (speed) {
851 case SPEED_1000:
852 reg |= SPDSTS_1000 << SPEED_SHIFT;
853 break;
854 case SPEED_100:
855 reg |= SPDSTS_100 << SPEED_SHIFT;
856 break;
857 }
858
859 if (duplex == DUPLEX_FULL)
860 reg |= DUPLX_MODE;
861
862 core_writel(priv, reg, offset);
863 }
864
865 if (mode == MLO_AN_PHY && phydev)
866 p->eee_enabled = b53_eee_init(ds, port, phydev);
867}
868
869static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
870 struct phylink_link_state *status)
871{
872 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
873
874 status->link = false;
875
876
877
878
879
880
881
882
883
884 if (port == priv->moca_port) {
885 status->link = priv->port_sts[port].link;
886
887
888
889
890
891 if (!status->link)
892 netif_carrier_off(dsa_to_port(ds, port)->slave);
893 status->duplex = DUPLEX_FULL;
894 } else {
895 status->link = true;
896 }
897}
898
899static void bcm_sf2_enable_acb(struct dsa_switch *ds)
900{
901 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
902 u32 reg;
903
904
905 reg = acb_readl(priv, ACB_CONTROL);
906 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
907 acb_writel(priv, reg, ACB_CONTROL);
908 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
909 reg |= ACB_EN | ACB_ALGORITHM;
910 acb_writel(priv, reg, ACB_CONTROL);
911}
912
913static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
914{
915 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
916 unsigned int port;
917
918 bcm_sf2_intr_disable(priv);
919
920
921
922
923
924 for (port = 0; port < ds->num_ports; port++) {
925 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
926 bcm_sf2_port_disable(ds, port);
927 }
928
929 if (!priv->wol_ports_mask)
930 clk_disable_unprepare(priv->clk);
931
932 return 0;
933}
934
935static int bcm_sf2_sw_resume(struct dsa_switch *ds)
936{
937 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
938 int ret;
939
940 if (!priv->wol_ports_mask)
941 clk_prepare_enable(priv->clk);
942
943 ret = bcm_sf2_sw_rst(priv);
944 if (ret) {
945 pr_err("%s: failed to software reset switch\n", __func__);
946 return ret;
947 }
948
949 bcm_sf2_crossbar_setup(priv);
950
951 ret = bcm_sf2_cfp_resume(ds);
952 if (ret)
953 return ret;
954
955 if (priv->hw_params.num_gphy == 1)
956 bcm_sf2_gphy_enable_set(ds, true);
957
958 ds->ops->setup(ds);
959
960 return 0;
961}
962
963static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
964 struct ethtool_wolinfo *wol)
965{
966 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
967 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
968 struct ethtool_wolinfo pwol = { };
969
970
971 if (p->ethtool_ops->get_wol)
972 p->ethtool_ops->get_wol(p, &pwol);
973
974
975 wol->supported = pwol.supported;
976 memset(&wol->sopass, 0, sizeof(wol->sopass));
977
978 if (pwol.wolopts & WAKE_MAGICSECURE)
979 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
980
981 if (priv->wol_ports_mask & (1 << port))
982 wol->wolopts = pwol.wolopts;
983 else
984 wol->wolopts = 0;
985}
986
987static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
988 struct ethtool_wolinfo *wol)
989{
990 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
991 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
992 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
993 struct ethtool_wolinfo pwol = { };
994
995 if (p->ethtool_ops->get_wol)
996 p->ethtool_ops->get_wol(p, &pwol);
997 if (wol->wolopts & ~pwol.supported)
998 return -EINVAL;
999
1000 if (wol->wolopts)
1001 priv->wol_ports_mask |= (1 << port);
1002 else
1003 priv->wol_ports_mask &= ~(1 << port);
1004
1005
1006
1007
1008
1009 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1010 priv->wol_ports_mask |= (1 << cpu_port);
1011 else
1012 priv->wol_ports_mask &= ~(1 << cpu_port);
1013
1014 return p->ethtool_ops->set_wol(p, wol);
1015}
1016
1017static int bcm_sf2_sw_setup(struct dsa_switch *ds)
1018{
1019 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
1020 unsigned int port;
1021
1022
1023 for (port = 0; port < priv->hw_params.num_ports; port++) {
1024
1025 if (dsa_is_user_port(ds, port))
1026 bcm_sf2_port_setup(ds, port, NULL);
1027 else if (dsa_is_cpu_port(ds, port))
1028 bcm_sf2_imp_setup(ds, port);
1029 else
1030 bcm_sf2_port_disable(ds, port);
1031 }
1032
1033 b53_configure_vlan(ds);
1034 bcm_sf2_enable_acb(ds);
1035
1036 return b53_setup_devlink_resources(ds);
1037}
1038
1039static void bcm_sf2_sw_teardown(struct dsa_switch *ds)
1040{
1041 dsa_devlink_resources_unregister(ds);
1042}
1043
1044
1045
1046
1047
1048#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
1049
1050static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
1051 u8 *val)
1052{
1053 struct bcm_sf2_priv *priv = dev->priv;
1054
1055 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1056
1057 return 0;
1058}
1059
1060static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
1061 u16 *val)
1062{
1063 struct bcm_sf2_priv *priv = dev->priv;
1064
1065 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1066
1067 return 0;
1068}
1069
1070static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
1071 u32 *val)
1072{
1073 struct bcm_sf2_priv *priv = dev->priv;
1074
1075 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
1076
1077 return 0;
1078}
1079
1080static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
1081 u64 *val)
1082{
1083 struct bcm_sf2_priv *priv = dev->priv;
1084
1085 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
1086
1087 return 0;
1088}
1089
1090static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
1091 u8 value)
1092{
1093 struct bcm_sf2_priv *priv = dev->priv;
1094
1095 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1096
1097 return 0;
1098}
1099
1100static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
1101 u16 value)
1102{
1103 struct bcm_sf2_priv *priv = dev->priv;
1104
1105 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1106
1107 return 0;
1108}
1109
1110static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
1111 u32 value)
1112{
1113 struct bcm_sf2_priv *priv = dev->priv;
1114
1115 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1116
1117 return 0;
1118}
1119
1120static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
1121 u64 value)
1122{
1123 struct bcm_sf2_priv *priv = dev->priv;
1124
1125 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
1126
1127 return 0;
1128}
1129
1130static const struct b53_io_ops bcm_sf2_io_ops = {
1131 .read8 = bcm_sf2_core_read8,
1132 .read16 = bcm_sf2_core_read16,
1133 .read32 = bcm_sf2_core_read32,
1134 .read48 = bcm_sf2_core_read64,
1135 .read64 = bcm_sf2_core_read64,
1136 .write8 = bcm_sf2_core_write8,
1137 .write16 = bcm_sf2_core_write16,
1138 .write32 = bcm_sf2_core_write32,
1139 .write48 = bcm_sf2_core_write64,
1140 .write64 = bcm_sf2_core_write64,
1141};
1142
1143static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
1144 u32 stringset, uint8_t *data)
1145{
1146 int cnt = b53_get_sset_count(ds, port, stringset);
1147
1148 b53_get_strings(ds, port, stringset, data);
1149 bcm_sf2_cfp_get_strings(ds, port, stringset,
1150 data + cnt * ETH_GSTRING_LEN);
1151}
1152
1153static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
1154 uint64_t *data)
1155{
1156 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
1157
1158 b53_get_ethtool_stats(ds, port, data);
1159 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
1160}
1161
1162static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
1163 int sset)
1164{
1165 int cnt = b53_get_sset_count(ds, port, sset);
1166
1167 if (cnt < 0)
1168 return cnt;
1169
1170 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
1171
1172 return cnt;
1173}
1174
1175static const struct dsa_switch_ops bcm_sf2_ops = {
1176 .get_tag_protocol = b53_get_tag_protocol,
1177 .setup = bcm_sf2_sw_setup,
1178 .teardown = bcm_sf2_sw_teardown,
1179 .get_strings = bcm_sf2_sw_get_strings,
1180 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1181 .get_sset_count = bcm_sf2_sw_get_sset_count,
1182 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
1183 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1184 .phylink_validate = bcm_sf2_sw_validate,
1185 .phylink_mac_config = bcm_sf2_sw_mac_config,
1186 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
1187 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
1188 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
1189 .suspend = bcm_sf2_sw_suspend,
1190 .resume = bcm_sf2_sw_resume,
1191 .get_wol = bcm_sf2_sw_get_wol,
1192 .set_wol = bcm_sf2_sw_set_wol,
1193 .port_enable = bcm_sf2_port_setup,
1194 .port_disable = bcm_sf2_port_disable,
1195 .get_mac_eee = b53_get_mac_eee,
1196 .set_mac_eee = b53_set_mac_eee,
1197 .port_bridge_join = b53_br_join,
1198 .port_bridge_leave = b53_br_leave,
1199 .port_pre_bridge_flags = b53_br_flags_pre,
1200 .port_bridge_flags = b53_br_flags,
1201 .port_stp_state_set = b53_br_set_stp_state,
1202 .port_set_mrouter = b53_set_mrouter,
1203 .port_fast_age = b53_br_fast_age,
1204 .port_vlan_filtering = b53_vlan_filtering,
1205 .port_vlan_add = b53_vlan_add,
1206 .port_vlan_del = b53_vlan_del,
1207 .port_fdb_dump = b53_fdb_dump,
1208 .port_fdb_add = b53_fdb_add,
1209 .port_fdb_del = b53_fdb_del,
1210 .get_rxnfc = bcm_sf2_get_rxnfc,
1211 .set_rxnfc = bcm_sf2_set_rxnfc,
1212 .port_mirror_add = b53_mirror_add,
1213 .port_mirror_del = b53_mirror_del,
1214 .port_mdb_add = b53_mdb_add,
1215 .port_mdb_del = b53_mdb_del,
1216};
1217
1218struct bcm_sf2_of_data {
1219 u32 type;
1220 const u16 *reg_offsets;
1221 unsigned int core_reg_align;
1222 unsigned int num_cfp_rules;
1223 unsigned int num_crossbar_int_ports;
1224};
1225
1226static const u16 bcm_sf2_4908_reg_offsets[] = {
1227 [REG_SWITCH_CNTRL] = 0x00,
1228 [REG_SWITCH_STATUS] = 0x04,
1229 [REG_DIR_DATA_WRITE] = 0x08,
1230 [REG_DIR_DATA_READ] = 0x0c,
1231 [REG_SWITCH_REVISION] = 0x10,
1232 [REG_PHY_REVISION] = 0x14,
1233 [REG_SPHY_CNTRL] = 0x24,
1234 [REG_CROSSBAR] = 0xc8,
1235 [REG_RGMII_11_CNTRL] = 0x014c,
1236 [REG_LED_0_CNTRL] = 0x40,
1237 [REG_LED_1_CNTRL] = 0x4c,
1238 [REG_LED_2_CNTRL] = 0x58,
1239};
1240
1241static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
1242 .type = BCM4908_DEVICE_ID,
1243 .core_reg_align = 0,
1244 .reg_offsets = bcm_sf2_4908_reg_offsets,
1245 .num_cfp_rules = 256,
1246 .num_crossbar_int_ports = 2,
1247};
1248
1249
1250static const u16 bcm_sf2_7445_reg_offsets[] = {
1251 [REG_SWITCH_CNTRL] = 0x00,
1252 [REG_SWITCH_STATUS] = 0x04,
1253 [REG_DIR_DATA_WRITE] = 0x08,
1254 [REG_DIR_DATA_READ] = 0x0C,
1255 [REG_SWITCH_REVISION] = 0x18,
1256 [REG_PHY_REVISION] = 0x1C,
1257 [REG_SPHY_CNTRL] = 0x2C,
1258 [REG_RGMII_0_CNTRL] = 0x34,
1259 [REG_RGMII_1_CNTRL] = 0x40,
1260 [REG_RGMII_2_CNTRL] = 0x4c,
1261 [REG_LED_0_CNTRL] = 0x90,
1262 [REG_LED_1_CNTRL] = 0x94,
1263 [REG_LED_2_CNTRL] = 0x98,
1264};
1265
1266static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1267 .type = BCM7445_DEVICE_ID,
1268 .core_reg_align = 0,
1269 .reg_offsets = bcm_sf2_7445_reg_offsets,
1270 .num_cfp_rules = 256,
1271};
1272
1273static const u16 bcm_sf2_7278_reg_offsets[] = {
1274 [REG_SWITCH_CNTRL] = 0x00,
1275 [REG_SWITCH_STATUS] = 0x04,
1276 [REG_DIR_DATA_WRITE] = 0x08,
1277 [REG_DIR_DATA_READ] = 0x0c,
1278 [REG_SWITCH_REVISION] = 0x10,
1279 [REG_PHY_REVISION] = 0x14,
1280 [REG_SPHY_CNTRL] = 0x24,
1281 [REG_RGMII_0_CNTRL] = 0xe0,
1282 [REG_RGMII_1_CNTRL] = 0xec,
1283 [REG_RGMII_2_CNTRL] = 0xf8,
1284 [REG_LED_0_CNTRL] = 0x40,
1285 [REG_LED_1_CNTRL] = 0x4c,
1286 [REG_LED_2_CNTRL] = 0x58,
1287};
1288
1289static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1290 .type = BCM7278_DEVICE_ID,
1291 .core_reg_align = 1,
1292 .reg_offsets = bcm_sf2_7278_reg_offsets,
1293 .num_cfp_rules = 128,
1294};
1295
1296static const struct of_device_id bcm_sf2_of_match[] = {
1297 { .compatible = "brcm,bcm4908-switch",
1298 .data = &bcm_sf2_4908_data
1299 },
1300 { .compatible = "brcm,bcm7445-switch-v4.0",
1301 .data = &bcm_sf2_7445_data
1302 },
1303 { .compatible = "brcm,bcm7278-switch-v4.0",
1304 .data = &bcm_sf2_7278_data
1305 },
1306 { .compatible = "brcm,bcm7278-switch-v4.8",
1307 .data = &bcm_sf2_7278_data
1308 },
1309 { },
1310};
1311MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1312
1313static int bcm_sf2_sw_probe(struct platform_device *pdev)
1314{
1315 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1316 struct device_node *dn = pdev->dev.of_node;
1317 const struct of_device_id *of_id = NULL;
1318 const struct bcm_sf2_of_data *data;
1319 struct b53_platform_data *pdata;
1320 struct dsa_switch_ops *ops;
1321 struct device_node *ports;
1322 struct bcm_sf2_priv *priv;
1323 struct b53_device *dev;
1324 struct dsa_switch *ds;
1325 void __iomem **base;
1326 unsigned int i;
1327 u32 reg, rev;
1328 int ret;
1329
1330 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1331 if (!priv)
1332 return -ENOMEM;
1333
1334 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1335 if (!ops)
1336 return -ENOMEM;
1337
1338 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1339 if (!dev)
1340 return -ENOMEM;
1341
1342 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1343 if (!pdata)
1344 return -ENOMEM;
1345
1346 of_id = of_match_node(bcm_sf2_of_match, dn);
1347 if (!of_id || !of_id->data)
1348 return -EINVAL;
1349
1350 data = of_id->data;
1351
1352
1353 priv->type = data->type;
1354 priv->reg_offsets = data->reg_offsets;
1355 priv->core_reg_align = data->core_reg_align;
1356 priv->num_cfp_rules = data->num_cfp_rules;
1357 priv->num_crossbar_int_ports = data->num_crossbar_int_ports;
1358
1359 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1360 "switch");
1361 if (IS_ERR(priv->rcdev))
1362 return PTR_ERR(priv->rcdev);
1363
1364
1365
1366
1367
1368 pdata->chip_id = priv->type;
1369 dev->pdata = pdata;
1370
1371 priv->dev = dev;
1372 ds = dev->ds;
1373 ds->ops = &bcm_sf2_ops;
1374
1375
1376 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1377
1378 dev_set_drvdata(&pdev->dev, priv);
1379
1380 spin_lock_init(&priv->indir_lock);
1381 mutex_init(&priv->cfp.lock);
1382 INIT_LIST_HEAD(&priv->cfp.rules_list);
1383
1384
1385
1386
1387 set_bit(0, priv->cfp.used);
1388 set_bit(0, priv->cfp.unique);
1389
1390
1391 of_node_get(dn);
1392 ports = of_find_node_by_name(dn, "ports");
1393 if (ports) {
1394 bcm_sf2_identify_ports(priv, ports);
1395 of_node_put(ports);
1396 }
1397
1398 priv->irq0 = irq_of_parse_and_map(dn, 0);
1399 priv->irq1 = irq_of_parse_and_map(dn, 1);
1400
1401 base = &priv->core;
1402 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1403 *base = devm_platform_ioremap_resource(pdev, i);
1404 if (IS_ERR(*base)) {
1405 pr_err("unable to find register: %s\n", reg_names[i]);
1406 return PTR_ERR(*base);
1407 }
1408 base++;
1409 }
1410
1411 priv->clk = devm_clk_get_optional(&pdev->dev, "sw_switch");
1412 if (IS_ERR(priv->clk))
1413 return PTR_ERR(priv->clk);
1414
1415 clk_prepare_enable(priv->clk);
1416
1417 priv->clk_mdiv = devm_clk_get_optional(&pdev->dev, "sw_switch_mdiv");
1418 if (IS_ERR(priv->clk_mdiv)) {
1419 ret = PTR_ERR(priv->clk_mdiv);
1420 goto out_clk;
1421 }
1422
1423 clk_prepare_enable(priv->clk_mdiv);
1424
1425 ret = bcm_sf2_sw_rst(priv);
1426 if (ret) {
1427 pr_err("unable to software reset switch: %d\n", ret);
1428 goto out_clk_mdiv;
1429 }
1430
1431 bcm_sf2_crossbar_setup(priv);
1432
1433 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1434
1435 ret = bcm_sf2_mdio_register(ds);
1436 if (ret) {
1437 pr_err("failed to register MDIO bus\n");
1438 goto out_clk_mdiv;
1439 }
1440
1441 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1442
1443 ret = bcm_sf2_cfp_rst(priv);
1444 if (ret) {
1445 pr_err("failed to reset CFP\n");
1446 goto out_mdio;
1447 }
1448
1449
1450 bcm_sf2_intr_disable(priv);
1451
1452 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1453 "switch_0", ds);
1454 if (ret < 0) {
1455 pr_err("failed to request switch_0 IRQ\n");
1456 goto out_mdio;
1457 }
1458
1459 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1460 "switch_1", ds);
1461 if (ret < 0) {
1462 pr_err("failed to request switch_1 IRQ\n");
1463 goto out_mdio;
1464 }
1465
1466
1467 reg = core_readl(priv, CORE_GMNCFGCFG);
1468 reg |= RST_MIB_CNT;
1469 core_writel(priv, reg, CORE_GMNCFGCFG);
1470 reg &= ~RST_MIB_CNT;
1471 core_writel(priv, reg, CORE_GMNCFGCFG);
1472
1473
1474 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1475 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1476 priv->hw_params.num_ports = DSA_MAX_PORTS;
1477
1478
1479 if (of_property_read_u32(dn, "brcm,num-gphy",
1480 &priv->hw_params.num_gphy))
1481 priv->hw_params.num_gphy = 1;
1482
1483 rev = reg_readl(priv, REG_SWITCH_REVISION);
1484 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1485 SWITCH_TOP_REV_MASK;
1486 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1487
1488 rev = reg_readl(priv, REG_PHY_REVISION);
1489 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1490
1491 ret = b53_switch_register(dev);
1492 if (ret)
1493 goto out_mdio;
1494
1495 dev_info(&pdev->dev,
1496 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1497 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1498 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1499 priv->irq0, priv->irq1);
1500
1501 return 0;
1502
1503out_mdio:
1504 bcm_sf2_mdio_unregister(priv);
1505out_clk_mdiv:
1506 clk_disable_unprepare(priv->clk_mdiv);
1507out_clk:
1508 clk_disable_unprepare(priv->clk);
1509 return ret;
1510}
1511
1512static int bcm_sf2_sw_remove(struct platform_device *pdev)
1513{
1514 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1515
1516 priv->wol_ports_mask = 0;
1517
1518 bcm_sf2_intr_disable(priv);
1519 dsa_unregister_switch(priv->dev->ds);
1520 bcm_sf2_cfp_exit(priv->dev->ds);
1521 bcm_sf2_mdio_unregister(priv);
1522 clk_disable_unprepare(priv->clk_mdiv);
1523 clk_disable_unprepare(priv->clk);
1524 if (priv->type == BCM7278_DEVICE_ID)
1525 reset_control_assert(priv->rcdev);
1526
1527 return 0;
1528}
1529
1530static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1531{
1532 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1533
1534
1535
1536
1537
1538
1539
1540 if (priv->hw_params.num_gphy == 1)
1541 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1542}
1543
1544#ifdef CONFIG_PM_SLEEP
1545static int bcm_sf2_suspend(struct device *dev)
1546{
1547 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1548
1549 return dsa_switch_suspend(priv->dev->ds);
1550}
1551
1552static int bcm_sf2_resume(struct device *dev)
1553{
1554 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1555
1556 return dsa_switch_resume(priv->dev->ds);
1557}
1558#endif
1559
1560static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1561 bcm_sf2_suspend, bcm_sf2_resume);
1562
1563
1564static struct platform_driver bcm_sf2_driver = {
1565 .probe = bcm_sf2_sw_probe,
1566 .remove = bcm_sf2_sw_remove,
1567 .shutdown = bcm_sf2_sw_shutdown,
1568 .driver = {
1569 .name = "brcm-sf2",
1570 .of_match_table = bcm_sf2_of_match,
1571 .pm = &bcm_sf2_pm_ops,
1572 },
1573};
1574module_platform_driver(bcm_sf2_driver);
1575
1576MODULE_AUTHOR("Broadcom Corporation");
1577MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1578MODULE_LICENSE("GPL");
1579MODULE_ALIAS("platform:brcm-sf2");
1580
