linux/drivers/mmc/host/omap.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 *  linux/drivers/mmc/host/omap.c
   4 *
   5 *  Copyright (C) 2004 Nokia Corporation
   6 *  Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
   7 *  Misc hacks here and there by Tony Lindgren <tony@atomide.com>
   8 *  Other hacks (DMA, SD, etc) by David Brownell
   9 */
  10
  11#include <linux/module.h>
  12#include <linux/moduleparam.h>
  13#include <linux/init.h>
  14#include <linux/ioport.h>
  15#include <linux/platform_device.h>
  16#include <linux/interrupt.h>
  17#include <linux/dmaengine.h>
  18#include <linux/dma-mapping.h>
  19#include <linux/delay.h>
  20#include <linux/spinlock.h>
  21#include <linux/timer.h>
  22#include <linux/of.h>
  23#include <linux/mmc/host.h>
  24#include <linux/mmc/card.h>
  25#include <linux/mmc/mmc.h>
  26#include <linux/clk.h>
  27#include <linux/scatterlist.h>
  28#include <linux/slab.h>
  29#include <linux/platform_data/mmc-omap.h>
  30
  31
  32#define OMAP_MMC_REG_CMD        0x00
  33#define OMAP_MMC_REG_ARGL       0x01
  34#define OMAP_MMC_REG_ARGH       0x02
  35#define OMAP_MMC_REG_CON        0x03
  36#define OMAP_MMC_REG_STAT       0x04
  37#define OMAP_MMC_REG_IE         0x05
  38#define OMAP_MMC_REG_CTO        0x06
  39#define OMAP_MMC_REG_DTO        0x07
  40#define OMAP_MMC_REG_DATA       0x08
  41#define OMAP_MMC_REG_BLEN       0x09
  42#define OMAP_MMC_REG_NBLK       0x0a
  43#define OMAP_MMC_REG_BUF        0x0b
  44#define OMAP_MMC_REG_SDIO       0x0d
  45#define OMAP_MMC_REG_REV        0x0f
  46#define OMAP_MMC_REG_RSP0       0x10
  47#define OMAP_MMC_REG_RSP1       0x11
  48#define OMAP_MMC_REG_RSP2       0x12
  49#define OMAP_MMC_REG_RSP3       0x13
  50#define OMAP_MMC_REG_RSP4       0x14
  51#define OMAP_MMC_REG_RSP5       0x15
  52#define OMAP_MMC_REG_RSP6       0x16
  53#define OMAP_MMC_REG_RSP7       0x17
  54#define OMAP_MMC_REG_IOSR       0x18
  55#define OMAP_MMC_REG_SYSC       0x19
  56#define OMAP_MMC_REG_SYSS       0x1a
  57
  58#define OMAP_MMC_STAT_CARD_ERR          (1 << 14)
  59#define OMAP_MMC_STAT_CARD_IRQ          (1 << 13)
  60#define OMAP_MMC_STAT_OCR_BUSY          (1 << 12)
  61#define OMAP_MMC_STAT_A_EMPTY           (1 << 11)
  62#define OMAP_MMC_STAT_A_FULL            (1 << 10)
  63#define OMAP_MMC_STAT_CMD_CRC           (1 <<  8)
  64#define OMAP_MMC_STAT_CMD_TOUT          (1 <<  7)
  65#define OMAP_MMC_STAT_DATA_CRC          (1 <<  6)
  66#define OMAP_MMC_STAT_DATA_TOUT         (1 <<  5)
  67#define OMAP_MMC_STAT_END_BUSY          (1 <<  4)
  68#define OMAP_MMC_STAT_END_OF_DATA       (1 <<  3)
  69#define OMAP_MMC_STAT_CARD_BUSY         (1 <<  2)
  70#define OMAP_MMC_STAT_END_OF_CMD        (1 <<  0)
  71
  72#define mmc_omap7xx()   (host->features & MMC_OMAP7XX)
  73#define mmc_omap15xx()  (host->features & MMC_OMAP15XX)
  74#define mmc_omap16xx()  (host->features & MMC_OMAP16XX)
  75#define MMC_OMAP1_MASK  (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
  76#define mmc_omap1()     (host->features & MMC_OMAP1_MASK)
  77#define mmc_omap2()     (!mmc_omap1())
  78
  79#define OMAP_MMC_REG(host, reg)         (OMAP_MMC_REG_##reg << (host)->reg_shift)
  80#define OMAP_MMC_READ(host, reg)        __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
  81#define OMAP_MMC_WRITE(host, reg, val)  __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
  82
  83/*
  84 * Command types
  85 */
  86#define OMAP_MMC_CMDTYPE_BC     0
  87#define OMAP_MMC_CMDTYPE_BCR    1
  88#define OMAP_MMC_CMDTYPE_AC     2
  89#define OMAP_MMC_CMDTYPE_ADTC   3
  90
  91#define DRIVER_NAME "mmci-omap"
  92
  93/* Specifies how often in millisecs to poll for card status changes
  94 * when the cover switch is open */
  95#define OMAP_MMC_COVER_POLL_DELAY       500
  96
  97struct mmc_omap_host;
  98
  99struct mmc_omap_slot {
 100        int                     id;
 101        unsigned int            vdd;
 102        u16                     saved_con;
 103        u16                     bus_mode;
 104        u16                     power_mode;
 105        unsigned int            fclk_freq;
 106
 107        struct tasklet_struct   cover_tasklet;
 108        struct timer_list       cover_timer;
 109        unsigned                cover_open;
 110
 111        struct mmc_request      *mrq;
 112        struct mmc_omap_host    *host;
 113        struct mmc_host         *mmc;
 114        struct omap_mmc_slot_data *pdata;
 115};
 116
 117struct mmc_omap_host {
 118        int                     initialized;
 119        struct mmc_request *    mrq;
 120        struct mmc_command *    cmd;
 121        struct mmc_data *       data;
 122        struct mmc_host *       mmc;
 123        struct device *         dev;
 124        unsigned char           id; /* 16xx chips have 2 MMC blocks */
 125        struct clk *            iclk;
 126        struct clk *            fclk;
 127        struct dma_chan         *dma_rx;
 128        u32                     dma_rx_burst;
 129        struct dma_chan         *dma_tx;
 130        u32                     dma_tx_burst;
 131        void __iomem            *virt_base;
 132        unsigned int            phys_base;
 133        int                     irq;
 134        unsigned char           bus_mode;
 135        unsigned int            reg_shift;
 136
 137        struct work_struct      cmd_abort_work;
 138        unsigned                abort:1;
 139        struct timer_list       cmd_abort_timer;
 140
 141        struct work_struct      slot_release_work;
 142        struct mmc_omap_slot    *next_slot;
 143        struct work_struct      send_stop_work;
 144        struct mmc_data         *stop_data;
 145
 146        unsigned int            sg_len;
 147        int                     sg_idx;
 148        u16 *                   buffer;
 149        u32                     buffer_bytes_left;
 150        u32                     total_bytes_left;
 151
 152        unsigned                features;
 153        unsigned                brs_received:1, dma_done:1;
 154        unsigned                dma_in_use:1;
 155        spinlock_t              dma_lock;
 156
 157        struct mmc_omap_slot    *slots[OMAP_MMC_MAX_SLOTS];
 158        struct mmc_omap_slot    *current_slot;
 159        spinlock_t              slot_lock;
 160        wait_queue_head_t       slot_wq;
 161        int                     nr_slots;
 162
 163        struct timer_list       clk_timer;
 164        spinlock_t              clk_lock;     /* for changing enabled state */
 165        unsigned int            fclk_enabled:1;
 166        struct workqueue_struct *mmc_omap_wq;
 167
 168        struct omap_mmc_platform_data *pdata;
 169};
 170
 171
 172static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
 173{
 174        unsigned long tick_ns;
 175
 176        if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
 177                tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
 178                ndelay(8 * tick_ns);
 179        }
 180}
 181
 182static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
 183{
 184        unsigned long flags;
 185
 186        spin_lock_irqsave(&host->clk_lock, flags);
 187        if (host->fclk_enabled != enable) {
 188                host->fclk_enabled = enable;
 189                if (enable)
 190                        clk_enable(host->fclk);
 191                else
 192                        clk_disable(host->fclk);
 193        }
 194        spin_unlock_irqrestore(&host->clk_lock, flags);
 195}
 196
 197static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
 198{
 199        struct mmc_omap_host *host = slot->host;
 200        unsigned long flags;
 201
 202        if (claimed)
 203                goto no_claim;
 204        spin_lock_irqsave(&host->slot_lock, flags);
 205        while (host->mmc != NULL) {
 206                spin_unlock_irqrestore(&host->slot_lock, flags);
 207                wait_event(host->slot_wq, host->mmc == NULL);
 208                spin_lock_irqsave(&host->slot_lock, flags);
 209        }
 210        host->mmc = slot->mmc;
 211        spin_unlock_irqrestore(&host->slot_lock, flags);
 212no_claim:
 213        del_timer(&host->clk_timer);
 214        if (host->current_slot != slot || !claimed)
 215                mmc_omap_fclk_offdelay(host->current_slot);
 216
 217        if (host->current_slot != slot) {
 218                OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
 219                if (host->pdata->switch_slot != NULL)
 220                        host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
 221                host->current_slot = slot;
 222        }
 223
 224        if (claimed) {
 225                mmc_omap_fclk_enable(host, 1);
 226
 227                /* Doing the dummy read here seems to work around some bug
 228                 * at least in OMAP24xx silicon where the command would not
 229                 * start after writing the CMD register. Sigh. */
 230                OMAP_MMC_READ(host, CON);
 231
 232                OMAP_MMC_WRITE(host, CON, slot->saved_con);
 233        } else
 234                mmc_omap_fclk_enable(host, 0);
 235}
 236
 237static void mmc_omap_start_request(struct mmc_omap_host *host,
 238                                   struct mmc_request *req);
 239
 240static void mmc_omap_slot_release_work(struct work_struct *work)
 241{
 242        struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 243                                                  slot_release_work);
 244        struct mmc_omap_slot *next_slot = host->next_slot;
 245        struct mmc_request *rq;
 246
 247        host->next_slot = NULL;
 248        mmc_omap_select_slot(next_slot, 1);
 249
 250        rq = next_slot->mrq;
 251        next_slot->mrq = NULL;
 252        mmc_omap_start_request(host, rq);
 253}
 254
 255static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
 256{
 257        struct mmc_omap_host *host = slot->host;
 258        unsigned long flags;
 259        int i;
 260
 261        BUG_ON(slot == NULL || host->mmc == NULL);
 262
 263        if (clk_enabled)
 264                /* Keeps clock running for at least 8 cycles on valid freq */
 265                mod_timer(&host->clk_timer, jiffies  + HZ/10);
 266        else {
 267                del_timer(&host->clk_timer);
 268                mmc_omap_fclk_offdelay(slot);
 269                mmc_omap_fclk_enable(host, 0);
 270        }
 271
 272        spin_lock_irqsave(&host->slot_lock, flags);
 273        /* Check for any pending requests */
 274        for (i = 0; i < host->nr_slots; i++) {
 275                struct mmc_omap_slot *new_slot;
 276
 277                if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
 278                        continue;
 279
 280                BUG_ON(host->next_slot != NULL);
 281                new_slot = host->slots[i];
 282                /* The current slot should not have a request in queue */
 283                BUG_ON(new_slot == host->current_slot);
 284
 285                host->next_slot = new_slot;
 286                host->mmc = new_slot->mmc;
 287                spin_unlock_irqrestore(&host->slot_lock, flags);
 288                queue_work(host->mmc_omap_wq, &host->slot_release_work);
 289                return;
 290        }
 291
 292        host->mmc = NULL;
 293        wake_up(&host->slot_wq);
 294        spin_unlock_irqrestore(&host->slot_lock, flags);
 295}
 296
 297static inline
 298int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
 299{
 300        if (slot->pdata->get_cover_state)
 301                return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
 302                                                    slot->id);
 303        return 0;
 304}
 305
 306static ssize_t
 307mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
 308                           char *buf)
 309{
 310        struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 311        struct mmc_omap_slot *slot = mmc_priv(mmc);
 312
 313        return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
 314                       "closed");
 315}
 316
 317static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
 318
 319static ssize_t
 320mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
 321                        char *buf)
 322{
 323        struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 324        struct mmc_omap_slot *slot = mmc_priv(mmc);
 325
 326        return sprintf(buf, "%s\n", slot->pdata->name);
 327}
 328
 329static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
 330
 331static void
 332mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
 333{
 334        u32 cmdreg;
 335        u32 resptype;
 336        u32 cmdtype;
 337        u16 irq_mask;
 338
 339        host->cmd = cmd;
 340
 341        resptype = 0;
 342        cmdtype = 0;
 343
 344        /* Our hardware needs to know exact type */
 345        switch (mmc_resp_type(cmd)) {
 346        case MMC_RSP_NONE:
 347                break;
 348        case MMC_RSP_R1:
 349        case MMC_RSP_R1B:
 350                /* resp 1, 1b, 6, 7 */
 351                resptype = 1;
 352                break;
 353        case MMC_RSP_R2:
 354                resptype = 2;
 355                break;
 356        case MMC_RSP_R3:
 357                resptype = 3;
 358                break;
 359        default:
 360                dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
 361                break;
 362        }
 363
 364        if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
 365                cmdtype = OMAP_MMC_CMDTYPE_ADTC;
 366        } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
 367                cmdtype = OMAP_MMC_CMDTYPE_BC;
 368        } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
 369                cmdtype = OMAP_MMC_CMDTYPE_BCR;
 370        } else {
 371                cmdtype = OMAP_MMC_CMDTYPE_AC;
 372        }
 373
 374        cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
 375
 376        if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
 377                cmdreg |= 1 << 6;
 378
 379        if (cmd->flags & MMC_RSP_BUSY)
 380                cmdreg |= 1 << 11;
 381
 382        if (host->data && !(host->data->flags & MMC_DATA_WRITE))
 383                cmdreg |= 1 << 15;
 384
 385        mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
 386
 387        OMAP_MMC_WRITE(host, CTO, 200);
 388        OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
 389        OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
 390        irq_mask = OMAP_MMC_STAT_A_EMPTY    | OMAP_MMC_STAT_A_FULL    |
 391                   OMAP_MMC_STAT_CMD_CRC    | OMAP_MMC_STAT_CMD_TOUT  |
 392                   OMAP_MMC_STAT_DATA_CRC   | OMAP_MMC_STAT_DATA_TOUT |
 393                   OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR  |
 394                   OMAP_MMC_STAT_END_OF_DATA;
 395        if (cmd->opcode == MMC_ERASE)
 396                irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT;
 397        OMAP_MMC_WRITE(host, IE, irq_mask);
 398        OMAP_MMC_WRITE(host, CMD, cmdreg);
 399}
 400
 401static void
 402mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
 403                     int abort)
 404{
 405        enum dma_data_direction dma_data_dir;
 406        struct device *dev = mmc_dev(host->mmc);
 407        struct dma_chan *c;
 408
 409        if (data->flags & MMC_DATA_WRITE) {
 410                dma_data_dir = DMA_TO_DEVICE;
 411                c = host->dma_tx;
 412        } else {
 413                dma_data_dir = DMA_FROM_DEVICE;
 414                c = host->dma_rx;
 415        }
 416        if (c) {
 417                if (data->error) {
 418                        dmaengine_terminate_all(c);
 419                        /* Claim nothing transferred on error... */
 420                        data->bytes_xfered = 0;
 421                }
 422                dev = c->device->dev;
 423        }
 424        dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
 425}
 426
 427static void mmc_omap_send_stop_work(struct work_struct *work)
 428{
 429        struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 430                                                  send_stop_work);
 431        struct mmc_omap_slot *slot = host->current_slot;
 432        struct mmc_data *data = host->stop_data;
 433        unsigned long tick_ns;
 434
 435        tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq);
 436        ndelay(8*tick_ns);
 437
 438        mmc_omap_start_command(host, data->stop);
 439}
 440
 441static void
 442mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
 443{
 444        if (host->dma_in_use)
 445                mmc_omap_release_dma(host, data, data->error);
 446
 447        host->data = NULL;
 448        host->sg_len = 0;
 449
 450        /* NOTE:  MMC layer will sometimes poll-wait CMD13 next, issuing
 451         * dozens of requests until the card finishes writing data.
 452         * It'd be cheaper to just wait till an EOFB interrupt arrives...
 453         */
 454
 455        if (!data->stop) {
 456                struct mmc_host *mmc;
 457
 458                host->mrq = NULL;
 459                mmc = host->mmc;
 460                mmc_omap_release_slot(host->current_slot, 1);
 461                mmc_request_done(mmc, data->mrq);
 462                return;
 463        }
 464
 465        host->stop_data = data;
 466        queue_work(host->mmc_omap_wq, &host->send_stop_work);
 467}
 468
 469static void
 470mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
 471{
 472        struct mmc_omap_slot *slot = host->current_slot;
 473        unsigned int restarts, passes, timeout;
 474        u16 stat = 0;
 475
 476        /* Sending abort takes 80 clocks. Have some extra and round up */
 477        timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq);
 478        restarts = 0;
 479        while (restarts < maxloops) {
 480                OMAP_MMC_WRITE(host, STAT, 0xFFFF);
 481                OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
 482
 483                passes = 0;
 484                while (passes < timeout) {
 485                        stat = OMAP_MMC_READ(host, STAT);
 486                        if (stat & OMAP_MMC_STAT_END_OF_CMD)
 487                                goto out;
 488                        udelay(1);
 489                        passes++;
 490                }
 491
 492                restarts++;
 493        }
 494out:
 495        OMAP_MMC_WRITE(host, STAT, stat);
 496}
 497
 498static void
 499mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
 500{
 501        if (host->dma_in_use)
 502                mmc_omap_release_dma(host, data, 1);
 503
 504        host->data = NULL;
 505        host->sg_len = 0;
 506
 507        mmc_omap_send_abort(host, 10000);
 508}
 509
 510static void
 511mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
 512{
 513        unsigned long flags;
 514        int done;
 515
 516        if (!host->dma_in_use) {
 517                mmc_omap_xfer_done(host, data);
 518                return;
 519        }
 520        done = 0;
 521        spin_lock_irqsave(&host->dma_lock, flags);
 522        if (host->dma_done)
 523                done = 1;
 524        else
 525                host->brs_received = 1;
 526        spin_unlock_irqrestore(&host->dma_lock, flags);
 527        if (done)
 528                mmc_omap_xfer_done(host, data);
 529}
 530
 531static void
 532mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
 533{
 534        unsigned long flags;
 535        int done;
 536
 537        done = 0;
 538        spin_lock_irqsave(&host->dma_lock, flags);
 539        if (host->brs_received)
 540                done = 1;
 541        else
 542                host->dma_done = 1;
 543        spin_unlock_irqrestore(&host->dma_lock, flags);
 544        if (done)
 545                mmc_omap_xfer_done(host, data);
 546}
 547
 548static void
 549mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
 550{
 551        host->cmd = NULL;
 552
 553        del_timer(&host->cmd_abort_timer);
 554
 555        if (cmd->flags & MMC_RSP_PRESENT) {
 556                if (cmd->flags & MMC_RSP_136) {
 557                        /* response type 2 */
 558                        cmd->resp[3] =
 559                                OMAP_MMC_READ(host, RSP0) |
 560                                (OMAP_MMC_READ(host, RSP1) << 16);
 561                        cmd->resp[2] =
 562                                OMAP_MMC_READ(host, RSP2) |
 563                                (OMAP_MMC_READ(host, RSP3) << 16);
 564                        cmd->resp[1] =
 565                                OMAP_MMC_READ(host, RSP4) |
 566                                (OMAP_MMC_READ(host, RSP5) << 16);
 567                        cmd->resp[0] =
 568                                OMAP_MMC_READ(host, RSP6) |
 569                                (OMAP_MMC_READ(host, RSP7) << 16);
 570                } else {
 571                        /* response types 1, 1b, 3, 4, 5, 6 */
 572                        cmd->resp[0] =
 573                                OMAP_MMC_READ(host, RSP6) |
 574                                (OMAP_MMC_READ(host, RSP7) << 16);
 575                }
 576        }
 577
 578        if (host->data == NULL || cmd->error) {
 579                struct mmc_host *mmc;
 580
 581                if (host->data != NULL)
 582                        mmc_omap_abort_xfer(host, host->data);
 583                host->mrq = NULL;
 584                mmc = host->mmc;
 585                mmc_omap_release_slot(host->current_slot, 1);
 586                mmc_request_done(mmc, cmd->mrq);
 587        }
 588}
 589
 590/*
 591 * Abort stuck command. Can occur when card is removed while it is being
 592 * read.
 593 */
 594static void mmc_omap_abort_command(struct work_struct *work)
 595{
 596        struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
 597                                                  cmd_abort_work);
 598        BUG_ON(!host->cmd);
 599
 600        dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
 601                host->cmd->opcode);
 602
 603        if (host->cmd->error == 0)
 604                host->cmd->error = -ETIMEDOUT;
 605
 606        if (host->data == NULL) {
 607                struct mmc_command *cmd;
 608                struct mmc_host    *mmc;
 609
 610                cmd = host->cmd;
 611                host->cmd = NULL;
 612                mmc_omap_send_abort(host, 10000);
 613
 614                host->mrq = NULL;
 615                mmc = host->mmc;
 616                mmc_omap_release_slot(host->current_slot, 1);
 617                mmc_request_done(mmc, cmd->mrq);
 618        } else
 619                mmc_omap_cmd_done(host, host->cmd);
 620
 621        host->abort = 0;
 622        enable_irq(host->irq);
 623}
 624
 625static void
 626mmc_omap_cmd_timer(struct timer_list *t)
 627{
 628        struct mmc_omap_host *host = from_timer(host, t, cmd_abort_timer);
 629        unsigned long flags;
 630
 631        spin_lock_irqsave(&host->slot_lock, flags);
 632        if (host->cmd != NULL && !host->abort) {
 633                OMAP_MMC_WRITE(host, IE, 0);
 634                disable_irq(host->irq);
 635                host->abort = 1;
 636                queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 637        }
 638        spin_unlock_irqrestore(&host->slot_lock, flags);
 639}
 640
 641/* PIO only */
 642static void
 643mmc_omap_sg_to_buf(struct mmc_omap_host *host)
 644{
 645        struct scatterlist *sg;
 646
 647        sg = host->data->sg + host->sg_idx;
 648        host->buffer_bytes_left = sg->length;
 649        host->buffer = sg_virt(sg);
 650        if (host->buffer_bytes_left > host->total_bytes_left)
 651                host->buffer_bytes_left = host->total_bytes_left;
 652}
 653
 654static void
 655mmc_omap_clk_timer(struct timer_list *t)
 656{
 657        struct mmc_omap_host *host = from_timer(host, t, clk_timer);
 658
 659        mmc_omap_fclk_enable(host, 0);
 660}
 661
 662/* PIO only */
 663static void
 664mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
 665{
 666        int n, nwords;
 667
 668        if (host->buffer_bytes_left == 0) {
 669                host->sg_idx++;
 670                BUG_ON(host->sg_idx == host->sg_len);
 671                mmc_omap_sg_to_buf(host);
 672        }
 673        n = 64;
 674        if (n > host->buffer_bytes_left)
 675                n = host->buffer_bytes_left;
 676
 677        /* Round up to handle odd number of bytes to transfer */
 678        nwords = DIV_ROUND_UP(n, 2);
 679
 680        host->buffer_bytes_left -= n;
 681        host->total_bytes_left -= n;
 682        host->data->bytes_xfered += n;
 683
 684        if (write) {
 685                __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
 686                              host->buffer, nwords);
 687        } else {
 688                __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
 689                             host->buffer, nwords);
 690        }
 691
 692        host->buffer += nwords;
 693}
 694
 695#ifdef CONFIG_MMC_DEBUG
 696static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
 697{
 698        static const char *mmc_omap_status_bits[] = {
 699                "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
 700                "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
 701        };
 702        int i;
 703        char res[64], *buf = res;
 704
 705        buf += sprintf(buf, "MMC IRQ 0x%x:", status);
 706
 707        for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
 708                if (status & (1 << i))
 709                        buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
 710        dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
 711}
 712#else
 713static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
 714{
 715}
 716#endif
 717
 718
 719static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
 720{
 721        struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
 722        u16 status;
 723        int end_command;
 724        int end_transfer;
 725        int transfer_error, cmd_error;
 726
 727        if (host->cmd == NULL && host->data == NULL) {
 728                status = OMAP_MMC_READ(host, STAT);
 729                dev_info(mmc_dev(host->slots[0]->mmc),
 730                         "Spurious IRQ 0x%04x\n", status);
 731                if (status != 0) {
 732                        OMAP_MMC_WRITE(host, STAT, status);
 733                        OMAP_MMC_WRITE(host, IE, 0);
 734                }
 735                return IRQ_HANDLED;
 736        }
 737
 738        end_command = 0;
 739        end_transfer = 0;
 740        transfer_error = 0;
 741        cmd_error = 0;
 742
 743        while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
 744                int cmd;
 745
 746                OMAP_MMC_WRITE(host, STAT, status);
 747                if (host->cmd != NULL)
 748                        cmd = host->cmd->opcode;
 749                else
 750                        cmd = -1;
 751                dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
 752                        status, cmd);
 753                mmc_omap_report_irq(host, status);
 754
 755                if (host->total_bytes_left) {
 756                        if ((status & OMAP_MMC_STAT_A_FULL) ||
 757                            (status & OMAP_MMC_STAT_END_OF_DATA))
 758                                mmc_omap_xfer_data(host, 0);
 759                        if (status & OMAP_MMC_STAT_A_EMPTY)
 760                                mmc_omap_xfer_data(host, 1);
 761                }
 762
 763                if (status & OMAP_MMC_STAT_END_OF_DATA)
 764                        end_transfer = 1;
 765
 766                if (status & OMAP_MMC_STAT_DATA_TOUT) {
 767                        dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
 768                                cmd);
 769                        if (host->data) {
 770                                host->data->error = -ETIMEDOUT;
 771                                transfer_error = 1;
 772                        }
 773                }
 774
 775                if (status & OMAP_MMC_STAT_DATA_CRC) {
 776                        if (host->data) {
 777                                host->data->error = -EILSEQ;
 778                                dev_dbg(mmc_dev(host->mmc),
 779                                         "data CRC error, bytes left %d\n",
 780                                        host->total_bytes_left);
 781                                transfer_error = 1;
 782                        } else {
 783                                dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
 784                        }
 785                }
 786
 787                if (status & OMAP_MMC_STAT_CMD_TOUT) {
 788                        /* Timeouts are routine with some commands */
 789                        if (host->cmd) {
 790                                struct mmc_omap_slot *slot =
 791                                        host->current_slot;
 792                                if (slot == NULL ||
 793                                    !mmc_omap_cover_is_open(slot))
 794                                        dev_err(mmc_dev(host->mmc),
 795                                                "command timeout (CMD%d)\n",
 796                                                cmd);
 797                                host->cmd->error = -ETIMEDOUT;
 798                                end_command = 1;
 799                                cmd_error = 1;
 800                        }
 801                }
 802
 803                if (status & OMAP_MMC_STAT_CMD_CRC) {
 804                        if (host->cmd) {
 805                                dev_err(mmc_dev(host->mmc),
 806                                        "command CRC error (CMD%d, arg 0x%08x)\n",
 807                                        cmd, host->cmd->arg);
 808                                host->cmd->error = -EILSEQ;
 809                                end_command = 1;
 810                                cmd_error = 1;
 811                        } else
 812                                dev_err(mmc_dev(host->mmc),
 813                                        "command CRC error without cmd?\n");
 814                }
 815
 816                if (status & OMAP_MMC_STAT_CARD_ERR) {
 817                        dev_dbg(mmc_dev(host->mmc),
 818                                "ignoring card status error (CMD%d)\n",
 819                                cmd);
 820                        end_command = 1;
 821                }
 822
 823                /*
 824                 * NOTE: On 1610 the END_OF_CMD may come too early when
 825                 * starting a write
 826                 */
 827                if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
 828                    (!(status & OMAP_MMC_STAT_A_EMPTY))) {
 829                        end_command = 1;
 830                }
 831        }
 832
 833        if (cmd_error && host->data) {
 834                del_timer(&host->cmd_abort_timer);
 835                host->abort = 1;
 836                OMAP_MMC_WRITE(host, IE, 0);
 837                disable_irq_nosync(host->irq);
 838                queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
 839                return IRQ_HANDLED;
 840        }
 841
 842        if (end_command && host->cmd)
 843                mmc_omap_cmd_done(host, host->cmd);
 844        if (host->data != NULL) {
 845                if (transfer_error)
 846                        mmc_omap_xfer_done(host, host->data);
 847                else if (end_transfer)
 848                        mmc_omap_end_of_data(host, host->data);
 849        }
 850
 851        return IRQ_HANDLED;
 852}
 853
 854void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
 855{
 856        int cover_open;
 857        struct mmc_omap_host *host = dev_get_drvdata(dev);
 858        struct mmc_omap_slot *slot = host->slots[num];
 859
 860        BUG_ON(num >= host->nr_slots);
 861
 862        /* Other subsystems can call in here before we're initialised. */
 863        if (host->nr_slots == 0 || !host->slots[num])
 864                return;
 865
 866        cover_open = mmc_omap_cover_is_open(slot);
 867        if (cover_open != slot->cover_open) {
 868                slot->cover_open = cover_open;
 869                sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
 870        }
 871
 872        tasklet_hi_schedule(&slot->cover_tasklet);
 873}
 874
 875static void mmc_omap_cover_timer(struct timer_list *t)
 876{
 877        struct mmc_omap_slot *slot = from_timer(slot, t, cover_timer);
 878        tasklet_schedule(&slot->cover_tasklet);
 879}
 880
 881static void mmc_omap_cover_handler(struct tasklet_struct *t)
 882{
 883        struct mmc_omap_slot *slot = from_tasklet(slot, t, cover_tasklet);
 884        int cover_open = mmc_omap_cover_is_open(slot);
 885
 886        mmc_detect_change(slot->mmc, 0);
 887        if (!cover_open)
 888                return;
 889
 890        /*
 891         * If no card is inserted, we postpone polling until
 892         * the cover has been closed.
 893         */
 894        if (slot->mmc->card == NULL)
 895                return;
 896
 897        mod_timer(&slot->cover_timer,
 898                  jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
 899}
 900
 901static void mmc_omap_dma_callback(void *priv)
 902{
 903        struct mmc_omap_host *host = priv;
 904        struct mmc_data *data = host->data;
 905
 906        /* If we got to the end of DMA, assume everything went well */
 907        data->bytes_xfered += data->blocks * data->blksz;
 908
 909        mmc_omap_dma_done(host, data);
 910}
 911
 912static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 913{
 914        u16 reg;
 915
 916        reg = OMAP_MMC_READ(host, SDIO);
 917        reg &= ~(1 << 5);
 918        OMAP_MMC_WRITE(host, SDIO, reg);
 919        /* Set maximum timeout */
 920        OMAP_MMC_WRITE(host, CTO, 0xfd);
 921}
 922
 923static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
 924{
 925        unsigned int timeout, cycle_ns;
 926        u16 reg;
 927
 928        cycle_ns = 1000000000 / host->current_slot->fclk_freq;
 929        timeout = req->data->timeout_ns / cycle_ns;
 930        timeout += req->data->timeout_clks;
 931
 932        /* Check if we need to use timeout multiplier register */
 933        reg = OMAP_MMC_READ(host, SDIO);
 934        if (timeout > 0xffff) {
 935                reg |= (1 << 5);
 936                timeout /= 1024;
 937        } else
 938                reg &= ~(1 << 5);
 939        OMAP_MMC_WRITE(host, SDIO, reg);
 940        OMAP_MMC_WRITE(host, DTO, timeout);
 941}
 942
 943static void
 944mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
 945{
 946        struct mmc_data *data = req->data;
 947        int i, use_dma = 1, block_size;
 948        struct scatterlist *sg;
 949        unsigned sg_len;
 950
 951        host->data = data;
 952        if (data == NULL) {
 953                OMAP_MMC_WRITE(host, BLEN, 0);
 954                OMAP_MMC_WRITE(host, NBLK, 0);
 955                OMAP_MMC_WRITE(host, BUF, 0);
 956                host->dma_in_use = 0;
 957                set_cmd_timeout(host, req);
 958                return;
 959        }
 960
 961        block_size = data->blksz;
 962
 963        OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
 964        OMAP_MMC_WRITE(host, BLEN, block_size - 1);
 965        set_data_timeout(host, req);
 966
 967        /* cope with calling layer confusion; it issues "single
 968         * block" writes using multi-block scatterlists.
 969         */
 970        sg_len = (data->blocks == 1) ? 1 : data->sg_len;
 971
 972        /* Only do DMA for entire blocks */
 973        for_each_sg(data->sg, sg, sg_len, i) {
 974                if ((sg->length % block_size) != 0) {
 975                        use_dma = 0;
 976                        break;
 977                }
 978        }
 979
 980        host->sg_idx = 0;
 981        if (use_dma) {
 982                enum dma_data_direction dma_data_dir;
 983                struct dma_async_tx_descriptor *tx;
 984                struct dma_chan *c;
 985                u32 burst, *bp;
 986                u16 buf;
 987
 988                /*
 989                 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
 990                 * and 24xx. Use 16 or 32 word frames when the
 991                 * blocksize is at least that large. Blocksize is
 992                 * usually 512 bytes; but not for some SD reads.
 993                 */
 994                burst = mmc_omap15xx() ? 32 : 64;
 995                if (burst > data->blksz)
 996                        burst = data->blksz;
 997
 998                burst >>= 1;
 999
1000                if (data->flags & MMC_DATA_WRITE) {
1001                        c = host->dma_tx;
1002                        bp = &host->dma_tx_burst;
1003                        buf = 0x0f80 | (burst - 1) << 0;
1004                        dma_data_dir = DMA_TO_DEVICE;
1005                } else {
1006                        c = host->dma_rx;
1007                        bp = &host->dma_rx_burst;
1008                        buf = 0x800f | (burst - 1) << 8;
1009                        dma_data_dir = DMA_FROM_DEVICE;
1010                }
1011
1012                if (!c)
1013                        goto use_pio;
1014
1015                /* Only reconfigure if we have a different burst size */
1016                if (*bp != burst) {
1017                        struct dma_slave_config cfg = {
1018                                .src_addr = host->phys_base +
1019                                            OMAP_MMC_REG(host, DATA),
1020                                .dst_addr = host->phys_base +
1021                                            OMAP_MMC_REG(host, DATA),
1022                                .src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1023                                .dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES,
1024                                .src_maxburst = burst,
1025                                .dst_maxburst = burst,
1026                        };
1027
1028                        if (dmaengine_slave_config(c, &cfg))
1029                                goto use_pio;
1030
1031                        *bp = burst;
1032                }
1033
1034                host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035                                          dma_data_dir);
1036                if (host->sg_len == 0)
1037                        goto use_pio;
1038
1039                tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040                        data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042                if (!tx)
1043                        goto use_pio;
1044
1045                OMAP_MMC_WRITE(host, BUF, buf);
1046
1047                tx->callback = mmc_omap_dma_callback;
1048                tx->callback_param = host;
1049                dmaengine_submit(tx);
1050                host->brs_received = 0;
1051                host->dma_done = 0;
1052                host->dma_in_use = 1;
1053                return;
1054        }
1055 use_pio:
1056
1057        /* Revert to PIO? */
1058        OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059        host->total_bytes_left = data->blocks * block_size;
1060        host->sg_len = sg_len;
1061        mmc_omap_sg_to_buf(host);
1062        host->dma_in_use = 0;
1063}
1064
1065static void mmc_omap_start_request(struct mmc_omap_host *host,
1066                                   struct mmc_request *req)
1067{
1068        BUG_ON(host->mrq != NULL);
1069
1070        host->mrq = req;
1071
1072        /* only touch fifo AFTER the controller readies it */
1073        mmc_omap_prepare_data(host, req);
1074        mmc_omap_start_command(host, req->cmd);
1075        if (host->dma_in_use) {
1076                struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077                                host->dma_tx : host->dma_rx;
1078
1079                dma_async_issue_pending(c);
1080        }
1081}
1082
1083static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084{
1085        struct mmc_omap_slot *slot = mmc_priv(mmc);
1086        struct mmc_omap_host *host = slot->host;
1087        unsigned long flags;
1088
1089        spin_lock_irqsave(&host->slot_lock, flags);
1090        if (host->mmc != NULL) {
1091                BUG_ON(slot->mrq != NULL);
1092                slot->mrq = req;
1093                spin_unlock_irqrestore(&host->slot_lock, flags);
1094                return;
1095        } else
1096                host->mmc = mmc;
1097        spin_unlock_irqrestore(&host->slot_lock, flags);
1098        mmc_omap_select_slot(slot, 1);
1099        mmc_omap_start_request(host, req);
1100}
1101
1102static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103                                int vdd)
1104{
1105        struct mmc_omap_host *host;
1106
1107        host = slot->host;
1108
1109        if (slot->pdata->set_power != NULL)
1110                slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111                                        vdd);
1112        if (mmc_omap2()) {
1113                u16 w;
1114
1115                if (power_on) {
1116                        w = OMAP_MMC_READ(host, CON);
1117                        OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118                } else {
1119                        w = OMAP_MMC_READ(host, CON);
1120                        OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121                }
1122        }
1123}
1124
1125static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1126{
1127        struct mmc_omap_slot *slot = mmc_priv(mmc);
1128        struct mmc_omap_host *host = slot->host;
1129        int func_clk_rate = clk_get_rate(host->fclk);
1130        int dsor;
1131
1132        if (ios->clock == 0)
1133                return 0;
1134
1135        dsor = func_clk_rate / ios->clock;
1136        if (dsor < 1)
1137                dsor = 1;
1138
1139        if (func_clk_rate / dsor > ios->clock)
1140                dsor++;
1141
1142        if (dsor > 250)
1143                dsor = 250;
1144
1145        slot->fclk_freq = func_clk_rate / dsor;
1146
1147        if (ios->bus_width == MMC_BUS_WIDTH_4)
1148                dsor |= 1 << 15;
1149
1150        return dsor;
1151}
1152
1153static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154{
1155        struct mmc_omap_slot *slot = mmc_priv(mmc);
1156        struct mmc_omap_host *host = slot->host;
1157        int i, dsor;
1158        int clk_enabled, init_stream;
1159
1160        mmc_omap_select_slot(slot, 0);
1161
1162        dsor = mmc_omap_calc_divisor(mmc, ios);
1163
1164        if (ios->vdd != slot->vdd)
1165                slot->vdd = ios->vdd;
1166
1167        clk_enabled = 0;
1168        init_stream = 0;
1169        switch (ios->power_mode) {
1170        case MMC_POWER_OFF:
1171                mmc_omap_set_power(slot, 0, ios->vdd);
1172                break;
1173        case MMC_POWER_UP:
1174                /* Cannot touch dsor yet, just power up MMC */
1175                mmc_omap_set_power(slot, 1, ios->vdd);
1176                slot->power_mode = ios->power_mode;
1177                goto exit;
1178        case MMC_POWER_ON:
1179                mmc_omap_fclk_enable(host, 1);
1180                clk_enabled = 1;
1181                dsor |= 1 << 11;
1182                if (slot->power_mode != MMC_POWER_ON)
1183                        init_stream = 1;
1184                break;
1185        }
1186        slot->power_mode = ios->power_mode;
1187
1188        if (slot->bus_mode != ios->bus_mode) {
1189                if (slot->pdata->set_bus_mode != NULL)
1190                        slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1191                                                  ios->bus_mode);
1192                slot->bus_mode = ios->bus_mode;
1193        }
1194
1195        /* On insanely high arm_per frequencies something sometimes
1196         * goes somehow out of sync, and the POW bit is not being set,
1197         * which results in the while loop below getting stuck.
1198         * Writing to the CON register twice seems to do the trick. */
1199        for (i = 0; i < 2; i++)
1200                OMAP_MMC_WRITE(host, CON, dsor);
1201        slot->saved_con = dsor;
1202        if (init_stream) {
1203                /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1204                int usecs = 250;
1205
1206                /* Send clock cycles, poll completion */
1207                OMAP_MMC_WRITE(host, IE, 0);
1208                OMAP_MMC_WRITE(host, STAT, 0xffff);
1209                OMAP_MMC_WRITE(host, CMD, 1 << 7);
1210                while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1211                        udelay(1);
1212                        usecs--;
1213                }
1214                OMAP_MMC_WRITE(host, STAT, 1);
1215        }
1216
1217exit:
1218        mmc_omap_release_slot(slot, clk_enabled);
1219}
1220
1221static const struct mmc_host_ops mmc_omap_ops = {
1222        .request        = mmc_omap_request,
1223        .set_ios        = mmc_omap_set_ios,
1224};
1225
1226static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1227{
1228        struct mmc_omap_slot *slot = NULL;
1229        struct mmc_host *mmc;
1230        int r;
1231
1232        mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1233        if (mmc == NULL)
1234                return -ENOMEM;
1235
1236        slot = mmc_priv(mmc);
1237        slot->host = host;
1238        slot->mmc = mmc;
1239        slot->id = id;
1240        slot->power_mode = MMC_POWER_UNDEFINED;
1241        slot->pdata = &host->pdata->slots[id];
1242
1243        host->slots[id] = slot;
1244
1245        mmc->caps = 0;
1246        if (host->pdata->slots[id].wires >= 4)
1247                mmc->caps |= MMC_CAP_4_BIT_DATA;
1248
1249        mmc->ops = &mmc_omap_ops;
1250        mmc->f_min = 400000;
1251
1252        if (mmc_omap2())
1253                mmc->f_max = 48000000;
1254        else
1255                mmc->f_max = 24000000;
1256        if (host->pdata->max_freq)
1257                mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1258        mmc->ocr_avail = slot->pdata->ocr_mask;
1259
1260        /* Use scatterlist DMA to reduce per-transfer costs.
1261         * NOTE max_seg_size assumption that small blocks aren't
1262         * normally used (except e.g. for reading SD registers).
1263         */
1264        mmc->max_segs = 32;
1265        mmc->max_blk_size = 2048;       /* BLEN is 11 bits (+1) */
1266        mmc->max_blk_count = 2048;      /* NBLK is 11 bits (+1) */
1267        mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1268        mmc->max_seg_size = mmc->max_req_size;
1269
1270        if (slot->pdata->get_cover_state != NULL) {
1271                timer_setup(&slot->cover_timer, mmc_omap_cover_timer, 0);
1272                tasklet_setup(&slot->cover_tasklet, mmc_omap_cover_handler);
1273        }
1274
1275        r = mmc_add_host(mmc);
1276        if (r < 0)
1277                goto err_remove_host;
1278
1279        if (slot->pdata->name != NULL) {
1280                r = device_create_file(&mmc->class_dev,
1281                                        &dev_attr_slot_name);
1282                if (r < 0)
1283                        goto err_remove_host;
1284        }
1285
1286        if (slot->pdata->get_cover_state != NULL) {
1287                r = device_create_file(&mmc->class_dev,
1288                                        &dev_attr_cover_switch);
1289                if (r < 0)
1290                        goto err_remove_slot_name;
1291                tasklet_schedule(&slot->cover_tasklet);
1292        }
1293
1294        return 0;
1295
1296err_remove_slot_name:
1297        if (slot->pdata->name != NULL)
1298                device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1299err_remove_host:
1300        mmc_remove_host(mmc);
1301        mmc_free_host(mmc);
1302        return r;
1303}
1304
1305static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1306{
1307        struct mmc_host *mmc = slot->mmc;
1308
1309        if (slot->pdata->name != NULL)
1310                device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1311        if (slot->pdata->get_cover_state != NULL)
1312                device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1313
1314        tasklet_kill(&slot->cover_tasklet);
1315        del_timer_sync(&slot->cover_timer);
1316        flush_workqueue(slot->host->mmc_omap_wq);
1317
1318        mmc_remove_host(mmc);
1319        mmc_free_host(mmc);
1320}
1321
1322static int mmc_omap_probe(struct platform_device *pdev)
1323{
1324        struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1325        struct mmc_omap_host *host = NULL;
1326        struct resource *res;
1327        int i, ret = 0;
1328        int irq;
1329
1330        if (pdata == NULL) {
1331                dev_err(&pdev->dev, "platform data missing\n");
1332                return -ENXIO;
1333        }
1334        if (pdata->nr_slots == 0) {
1335                dev_err(&pdev->dev, "no slots\n");
1336                return -EPROBE_DEFER;
1337        }
1338
1339        host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host),
1340                            GFP_KERNEL);
1341        if (host == NULL)
1342                return -ENOMEM;
1343
1344        irq = platform_get_irq(pdev, 0);
1345        if (irq < 0)
1346                return -ENXIO;
1347
1348        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1349        host->virt_base = devm_ioremap_resource(&pdev->dev, res);
1350        if (IS_ERR(host->virt_base))
1351                return PTR_ERR(host->virt_base);
1352
1353        INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1354        INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1355
1356        INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1357        timer_setup(&host->cmd_abort_timer, mmc_omap_cmd_timer, 0);
1358
1359        spin_lock_init(&host->clk_lock);
1360        timer_setup(&host->clk_timer, mmc_omap_clk_timer, 0);
1361
1362        spin_lock_init(&host->dma_lock);
1363        spin_lock_init(&host->slot_lock);
1364        init_waitqueue_head(&host->slot_wq);
1365
1366        host->pdata = pdata;
1367        host->features = host->pdata->slots[0].features;
1368        host->dev = &pdev->dev;
1369        platform_set_drvdata(pdev, host);
1370
1371        host->id = pdev->id;
1372        host->irq = irq;
1373        host->phys_base = res->start;
1374        host->iclk = clk_get(&pdev->dev, "ick");
1375        if (IS_ERR(host->iclk))
1376                return PTR_ERR(host->iclk);
1377        clk_enable(host->iclk);
1378
1379        host->fclk = clk_get(&pdev->dev, "fck");
1380        if (IS_ERR(host->fclk)) {
1381                ret = PTR_ERR(host->fclk);
1382                goto err_free_iclk;
1383        }
1384
1385        host->dma_tx_burst = -1;
1386        host->dma_rx_burst = -1;
1387
1388        host->dma_tx = dma_request_chan(&pdev->dev, "tx");
1389        if (IS_ERR(host->dma_tx)) {
1390                ret = PTR_ERR(host->dma_tx);
1391                if (ret == -EPROBE_DEFER) {
1392                        clk_put(host->fclk);
1393                        goto err_free_iclk;
1394                }
1395
1396                host->dma_tx = NULL;
1397                dev_warn(host->dev, "TX DMA channel request failed\n");
1398        }
1399
1400        host->dma_rx = dma_request_chan(&pdev->dev, "rx");
1401        if (IS_ERR(host->dma_rx)) {
1402                ret = PTR_ERR(host->dma_rx);
1403                if (ret == -EPROBE_DEFER) {
1404                        if (host->dma_tx)
1405                                dma_release_channel(host->dma_tx);
1406                        clk_put(host->fclk);
1407                        goto err_free_iclk;
1408                }
1409
1410                host->dma_rx = NULL;
1411                dev_warn(host->dev, "RX DMA channel request failed\n");
1412        }
1413
1414        ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1415        if (ret)
1416                goto err_free_dma;
1417
1418        if (pdata->init != NULL) {
1419                ret = pdata->init(&pdev->dev);
1420                if (ret < 0)
1421                        goto err_free_irq;
1422        }
1423
1424        host->nr_slots = pdata->nr_slots;
1425        host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1426
1427        host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1428        if (!host->mmc_omap_wq) {
1429                ret = -ENOMEM;
1430                goto err_plat_cleanup;
1431        }
1432
1433        for (i = 0; i < pdata->nr_slots; i++) {
1434                ret = mmc_omap_new_slot(host, i);
1435                if (ret < 0) {
1436                        while (--i >= 0)
1437                                mmc_omap_remove_slot(host->slots[i]);
1438
1439                        goto err_destroy_wq;
1440                }
1441        }
1442
1443        return 0;
1444
1445err_destroy_wq:
1446        destroy_workqueue(host->mmc_omap_wq);
1447err_plat_cleanup:
1448        if (pdata->cleanup)
1449                pdata->cleanup(&pdev->dev);
1450err_free_irq:
1451        free_irq(host->irq, host);
1452err_free_dma:
1453        if (host->dma_tx)
1454                dma_release_channel(host->dma_tx);
1455        if (host->dma_rx)
1456                dma_release_channel(host->dma_rx);
1457        clk_put(host->fclk);
1458err_free_iclk:
1459        clk_disable(host->iclk);
1460        clk_put(host->iclk);
1461        return ret;
1462}
1463
1464static int mmc_omap_remove(struct platform_device *pdev)
1465{
1466        struct mmc_omap_host *host = platform_get_drvdata(pdev);
1467        int i;
1468
1469        BUG_ON(host == NULL);
1470
1471        for (i = 0; i < host->nr_slots; i++)
1472                mmc_omap_remove_slot(host->slots[i]);
1473
1474        if (host->pdata->cleanup)
1475                host->pdata->cleanup(&pdev->dev);
1476
1477        mmc_omap_fclk_enable(host, 0);
1478        free_irq(host->irq, host);
1479        clk_put(host->fclk);
1480        clk_disable(host->iclk);
1481        clk_put(host->iclk);
1482
1483        if (host->dma_tx)
1484                dma_release_channel(host->dma_tx);
1485        if (host->dma_rx)
1486                dma_release_channel(host->dma_rx);
1487
1488        destroy_workqueue(host->mmc_omap_wq);
1489
1490        return 0;
1491}
1492
1493#if IS_BUILTIN(CONFIG_OF)
1494static const struct of_device_id mmc_omap_match[] = {
1495        { .compatible = "ti,omap2420-mmc", },
1496        { },
1497};
1498MODULE_DEVICE_TABLE(of, mmc_omap_match);
1499#endif
1500
1501static struct platform_driver mmc_omap_driver = {
1502        .probe          = mmc_omap_probe,
1503        .remove         = mmc_omap_remove,
1504        .driver         = {
1505                .name   = DRIVER_NAME,
1506                .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1507                .of_match_table = of_match_ptr(mmc_omap_match),
1508        },
1509};
1510
1511module_platform_driver(mmc_omap_driver);
1512MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1513MODULE_LICENSE("GPL");
1514MODULE_ALIAS("platform:" DRIVER_NAME);
1515MODULE_AUTHOR("Juha Yrjl");
1516