linux/drivers/mmc/host/dw_mmc-rockchip.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
   4 */
   5
   6#include <linux/module.h>
   7#include <linux/platform_device.h>
   8#include <linux/clk.h>
   9#include <linux/mmc/host.h>
  10#include <linux/of_address.h>
  11#include <linux/mmc/slot-gpio.h>
  12#include <linux/pm_runtime.h>
  13#include <linux/slab.h>
  14
  15#include "dw_mmc.h"
  16#include "dw_mmc-pltfm.h"
  17
  18#define RK3288_CLKGEN_DIV       2
  19
  20struct dw_mci_rockchip_priv_data {
  21        struct clk              *drv_clk;
  22        struct clk              *sample_clk;
  23        int                     default_sample_phase;
  24        int                     num_phases;
  25};
  26
  27static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
  28{
  29        struct dw_mci_rockchip_priv_data *priv = host->priv;
  30        int ret;
  31        unsigned int cclkin;
  32        u32 bus_hz;
  33
  34        if (ios->clock == 0)
  35                return;
  36
  37        /*
  38         * cclkin: source clock of mmc controller
  39         * bus_hz: card interface clock generated by CLKGEN
  40         * bus_hz = cclkin / RK3288_CLKGEN_DIV
  41         * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
  42         *
  43         * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
  44         * DDR52 8-bit mode.
  45         */
  46        if (ios->bus_width == MMC_BUS_WIDTH_8 &&
  47            ios->timing == MMC_TIMING_MMC_DDR52)
  48                cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
  49        else
  50                cclkin = ios->clock * RK3288_CLKGEN_DIV;
  51
  52        ret = clk_set_rate(host->ciu_clk, cclkin);
  53        if (ret)
  54                dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
  55
  56        bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
  57        if (bus_hz != host->bus_hz) {
  58                host->bus_hz = bus_hz;
  59                /* force dw_mci_setup_bus() */
  60                host->current_speed = 0;
  61        }
  62
  63        /* Make sure we use phases which we can enumerate with */
  64        if (!IS_ERR(priv->sample_clk) && ios->timing <= MMC_TIMING_SD_HS)
  65                clk_set_phase(priv->sample_clk, priv->default_sample_phase);
  66
  67        /*
  68         * Set the drive phase offset based on speed mode to achieve hold times.
  69         *
  70         * NOTE: this is _not_ a value that is dynamically tuned and is also
  71         * _not_ a value that will vary from board to board.  It is a value
  72         * that could vary between different SoC models if they had massively
  73         * different output clock delays inside their dw_mmc IP block (delay_o),
  74         * but since it's OK to overshoot a little we don't need to do complex
  75         * calculations and can pick values that will just work for everyone.
  76         *
  77         * When picking values we'll stick with picking 0/90/180/270 since
  78         * those can be made very accurately on all known Rockchip SoCs.
  79         *
  80         * Note that these values match values from the DesignWare Databook
  81         * tables for the most part except for SDR12 and "ID mode".  For those
  82         * two modes the databook calculations assume a clock in of 50MHz.  As
  83         * seen above, we always use a clock in rate that is exactly the
  84         * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
  85         * back out before the controller sees it).
  86         *
  87         * From measurement of a single device, it appears that delay_o is
  88         * about .5 ns.  Since we try to leave a bit of margin, it's expected
  89         * that numbers here will be fine even with much larger delay_o
  90         * (the 1.4 ns assumed by the DesignWare Databook would result in the
  91         * same results, for instance).
  92         */
  93        if (!IS_ERR(priv->drv_clk)) {
  94                int phase;
  95
  96                /*
  97                 * In almost all cases a 90 degree phase offset will provide
  98                 * sufficient hold times across all valid input clock rates
  99                 * assuming delay_o is not absurd for a given SoC.  We'll use
 100                 * that as a default.
 101                 */
 102                phase = 90;
 103
 104                switch (ios->timing) {
 105                case MMC_TIMING_MMC_DDR52:
 106                        /*
 107                         * Since clock in rate with MMC_DDR52 is doubled when
 108                         * bus width is 8 we need to double the phase offset
 109                         * to get the same timings.
 110                         */
 111                        if (ios->bus_width == MMC_BUS_WIDTH_8)
 112                                phase = 180;
 113                        break;
 114                case MMC_TIMING_UHS_SDR104:
 115                case MMC_TIMING_MMC_HS200:
 116                        /*
 117                         * In the case of 150 MHz clock (typical max for
 118                         * Rockchip SoCs), 90 degree offset will add a delay
 119                         * of 1.67 ns.  That will meet min hold time of .8 ns
 120                         * as long as clock output delay is < .87 ns.  On
 121                         * SoCs measured this seems to be OK, but it doesn't
 122                         * hurt to give margin here, so we use 180.
 123                         */
 124                        phase = 180;
 125                        break;
 126                }
 127
 128                clk_set_phase(priv->drv_clk, phase);
 129        }
 130}
 131
 132#define TUNING_ITERATION_TO_PHASE(i, num_phases) \
 133                (DIV_ROUND_UP((i) * 360, num_phases))
 134
 135static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
 136{
 137        struct dw_mci *host = slot->host;
 138        struct dw_mci_rockchip_priv_data *priv = host->priv;
 139        struct mmc_host *mmc = slot->mmc;
 140        int ret = 0;
 141        int i;
 142        bool v, prev_v = 0, first_v;
 143        struct range_t {
 144                int start;
 145                int end; /* inclusive */
 146        };
 147        struct range_t *ranges;
 148        unsigned int range_count = 0;
 149        int longest_range_len = -1;
 150        int longest_range = -1;
 151        int middle_phase;
 152
 153        if (IS_ERR(priv->sample_clk)) {
 154                dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
 155                return -EIO;
 156        }
 157
 158        ranges = kmalloc_array(priv->num_phases / 2 + 1,
 159                               sizeof(*ranges), GFP_KERNEL);
 160        if (!ranges)
 161                return -ENOMEM;
 162
 163        /* Try each phase and extract good ranges */
 164        for (i = 0; i < priv->num_phases; ) {
 165                clk_set_phase(priv->sample_clk,
 166                              TUNING_ITERATION_TO_PHASE(i, priv->num_phases));
 167
 168                v = !mmc_send_tuning(mmc, opcode, NULL);
 169
 170                if (i == 0)
 171                        first_v = v;
 172
 173                if ((!prev_v) && v) {
 174                        range_count++;
 175                        ranges[range_count-1].start = i;
 176                }
 177                if (v) {
 178                        ranges[range_count-1].end = i;
 179                        i++;
 180                } else if (i == priv->num_phases - 1) {
 181                        /* No extra skipping rules if we're at the end */
 182                        i++;
 183                } else {
 184                        /*
 185                         * No need to check too close to an invalid
 186                         * one since testing bad phases is slow.  Skip
 187                         * 20 degrees.
 188                         */
 189                        i += DIV_ROUND_UP(20 * priv->num_phases, 360);
 190
 191                        /* Always test the last one */
 192                        if (i >= priv->num_phases)
 193                                i = priv->num_phases - 1;
 194                }
 195
 196                prev_v = v;
 197        }
 198
 199        if (range_count == 0) {
 200                dev_warn(host->dev, "All phases bad!");
 201                ret = -EIO;
 202                goto free;
 203        }
 204
 205        /* wrap around case, merge the end points */
 206        if ((range_count > 1) && first_v && v) {
 207                ranges[0].start = ranges[range_count-1].start;
 208                range_count--;
 209        }
 210
 211        if (ranges[0].start == 0 && ranges[0].end == priv->num_phases - 1) {
 212                clk_set_phase(priv->sample_clk, priv->default_sample_phase);
 213                dev_info(host->dev, "All phases work, using default phase %d.",
 214                         priv->default_sample_phase);
 215                goto free;
 216        }
 217
 218        /* Find the longest range */
 219        for (i = 0; i < range_count; i++) {
 220                int len = (ranges[i].end - ranges[i].start + 1);
 221
 222                if (len < 0)
 223                        len += priv->num_phases;
 224
 225                if (longest_range_len < len) {
 226                        longest_range_len = len;
 227                        longest_range = i;
 228                }
 229
 230                dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
 231                        TUNING_ITERATION_TO_PHASE(ranges[i].start,
 232                                                  priv->num_phases),
 233                        TUNING_ITERATION_TO_PHASE(ranges[i].end,
 234                                                  priv->num_phases),
 235                        len
 236                );
 237        }
 238
 239        dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
 240                TUNING_ITERATION_TO_PHASE(ranges[longest_range].start,
 241                                          priv->num_phases),
 242                TUNING_ITERATION_TO_PHASE(ranges[longest_range].end,
 243                                          priv->num_phases),
 244                longest_range_len
 245        );
 246
 247        middle_phase = ranges[longest_range].start + longest_range_len / 2;
 248        middle_phase %= priv->num_phases;
 249        dev_info(host->dev, "Successfully tuned phase to %d\n",
 250                 TUNING_ITERATION_TO_PHASE(middle_phase, priv->num_phases));
 251
 252        clk_set_phase(priv->sample_clk,
 253                      TUNING_ITERATION_TO_PHASE(middle_phase,
 254                                                priv->num_phases));
 255
 256free:
 257        kfree(ranges);
 258        return ret;
 259}
 260
 261static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
 262{
 263        struct device_node *np = host->dev->of_node;
 264        struct dw_mci_rockchip_priv_data *priv;
 265
 266        priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
 267        if (!priv)
 268                return -ENOMEM;
 269
 270        if (of_property_read_u32(np, "rockchip,desired-num-phases",
 271                                        &priv->num_phases))
 272                priv->num_phases = 360;
 273
 274        if (of_property_read_u32(np, "rockchip,default-sample-phase",
 275                                        &priv->default_sample_phase))
 276                priv->default_sample_phase = 0;
 277
 278        priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
 279        if (IS_ERR(priv->drv_clk))
 280                dev_dbg(host->dev, "ciu-drive not available\n");
 281
 282        priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
 283        if (IS_ERR(priv->sample_clk))
 284                dev_dbg(host->dev, "ciu-sample not available\n");
 285
 286        host->priv = priv;
 287
 288        return 0;
 289}
 290
 291static int dw_mci_rockchip_init(struct dw_mci *host)
 292{
 293        /* It is slot 8 on Rockchip SoCs */
 294        host->sdio_id0 = 8;
 295
 296        if (of_device_is_compatible(host->dev->of_node,
 297                                    "rockchip,rk3288-dw-mshc"))
 298                host->bus_hz /= RK3288_CLKGEN_DIV;
 299
 300        return 0;
 301}
 302
 303/* Common capabilities of RK3288 SoC */
 304static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
 305        MMC_CAP_CMD23,
 306        MMC_CAP_CMD23,
 307        MMC_CAP_CMD23,
 308        MMC_CAP_CMD23,
 309};
 310
 311static const struct dw_mci_drv_data rk2928_drv_data = {
 312        .init                   = dw_mci_rockchip_init,
 313};
 314
 315static const struct dw_mci_drv_data rk3288_drv_data = {
 316        .caps                   = dw_mci_rk3288_dwmmc_caps,
 317        .num_caps               = ARRAY_SIZE(dw_mci_rk3288_dwmmc_caps),
 318        .set_ios                = dw_mci_rk3288_set_ios,
 319        .execute_tuning         = dw_mci_rk3288_execute_tuning,
 320        .parse_dt               = dw_mci_rk3288_parse_dt,
 321        .init                   = dw_mci_rockchip_init,
 322};
 323
 324static const struct of_device_id dw_mci_rockchip_match[] = {
 325        { .compatible = "rockchip,rk2928-dw-mshc",
 326                .data = &rk2928_drv_data },
 327        { .compatible = "rockchip,rk3288-dw-mshc",
 328                .data = &rk3288_drv_data },
 329        {},
 330};
 331MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
 332
 333static int dw_mci_rockchip_probe(struct platform_device *pdev)
 334{
 335        const struct dw_mci_drv_data *drv_data;
 336        const struct of_device_id *match;
 337        int ret;
 338
 339        if (!pdev->dev.of_node)
 340                return -ENODEV;
 341
 342        match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
 343        drv_data = match->data;
 344
 345        pm_runtime_get_noresume(&pdev->dev);
 346        pm_runtime_set_active(&pdev->dev);
 347        pm_runtime_enable(&pdev->dev);
 348        pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
 349        pm_runtime_use_autosuspend(&pdev->dev);
 350
 351        ret = dw_mci_pltfm_register(pdev, drv_data);
 352        if (ret) {
 353                pm_runtime_disable(&pdev->dev);
 354                pm_runtime_set_suspended(&pdev->dev);
 355                pm_runtime_put_noidle(&pdev->dev);
 356                return ret;
 357        }
 358
 359        pm_runtime_put_autosuspend(&pdev->dev);
 360
 361        return 0;
 362}
 363
 364static int dw_mci_rockchip_remove(struct platform_device *pdev)
 365{
 366        pm_runtime_get_sync(&pdev->dev);
 367        pm_runtime_disable(&pdev->dev);
 368        pm_runtime_put_noidle(&pdev->dev);
 369
 370        return dw_mci_pltfm_remove(pdev);
 371}
 372
 373static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
 374        SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 375                                pm_runtime_force_resume)
 376        SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
 377                           dw_mci_runtime_resume,
 378                           NULL)
 379};
 380
 381static struct platform_driver dw_mci_rockchip_pltfm_driver = {
 382        .probe          = dw_mci_rockchip_probe,
 383        .remove         = dw_mci_rockchip_remove,
 384        .driver         = {
 385                .name           = "dwmmc_rockchip",
 386                .probe_type     = PROBE_PREFER_ASYNCHRONOUS,
 387                .of_match_table = dw_mci_rockchip_match,
 388                .pm             = &dw_mci_rockchip_dev_pm_ops,
 389        },
 390};
 391
 392module_platform_driver(dw_mci_rockchip_pltfm_driver);
 393
 394MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
 395MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
 396MODULE_ALIAS("platform:dwmmc_rockchip");
 397MODULE_LICENSE("GPL v2");
 398