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10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/gpio/consumer.h>
13#include <linux/interrupt.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/platform_device.h>
19#include <linux/v4l2-subdev.h>
20#include <media/media-entity.h>
21#include <media/v4l2-common.h>
22#include <media/v4l2-ctrls.h>
23#include <media/v4l2-fwnode.h>
24#include <media/v4l2-subdev.h>
25#include "xilinx-vip.h"
26
27
28#define XCSI_CCR_OFFSET 0x00
29#define XCSI_CCR_SOFTRESET BIT(1)
30#define XCSI_CCR_ENABLE BIT(0)
31
32#define XCSI_PCR_OFFSET 0x04
33#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
34#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
35
36#define XCSI_CSR_OFFSET 0x10
37#define XCSI_CSR_PKTCNT GENMASK(31, 16)
38#define XCSI_CSR_SPFIFOFULL BIT(3)
39#define XCSI_CSR_SPFIFONE BIT(2)
40#define XCSI_CSR_SLBF BIT(1)
41#define XCSI_CSR_RIPCD BIT(0)
42
43#define XCSI_GIER_OFFSET 0x20
44#define XCSI_GIER_GIE BIT(0)
45
46#define XCSI_ISR_OFFSET 0x24
47#define XCSI_IER_OFFSET 0x28
48
49#define XCSI_ISR_FR BIT(31)
50#define XCSI_ISR_VCXFE BIT(30)
51#define XCSI_ISR_WCC BIT(22)
52#define XCSI_ISR_ILC BIT(21)
53#define XCSI_ISR_SPFIFOF BIT(20)
54#define XCSI_ISR_SPFIFONE BIT(19)
55#define XCSI_ISR_SLBF BIT(18)
56#define XCSI_ISR_STOP BIT(17)
57#define XCSI_ISR_SOTERR BIT(13)
58#define XCSI_ISR_SOTSYNCERR BIT(12)
59#define XCSI_ISR_ECC2BERR BIT(11)
60#define XCSI_ISR_ECC1BERR BIT(10)
61#define XCSI_ISR_CRCERR BIT(9)
62#define XCSI_ISR_DATAIDERR BIT(8)
63#define XCSI_ISR_VC3FSYNCERR BIT(7)
64#define XCSI_ISR_VC3FLVLERR BIT(6)
65#define XCSI_ISR_VC2FSYNCERR BIT(5)
66#define XCSI_ISR_VC2FLVLERR BIT(4)
67#define XCSI_ISR_VC1FSYNCERR BIT(3)
68#define XCSI_ISR_VC1FLVLERR BIT(2)
69#define XCSI_ISR_VC0FSYNCERR BIT(1)
70#define XCSI_ISR_VC0FLVLERR BIT(0)
71
72#define XCSI_ISR_ALLINTR_MASK (0xc07e3fff)
73
74
75
76
77
78#define XCSI_IER_INTR_MASK (XCSI_ISR_ALLINTR_MASK &\
79 ~(XCSI_ISR_STOP | XCSI_ISR_VCXFE))
80
81#define XCSI_SPKTR_OFFSET 0x30
82#define XCSI_SPKTR_DATA GENMASK(23, 8)
83#define XCSI_SPKTR_VC GENMASK(7, 6)
84#define XCSI_SPKTR_DT GENMASK(5, 0)
85#define XCSI_SPKT_FIFO_DEPTH 31
86
87#define XCSI_VCXR_OFFSET 0x34
88#define XCSI_VCXR_VCERR GENMASK(23, 0)
89#define XCSI_VCXR_FSYNCERR BIT(1)
90#define XCSI_VCXR_FLVLERR BIT(0)
91
92#define XCSI_CLKINFR_OFFSET 0x3C
93#define XCSI_CLKINFR_STOP BIT(1)
94
95#define XCSI_DLXINFR_OFFSET 0x40
96#define XCSI_DLXINFR_STOP BIT(5)
97#define XCSI_DLXINFR_SOTERR BIT(1)
98#define XCSI_DLXINFR_SOTSYNCERR BIT(0)
99#define XCSI_MAXDL_COUNT 0x4
100
101#define XCSI_VCXINF1R_OFFSET 0x60
102#define XCSI_VCXINF1R_LINECOUNT GENMASK(31, 16)
103#define XCSI_VCXINF1R_LINECOUNT_SHIFT 16
104#define XCSI_VCXINF1R_BYTECOUNT GENMASK(15, 0)
105
106#define XCSI_VCXINF2R_OFFSET 0x64
107#define XCSI_VCXINF2R_DT GENMASK(5, 0)
108#define XCSI_MAXVCX_COUNT 16
109
110
111
112
113
114#define XCSI_MEDIA_PADS 2
115#define XCSI_DEFAULT_WIDTH 1920
116#define XCSI_DEFAULT_HEIGHT 1080
117
118
119#define XCSI_DT_YUV4228B 0x1e
120#define XCSI_DT_YUV42210B 0x1f
121#define XCSI_DT_RGB444 0x20
122#define XCSI_DT_RGB555 0x21
123#define XCSI_DT_RGB565 0x22
124#define XCSI_DT_RGB666 0x23
125#define XCSI_DT_RGB888 0x24
126#define XCSI_DT_RAW6 0x28
127#define XCSI_DT_RAW7 0x29
128#define XCSI_DT_RAW8 0x2a
129#define XCSI_DT_RAW10 0x2b
130#define XCSI_DT_RAW12 0x2c
131#define XCSI_DT_RAW14 0x2d
132#define XCSI_DT_RAW16 0x2e
133#define XCSI_DT_RAW20 0x2f
134
135#define XCSI_VCX_START 4
136#define XCSI_MAX_VC 4
137#define XCSI_MAX_VCX 16
138
139#define XCSI_NEXTREG_OFFSET 4
140
141
142#define XCSI_VCX_NUM_EVENTS ((XCSI_MAX_VCX - XCSI_MAX_VC) * 2)
143
144
145
146
147
148
149struct xcsi2rxss_event {
150 u32 mask;
151 const char *name;
152};
153
154static const struct xcsi2rxss_event xcsi2rxss_events[] = {
155 { XCSI_ISR_FR, "Frame Received" },
156 { XCSI_ISR_VCXFE, "VCX Frame Errors" },
157 { XCSI_ISR_WCC, "Word Count Errors" },
158 { XCSI_ISR_ILC, "Invalid Lane Count Error" },
159 { XCSI_ISR_SPFIFOF, "Short Packet FIFO OverFlow Error" },
160 { XCSI_ISR_SPFIFONE, "Short Packet FIFO Not Empty" },
161 { XCSI_ISR_SLBF, "Streamline Buffer Full Error" },
162 { XCSI_ISR_STOP, "Lane Stop State" },
163 { XCSI_ISR_SOTERR, "SOT Error" },
164 { XCSI_ISR_SOTSYNCERR, "SOT Sync Error" },
165 { XCSI_ISR_ECC2BERR, "2 Bit ECC Unrecoverable Error" },
166 { XCSI_ISR_ECC1BERR, "1 Bit ECC Recoverable Error" },
167 { XCSI_ISR_CRCERR, "CRC Error" },
168 { XCSI_ISR_DATAIDERR, "Data Id Error" },
169 { XCSI_ISR_VC3FSYNCERR, "Virtual Channel 3 Frame Sync Error" },
170 { XCSI_ISR_VC3FLVLERR, "Virtual Channel 3 Frame Level Error" },
171 { XCSI_ISR_VC2FSYNCERR, "Virtual Channel 2 Frame Sync Error" },
172 { XCSI_ISR_VC2FLVLERR, "Virtual Channel 2 Frame Level Error" },
173 { XCSI_ISR_VC1FSYNCERR, "Virtual Channel 1 Frame Sync Error" },
174 { XCSI_ISR_VC1FLVLERR, "Virtual Channel 1 Frame Level Error" },
175 { XCSI_ISR_VC0FSYNCERR, "Virtual Channel 0 Frame Sync Error" },
176 { XCSI_ISR_VC0FLVLERR, "Virtual Channel 0 Frame Level Error" }
177};
178
179#define XCSI_NUM_EVENTS ARRAY_SIZE(xcsi2rxss_events)
180
181
182
183
184
185static const u32 xcsi2dt_mbus_lut[][2] = {
186 { XCSI_DT_YUV4228B, MEDIA_BUS_FMT_UYVY8_1X16 },
187 { XCSI_DT_YUV42210B, MEDIA_BUS_FMT_UYVY10_1X20 },
188 { XCSI_DT_RGB444, 0 },
189 { XCSI_DT_RGB555, 0 },
190 { XCSI_DT_RGB565, 0 },
191 { XCSI_DT_RGB666, 0 },
192 { XCSI_DT_RGB888, MEDIA_BUS_FMT_RBG888_1X24 },
193 { XCSI_DT_RAW6, 0 },
194 { XCSI_DT_RAW7, 0 },
195 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SRGGB8_1X8 },
196 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SBGGR8_1X8 },
197 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SGBRG8_1X8 },
198 { XCSI_DT_RAW8, MEDIA_BUS_FMT_SGRBG8_1X8 },
199 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SRGGB10_1X10 },
200 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SBGGR10_1X10 },
201 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SGBRG10_1X10 },
202 { XCSI_DT_RAW10, MEDIA_BUS_FMT_SGRBG10_1X10 },
203 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SRGGB12_1X12 },
204 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SBGGR12_1X12 },
205 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SGBRG12_1X12 },
206 { XCSI_DT_RAW12, MEDIA_BUS_FMT_SGRBG12_1X12 },
207 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SRGGB16_1X16 },
208 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SBGGR16_1X16 },
209 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SGBRG16_1X16 },
210 { XCSI_DT_RAW16, MEDIA_BUS_FMT_SGRBG16_1X16 },
211 { XCSI_DT_RAW20, 0 },
212};
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236struct xcsi2rxss_state {
237 struct v4l2_subdev subdev;
238 struct v4l2_mbus_framefmt format;
239 struct v4l2_mbus_framefmt default_format;
240 u32 events[XCSI_NUM_EVENTS];
241 u32 vcx_events[XCSI_VCX_NUM_EVENTS];
242 struct device *dev;
243 struct v4l2_subdev *rsubdev;
244 struct gpio_desc *rst_gpio;
245 struct clk_bulk_data *clks;
246 void __iomem *iomem;
247 u32 max_num_lanes;
248 u32 datatype;
249
250 struct mutex lock;
251 struct media_pad pads[XCSI_MEDIA_PADS];
252 bool streaming;
253 bool enable_active_lanes;
254 bool en_vcx;
255};
256
257static const struct clk_bulk_data xcsi2rxss_clks[] = {
258 { .id = "lite_aclk" },
259 { .id = "video_aclk" },
260};
261
262static inline struct xcsi2rxss_state *
263to_xcsi2rxssstate(struct v4l2_subdev *subdev)
264{
265 return container_of(subdev, struct xcsi2rxss_state, subdev);
266}
267
268
269
270
271static inline u32 xcsi2rxss_read(struct xcsi2rxss_state *xcsi2rxss, u32 addr)
272{
273 return ioread32(xcsi2rxss->iomem + addr);
274}
275
276static inline void xcsi2rxss_write(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
277 u32 value)
278{
279 iowrite32(value, xcsi2rxss->iomem + addr);
280}
281
282static inline void xcsi2rxss_clr(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
283 u32 clr)
284{
285 xcsi2rxss_write(xcsi2rxss, addr,
286 xcsi2rxss_read(xcsi2rxss, addr) & ~clr);
287}
288
289static inline void xcsi2rxss_set(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
290 u32 set)
291{
292 xcsi2rxss_write(xcsi2rxss, addr, xcsi2rxss_read(xcsi2rxss, addr) | set);
293}
294
295
296
297
298
299static u32 xcsi2rxss_get_nth_mbus(u32 dt, u32 n)
300{
301 unsigned int i;
302
303 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
304 if (xcsi2dt_mbus_lut[i][0] == dt) {
305 if (n-- == 0)
306 return xcsi2dt_mbus_lut[i][1];
307 }
308 }
309
310 return 0;
311}
312
313
314static u32 xcsi2rxss_get_dt(u32 mbus)
315{
316 unsigned int i;
317
318 for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
319 if (xcsi2dt_mbus_lut[i][1] == mbus)
320 return xcsi2dt_mbus_lut[i][0];
321 }
322
323 return 0;
324}
325
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328
329
330
331
332
333
334
335static int xcsi2rxss_soft_reset(struct xcsi2rxss_state *state)
336{
337 u32 timeout = 1000;
338
339 xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
340
341 while (xcsi2rxss_read(state, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD) {
342 if (timeout == 0) {
343 dev_err(state->dev, "soft reset timed out!\n");
344 return -ETIME;
345 }
346
347 timeout--;
348 udelay(1);
349 }
350
351 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
352 return 0;
353}
354
355static void xcsi2rxss_hard_reset(struct xcsi2rxss_state *state)
356{
357 if (!state->rst_gpio)
358 return;
359
360
361 gpiod_set_value_cansleep(state->rst_gpio, 1);
362 usleep_range(1, 2);
363 gpiod_set_value_cansleep(state->rst_gpio, 0);
364}
365
366static void xcsi2rxss_reset_event_counters(struct xcsi2rxss_state *state)
367{
368 unsigned int i;
369
370 for (i = 0; i < XCSI_NUM_EVENTS; i++)
371 state->events[i] = 0;
372
373 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++)
374 state->vcx_events[i] = 0;
375}
376
377
378static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state)
379{
380 struct device *dev = state->dev;
381 unsigned int i;
382
383 for (i = 0; i < XCSI_NUM_EVENTS; i++) {
384 if (state->events[i] > 0) {
385 dev_info(dev, "%s events: %d\n",
386 xcsi2rxss_events[i].name,
387 state->events[i]);
388 }
389 }
390
391 if (state->en_vcx) {
392 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
393 if (state->vcx_events[i] > 0) {
394 dev_info(dev,
395 "VC %d Frame %s err vcx events: %d\n",
396 (i / 2) + XCSI_VCX_START,
397 i & 1 ? "Sync" : "Level",
398 state->vcx_events[i]);
399 }
400 }
401 }
402}
403
404
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410
411
412static int xcsi2rxss_log_status(struct v4l2_subdev *sd)
413{
414 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
415 struct device *dev = xcsi2rxss->dev;
416 u32 reg, data;
417 unsigned int i, max_vc;
418
419 mutex_lock(&xcsi2rxss->lock);
420
421 xcsi2rxss_log_counters(xcsi2rxss);
422
423 dev_info(dev, "***** Core Status *****\n");
424 data = xcsi2rxss_read(xcsi2rxss, XCSI_CSR_OFFSET);
425 dev_info(dev, "Short Packet FIFO Full = %s\n",
426 data & XCSI_CSR_SPFIFOFULL ? "true" : "false");
427 dev_info(dev, "Short Packet FIFO Not Empty = %s\n",
428 data & XCSI_CSR_SPFIFONE ? "true" : "false");
429 dev_info(dev, "Stream line buffer full = %s\n",
430 data & XCSI_CSR_SLBF ? "true" : "false");
431 dev_info(dev, "Soft reset/Core disable in progress = %s\n",
432 data & XCSI_CSR_RIPCD ? "true" : "false");
433
434
435 dev_info(dev, "******** Clock Lane Info *********\n");
436 data = xcsi2rxss_read(xcsi2rxss, XCSI_CLKINFR_OFFSET);
437 dev_info(dev, "Clock Lane in Stop State = %s\n",
438 data & XCSI_CLKINFR_STOP ? "true" : "false");
439
440 dev_info(dev, "******** Data Lane Info *********\n");
441 dev_info(dev, "Lane\tSoT Error\tSoT Sync Error\tStop State\n");
442 reg = XCSI_DLXINFR_OFFSET;
443 for (i = 0; i < XCSI_MAXDL_COUNT; i++) {
444 data = xcsi2rxss_read(xcsi2rxss, reg);
445
446 dev_info(dev, "%d\t%s\t\t%s\t\t%s\n", i,
447 data & XCSI_DLXINFR_SOTERR ? "true" : "false",
448 data & XCSI_DLXINFR_SOTSYNCERR ? "true" : "false",
449 data & XCSI_DLXINFR_STOP ? "true" : "false");
450
451 reg += XCSI_NEXTREG_OFFSET;
452 }
453
454
455 dev_info(dev, "********** Virtual Channel Info ************\n");
456 dev_info(dev, "VC\tLine Count\tByte Count\tData Type\n");
457 if (xcsi2rxss->en_vcx)
458 max_vc = XCSI_MAX_VCX;
459 else
460 max_vc = XCSI_MAX_VC;
461
462 reg = XCSI_VCXINF1R_OFFSET;
463 for (i = 0; i < max_vc; i++) {
464 u32 line_count, byte_count, data_type;
465
466
467 data = xcsi2rxss_read(xcsi2rxss, reg);
468 byte_count = data & XCSI_VCXINF1R_BYTECOUNT;
469 line_count = data & XCSI_VCXINF1R_LINECOUNT;
470 line_count >>= XCSI_VCXINF1R_LINECOUNT_SHIFT;
471
472
473 reg += XCSI_NEXTREG_OFFSET;
474 data = xcsi2rxss_read(xcsi2rxss, reg);
475 data_type = data & XCSI_VCXINF2R_DT;
476
477 dev_info(dev, "%d\t%d\t\t%d\t\t0x%x\n", i, line_count,
478 byte_count, data_type);
479
480
481 reg += XCSI_NEXTREG_OFFSET;
482 }
483
484 mutex_unlock(&xcsi2rxss->lock);
485
486 return 0;
487}
488
489static struct v4l2_subdev *xcsi2rxss_get_remote_subdev(struct media_pad *local)
490{
491 struct media_pad *remote;
492
493 remote = media_entity_remote_pad(local);
494 if (!remote || !is_media_entity_v4l2_subdev(remote->entity))
495 return NULL;
496
497 return media_entity_to_v4l2_subdev(remote->entity);
498}
499
500static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
501{
502 int ret = 0;
503
504
505 xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
506
507 ret = xcsi2rxss_soft_reset(state);
508 if (ret) {
509 state->streaming = false;
510 return ret;
511 }
512
513
514 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
515 xcsi2rxss_write(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
516 xcsi2rxss_set(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
517
518 state->streaming = true;
519
520 state->rsubdev =
521 xcsi2rxss_get_remote_subdev(&state->pads[XVIP_PAD_SINK]);
522
523 ret = v4l2_subdev_call(state->rsubdev, video, s_stream, 1);
524 if (ret) {
525
526 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
527 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
528
529
530 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
531 state->streaming = false;
532 }
533
534 return ret;
535}
536
537static void xcsi2rxss_stop_stream(struct xcsi2rxss_state *state)
538{
539 v4l2_subdev_call(state->rsubdev, video, s_stream, 0);
540
541
542 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
543 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
544
545
546 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
547 state->streaming = false;
548}
549
550
551
552
553
554
555
556
557
558
559
560static irqreturn_t xcsi2rxss_irq_handler(int irq, void *data)
561{
562 struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)data;
563 struct device *dev = state->dev;
564 u32 status;
565
566 status = xcsi2rxss_read(state, XCSI_ISR_OFFSET) & XCSI_ISR_ALLINTR_MASK;
567 xcsi2rxss_write(state, XCSI_ISR_OFFSET, status);
568
569
570 if (status & XCSI_ISR_SPFIFONE) {
571 u32 count = 0;
572
573
574
575
576
577 for (count = 0; count < XCSI_SPKT_FIFO_DEPTH; ++count) {
578 u32 spfifostat, spkt;
579
580 spkt = xcsi2rxss_read(state, XCSI_SPKTR_OFFSET);
581 dev_dbg(dev, "Short packet = 0x%08x\n", spkt);
582 spfifostat = xcsi2rxss_read(state, XCSI_ISR_OFFSET);
583 spfifostat &= XCSI_ISR_SPFIFONE;
584 if (!spfifostat)
585 break;
586 xcsi2rxss_write(state, XCSI_ISR_OFFSET, spfifostat);
587 }
588 }
589
590
591 if (status & XCSI_ISR_SPFIFOF)
592 dev_dbg_ratelimited(dev, "Short packet FIFO overflowed\n");
593
594
595
596
597
598 if (status & XCSI_ISR_SLBF) {
599 dev_alert_ratelimited(dev, "Stream Line Buffer Full!\n");
600
601
602 xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
603 xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
604
605
606 xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
607
608
609
610
611
612
613
614
615
616
617 }
618
619
620 if (status & XCSI_ISR_ALLINTR_MASK) {
621 unsigned int i;
622
623 for (i = 0; i < XCSI_NUM_EVENTS; i++) {
624 if (!(status & xcsi2rxss_events[i].mask))
625 continue;
626 state->events[i]++;
627 dev_dbg_ratelimited(dev, "%s: %u\n",
628 xcsi2rxss_events[i].name,
629 state->events[i]);
630 }
631
632 if (status & XCSI_ISR_VCXFE && state->en_vcx) {
633 u32 vcxstatus;
634
635 vcxstatus = xcsi2rxss_read(state, XCSI_VCXR_OFFSET);
636 vcxstatus &= XCSI_VCXR_VCERR;
637 for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
638 if (!(vcxstatus & BIT(i)))
639 continue;
640 state->vcx_events[i]++;
641 }
642 xcsi2rxss_write(state, XCSI_VCXR_OFFSET, vcxstatus);
643 }
644 }
645
646 return IRQ_HANDLED;
647}
648
649
650
651
652
653
654
655
656
657
658
659static int xcsi2rxss_s_stream(struct v4l2_subdev *sd, int enable)
660{
661 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
662 int ret = 0;
663
664 mutex_lock(&xcsi2rxss->lock);
665
666 if (enable == xcsi2rxss->streaming)
667 goto stream_done;
668
669 if (enable) {
670 xcsi2rxss_reset_event_counters(xcsi2rxss);
671 ret = xcsi2rxss_start_stream(xcsi2rxss);
672 } else {
673 xcsi2rxss_stop_stream(xcsi2rxss);
674 xcsi2rxss_hard_reset(xcsi2rxss);
675 }
676
677stream_done:
678 mutex_unlock(&xcsi2rxss->lock);
679 return ret;
680}
681
682static struct v4l2_mbus_framefmt *
683__xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss,
684 struct v4l2_subdev_state *sd_state,
685 unsigned int pad, u32 which)
686{
687 switch (which) {
688 case V4L2_SUBDEV_FORMAT_TRY:
689 return v4l2_subdev_get_try_format(&xcsi2rxss->subdev,
690 sd_state, pad);
691 case V4L2_SUBDEV_FORMAT_ACTIVE:
692 return &xcsi2rxss->format;
693 default:
694 return NULL;
695 }
696}
697
698
699
700
701
702
703
704
705
706
707
708static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd,
709 struct v4l2_subdev_state *sd_state)
710{
711 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
712 struct v4l2_mbus_framefmt *format;
713 unsigned int i;
714
715 mutex_lock(&xcsi2rxss->lock);
716 for (i = 0; i < XCSI_MEDIA_PADS; i++) {
717 format = v4l2_subdev_get_try_format(sd, sd_state, i);
718 *format = xcsi2rxss->default_format;
719 }
720 mutex_unlock(&xcsi2rxss->lock);
721
722 return 0;
723}
724
725
726
727
728
729
730
731
732
733
734
735static int xcsi2rxss_get_format(struct v4l2_subdev *sd,
736 struct v4l2_subdev_state *sd_state,
737 struct v4l2_subdev_format *fmt)
738{
739 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
740
741 mutex_lock(&xcsi2rxss->lock);
742 fmt->format = *__xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
743 fmt->pad,
744 fmt->which);
745 mutex_unlock(&xcsi2rxss->lock);
746
747 return 0;
748}
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763static int xcsi2rxss_set_format(struct v4l2_subdev *sd,
764 struct v4l2_subdev_state *sd_state,
765 struct v4l2_subdev_format *fmt)
766{
767 struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
768 struct v4l2_mbus_framefmt *__format;
769 u32 dt;
770
771 mutex_lock(&xcsi2rxss->lock);
772
773
774
775
776
777
778 __format = __xcsi2rxss_get_pad_format(xcsi2rxss, sd_state,
779 fmt->pad, fmt->which);
780
781
782 if (fmt->pad == XVIP_PAD_SOURCE) {
783 fmt->format = *__format;
784 mutex_unlock(&xcsi2rxss->lock);
785 return 0;
786 }
787
788
789
790
791
792
793 dt = xcsi2rxss_get_dt(fmt->format.code);
794 if (dt != xcsi2rxss->datatype && dt != XCSI_DT_RAW8) {
795 dev_dbg(xcsi2rxss->dev, "Unsupported media bus format");
796
797 fmt->format.code = xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype,
798 0);
799 }
800
801 *__format = fmt->format;
802 mutex_unlock(&xcsi2rxss->lock);
803
804 return 0;
805}
806
807
808
809
810
811
812
813
814
815static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,
816 struct v4l2_subdev_state *sd_state,
817 struct v4l2_subdev_mbus_code_enum *code)
818{
819 struct xcsi2rxss_state *state = to_xcsi2rxssstate(sd);
820 u32 dt, n;
821 int ret = 0;
822
823
824 if (code->index < 4) {
825 n = code->index;
826 dt = XCSI_DT_RAW8;
827 } else if (state->datatype != XCSI_DT_RAW8) {
828 n = code->index - 4;
829 dt = state->datatype;
830 } else {
831 return -EINVAL;
832 }
833
834 code->code = xcsi2rxss_get_nth_mbus(dt, n);
835 if (!code->code)
836 ret = -EINVAL;
837
838 return ret;
839}
840
841
842
843
844
845static const struct media_entity_operations xcsi2rxss_media_ops = {
846 .link_validate = v4l2_subdev_link_validate
847};
848
849static const struct v4l2_subdev_core_ops xcsi2rxss_core_ops = {
850 .log_status = xcsi2rxss_log_status,
851};
852
853static const struct v4l2_subdev_video_ops xcsi2rxss_video_ops = {
854 .s_stream = xcsi2rxss_s_stream
855};
856
857static const struct v4l2_subdev_pad_ops xcsi2rxss_pad_ops = {
858 .init_cfg = xcsi2rxss_init_cfg,
859 .get_fmt = xcsi2rxss_get_format,
860 .set_fmt = xcsi2rxss_set_format,
861 .enum_mbus_code = xcsi2rxss_enum_mbus_code,
862 .link_validate = v4l2_subdev_link_validate_default,
863};
864
865static const struct v4l2_subdev_ops xcsi2rxss_ops = {
866 .core = &xcsi2rxss_core_ops,
867 .video = &xcsi2rxss_video_ops,
868 .pad = &xcsi2rxss_pad_ops
869};
870
871static int xcsi2rxss_parse_of(struct xcsi2rxss_state *xcsi2rxss)
872{
873 struct device *dev = xcsi2rxss->dev;
874 struct device_node *node = dev->of_node;
875
876 struct fwnode_handle *ep;
877 struct v4l2_fwnode_endpoint vep = {
878 .bus_type = V4L2_MBUS_CSI2_DPHY
879 };
880 bool en_csi_v20, vfb;
881 int ret;
882
883 en_csi_v20 = of_property_read_bool(node, "xlnx,en-csi-v2-0");
884 if (en_csi_v20)
885 xcsi2rxss->en_vcx = of_property_read_bool(node, "xlnx,en-vcx");
886
887 xcsi2rxss->enable_active_lanes =
888 of_property_read_bool(node, "xlnx,en-active-lanes");
889
890 ret = of_property_read_u32(node, "xlnx,csi-pxl-format",
891 &xcsi2rxss->datatype);
892 if (ret < 0) {
893 dev_err(dev, "missing xlnx,csi-pxl-format property\n");
894 return ret;
895 }
896
897 switch (xcsi2rxss->datatype) {
898 case XCSI_DT_YUV4228B:
899 case XCSI_DT_RGB444:
900 case XCSI_DT_RGB555:
901 case XCSI_DT_RGB565:
902 case XCSI_DT_RGB666:
903 case XCSI_DT_RGB888:
904 case XCSI_DT_RAW6:
905 case XCSI_DT_RAW7:
906 case XCSI_DT_RAW8:
907 case XCSI_DT_RAW10:
908 case XCSI_DT_RAW12:
909 case XCSI_DT_RAW14:
910 break;
911 case XCSI_DT_YUV42210B:
912 case XCSI_DT_RAW16:
913 case XCSI_DT_RAW20:
914 if (!en_csi_v20) {
915 ret = -EINVAL;
916 dev_dbg(dev, "enable csi v2 for this pixel format");
917 }
918 break;
919 default:
920 ret = -EINVAL;
921 }
922 if (ret < 0) {
923 dev_err(dev, "invalid csi-pxl-format property!\n");
924 return ret;
925 }
926
927 vfb = of_property_read_bool(node, "xlnx,vfb");
928 if (!vfb) {
929 dev_err(dev, "operation without VFB is not supported\n");
930 return -EINVAL;
931 }
932
933 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
934 XVIP_PAD_SINK, 0,
935 FWNODE_GRAPH_ENDPOINT_NEXT);
936 if (!ep) {
937 dev_err(dev, "no sink port found");
938 return -EINVAL;
939 }
940
941 ret = v4l2_fwnode_endpoint_parse(ep, &vep);
942 fwnode_handle_put(ep);
943 if (ret) {
944 dev_err(dev, "error parsing sink port");
945 return ret;
946 }
947
948 dev_dbg(dev, "mipi number lanes = %d\n",
949 vep.bus.mipi_csi2.num_data_lanes);
950
951 xcsi2rxss->max_num_lanes = vep.bus.mipi_csi2.num_data_lanes;
952
953 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
954 XVIP_PAD_SOURCE, 0,
955 FWNODE_GRAPH_ENDPOINT_NEXT);
956 if (!ep) {
957 dev_err(dev, "no source port found");
958 return -EINVAL;
959 }
960
961 fwnode_handle_put(ep);
962
963 dev_dbg(dev, "vcx %s, %u data lanes (%s), data type 0x%02x\n",
964 xcsi2rxss->en_vcx ? "enabled" : "disabled",
965 xcsi2rxss->max_num_lanes,
966 xcsi2rxss->enable_active_lanes ? "dynamic" : "static",
967 xcsi2rxss->datatype);
968
969 return 0;
970}
971
972static int xcsi2rxss_probe(struct platform_device *pdev)
973{
974 struct v4l2_subdev *subdev;
975 struct xcsi2rxss_state *xcsi2rxss;
976 int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
977 struct device *dev = &pdev->dev;
978 int irq, ret;
979
980 xcsi2rxss = devm_kzalloc(dev, sizeof(*xcsi2rxss), GFP_KERNEL);
981 if (!xcsi2rxss)
982 return -ENOMEM;
983
984 xcsi2rxss->dev = dev;
985
986 xcsi2rxss->clks = devm_kmemdup(dev, xcsi2rxss_clks,
987 sizeof(xcsi2rxss_clks), GFP_KERNEL);
988 if (!xcsi2rxss->clks)
989 return -ENOMEM;
990
991
992 xcsi2rxss->rst_gpio = devm_gpiod_get_optional(dev, "video-reset",
993 GPIOD_OUT_HIGH);
994 if (IS_ERR(xcsi2rxss->rst_gpio)) {
995 if (PTR_ERR(xcsi2rxss->rst_gpio) != -EPROBE_DEFER)
996 dev_err(dev, "Video Reset GPIO not setup in DT");
997 return PTR_ERR(xcsi2rxss->rst_gpio);
998 }
999
1000 ret = xcsi2rxss_parse_of(xcsi2rxss);
1001 if (ret < 0)
1002 return ret;
1003
1004 xcsi2rxss->iomem = devm_platform_ioremap_resource(pdev, 0);
1005 if (IS_ERR(xcsi2rxss->iomem))
1006 return PTR_ERR(xcsi2rxss->iomem);
1007
1008 irq = platform_get_irq(pdev, 0);
1009 if (irq < 0)
1010 return irq;
1011
1012 ret = devm_request_threaded_irq(dev, irq, NULL,
1013 xcsi2rxss_irq_handler, IRQF_ONESHOT,
1014 dev_name(dev), xcsi2rxss);
1015 if (ret) {
1016 dev_err(dev, "Err = %d Interrupt handler reg failed!\n", ret);
1017 return ret;
1018 }
1019
1020 ret = clk_bulk_get(dev, num_clks, xcsi2rxss->clks);
1021 if (ret)
1022 return ret;
1023
1024
1025 ret = clk_bulk_prepare_enable(num_clks, xcsi2rxss->clks);
1026 if (ret)
1027 goto err_clk_put;
1028
1029 mutex_init(&xcsi2rxss->lock);
1030
1031 xcsi2rxss_hard_reset(xcsi2rxss);
1032 xcsi2rxss_soft_reset(xcsi2rxss);
1033
1034
1035 xcsi2rxss->pads[XVIP_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1036 xcsi2rxss->pads[XVIP_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1037
1038
1039 xcsi2rxss->default_format.code =
1040 xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype, 0);
1041 xcsi2rxss->default_format.field = V4L2_FIELD_NONE;
1042 xcsi2rxss->default_format.colorspace = V4L2_COLORSPACE_SRGB;
1043 xcsi2rxss->default_format.width = XCSI_DEFAULT_WIDTH;
1044 xcsi2rxss->default_format.height = XCSI_DEFAULT_HEIGHT;
1045 xcsi2rxss->format = xcsi2rxss->default_format;
1046
1047
1048 subdev = &xcsi2rxss->subdev;
1049 v4l2_subdev_init(subdev, &xcsi2rxss_ops);
1050 subdev->dev = dev;
1051 strscpy(subdev->name, dev_name(dev), sizeof(subdev->name));
1052 subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
1053 subdev->entity.ops = &xcsi2rxss_media_ops;
1054 v4l2_set_subdevdata(subdev, xcsi2rxss);
1055
1056 ret = media_entity_pads_init(&subdev->entity, XCSI_MEDIA_PADS,
1057 xcsi2rxss->pads);
1058 if (ret < 0)
1059 goto error;
1060
1061 platform_set_drvdata(pdev, xcsi2rxss);
1062
1063 ret = v4l2_async_register_subdev(subdev);
1064 if (ret < 0) {
1065 dev_err(dev, "failed to register subdev\n");
1066 goto error;
1067 }
1068
1069 return 0;
1070error:
1071 media_entity_cleanup(&subdev->entity);
1072 mutex_destroy(&xcsi2rxss->lock);
1073 clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
1074err_clk_put:
1075 clk_bulk_put(num_clks, xcsi2rxss->clks);
1076 return ret;
1077}
1078
1079static int xcsi2rxss_remove(struct platform_device *pdev)
1080{
1081 struct xcsi2rxss_state *xcsi2rxss = platform_get_drvdata(pdev);
1082 struct v4l2_subdev *subdev = &xcsi2rxss->subdev;
1083 int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
1084
1085 v4l2_async_unregister_subdev(subdev);
1086 media_entity_cleanup(&subdev->entity);
1087 mutex_destroy(&xcsi2rxss->lock);
1088 clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
1089 clk_bulk_put(num_clks, xcsi2rxss->clks);
1090
1091 return 0;
1092}
1093
1094static const struct of_device_id xcsi2rxss_of_id_table[] = {
1095 { .compatible = "xlnx,mipi-csi2-rx-subsystem-5.0", },
1096 { }
1097};
1098MODULE_DEVICE_TABLE(of, xcsi2rxss_of_id_table);
1099
1100static struct platform_driver xcsi2rxss_driver = {
1101 .driver = {
1102 .name = "xilinx-csi2rxss",
1103 .of_match_table = xcsi2rxss_of_id_table,
1104 },
1105 .probe = xcsi2rxss_probe,
1106 .remove = xcsi2rxss_remove,
1107};
1108
1109module_platform_driver(xcsi2rxss_driver);
1110
1111MODULE_AUTHOR("Vishal Sagar <vsagar@xilinx.com>");
1112MODULE_DESCRIPTION("Xilinx MIPI CSI-2 Rx Subsystem Driver");
1113MODULE_LICENSE("GPL v2");
1114