linux/drivers/iommu/rockchip-iommu.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * IOMMU API for Rockchip
   4 *
   5 * Module Authors:      Simon Xue <xxm@rock-chips.com>
   6 *                      Daniel Kurtz <djkurtz@chromium.org>
   7 */
   8
   9#include <linux/clk.h>
  10#include <linux/compiler.h>
  11#include <linux/delay.h>
  12#include <linux/device.h>
  13#include <linux/dma-iommu.h>
  14#include <linux/dma-mapping.h>
  15#include <linux/errno.h>
  16#include <linux/interrupt.h>
  17#include <linux/io.h>
  18#include <linux/iommu.h>
  19#include <linux/iopoll.h>
  20#include <linux/list.h>
  21#include <linux/mm.h>
  22#include <linux/init.h>
  23#include <linux/of.h>
  24#include <linux/of_platform.h>
  25#include <linux/platform_device.h>
  26#include <linux/pm_runtime.h>
  27#include <linux/slab.h>
  28#include <linux/spinlock.h>
  29
  30/** MMU register offsets */
  31#define RK_MMU_DTE_ADDR         0x00    /* Directory table address */
  32#define RK_MMU_STATUS           0x04
  33#define RK_MMU_COMMAND          0x08
  34#define RK_MMU_PAGE_FAULT_ADDR  0x0C    /* IOVA of last page fault */
  35#define RK_MMU_ZAP_ONE_LINE     0x10    /* Shootdown one IOTLB entry */
  36#define RK_MMU_INT_RAWSTAT      0x14    /* IRQ status ignoring mask */
  37#define RK_MMU_INT_CLEAR        0x18    /* Acknowledge and re-arm irq */
  38#define RK_MMU_INT_MASK         0x1C    /* IRQ enable */
  39#define RK_MMU_INT_STATUS       0x20    /* IRQ status after masking */
  40#define RK_MMU_AUTO_GATING      0x24
  41
  42#define DTE_ADDR_DUMMY          0xCAFEBABE
  43
  44#define RK_MMU_POLL_PERIOD_US           100
  45#define RK_MMU_FORCE_RESET_TIMEOUT_US   100000
  46#define RK_MMU_POLL_TIMEOUT_US          1000
  47
  48/* RK_MMU_STATUS fields */
  49#define RK_MMU_STATUS_PAGING_ENABLED       BIT(0)
  50#define RK_MMU_STATUS_PAGE_FAULT_ACTIVE    BIT(1)
  51#define RK_MMU_STATUS_STALL_ACTIVE         BIT(2)
  52#define RK_MMU_STATUS_IDLE                 BIT(3)
  53#define RK_MMU_STATUS_REPLAY_BUFFER_EMPTY  BIT(4)
  54#define RK_MMU_STATUS_PAGE_FAULT_IS_WRITE  BIT(5)
  55#define RK_MMU_STATUS_STALL_NOT_ACTIVE     BIT(31)
  56
  57/* RK_MMU_COMMAND command values */
  58#define RK_MMU_CMD_ENABLE_PAGING    0  /* Enable memory translation */
  59#define RK_MMU_CMD_DISABLE_PAGING   1  /* Disable memory translation */
  60#define RK_MMU_CMD_ENABLE_STALL     2  /* Stall paging to allow other cmds */
  61#define RK_MMU_CMD_DISABLE_STALL    3  /* Stop stall re-enables paging */
  62#define RK_MMU_CMD_ZAP_CACHE        4  /* Shoot down entire IOTLB */
  63#define RK_MMU_CMD_PAGE_FAULT_DONE  5  /* Clear page fault */
  64#define RK_MMU_CMD_FORCE_RESET      6  /* Reset all registers */
  65
  66/* RK_MMU_INT_* register fields */
  67#define RK_MMU_IRQ_PAGE_FAULT    0x01  /* page fault */
  68#define RK_MMU_IRQ_BUS_ERROR     0x02  /* bus read error */
  69#define RK_MMU_IRQ_MASK          (RK_MMU_IRQ_PAGE_FAULT | RK_MMU_IRQ_BUS_ERROR)
  70
  71#define NUM_DT_ENTRIES 1024
  72#define NUM_PT_ENTRIES 1024
  73
  74#define SPAGE_ORDER 12
  75#define SPAGE_SIZE (1 << SPAGE_ORDER)
  76
  77 /*
  78  * Support mapping any size that fits in one page table:
  79  *   4 KiB to 4 MiB
  80  */
  81#define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
  82
  83struct rk_iommu_domain {
  84        struct list_head iommus;
  85        u32 *dt; /* page directory table */
  86        dma_addr_t dt_dma;
  87        spinlock_t iommus_lock; /* lock for iommus list */
  88        spinlock_t dt_lock; /* lock for modifying page directory table */
  89
  90        struct iommu_domain domain;
  91};
  92
  93/* list of clocks required by IOMMU */
  94static const char * const rk_iommu_clocks[] = {
  95        "aclk", "iface",
  96};
  97
  98struct rk_iommu_ops {
  99        phys_addr_t (*pt_address)(u32 dte);
 100        u32 (*mk_dtentries)(dma_addr_t pt_dma);
 101        u32 (*mk_ptentries)(phys_addr_t page, int prot);
 102        phys_addr_t (*dte_addr_phys)(u32 addr);
 103        u32 (*dma_addr_dte)(dma_addr_t dt_dma);
 104        u64 dma_bit_mask;
 105};
 106
 107struct rk_iommu {
 108        struct device *dev;
 109        void __iomem **bases;
 110        int num_mmu;
 111        int num_irq;
 112        struct clk_bulk_data *clocks;
 113        int num_clocks;
 114        bool reset_disabled;
 115        struct iommu_device iommu;
 116        struct list_head node; /* entry in rk_iommu_domain.iommus */
 117        struct iommu_domain *domain; /* domain to which iommu is attached */
 118        struct iommu_group *group;
 119};
 120
 121struct rk_iommudata {
 122        struct device_link *link; /* runtime PM link from IOMMU to master */
 123        struct rk_iommu *iommu;
 124};
 125
 126static struct device *dma_dev;
 127static const struct rk_iommu_ops *rk_ops;
 128
 129static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
 130                                  unsigned int count)
 131{
 132        size_t size = count * sizeof(u32); /* count of u32 entry */
 133
 134        dma_sync_single_for_device(dma_dev, dma, size, DMA_TO_DEVICE);
 135}
 136
 137static struct rk_iommu_domain *to_rk_domain(struct iommu_domain *dom)
 138{
 139        return container_of(dom, struct rk_iommu_domain, domain);
 140}
 141
 142/*
 143 * The Rockchip rk3288 iommu uses a 2-level page table.
 144 * The first level is the "Directory Table" (DT).
 145 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
 146 * to a "Page Table".
 147 * The second level is the 1024 Page Tables (PT).
 148 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
 149 * a 4 KB page of physical memory.
 150 *
 151 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
 152 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
 153 * address of the start of the DT page.
 154 *
 155 * The structure of the page table is as follows:
 156 *
 157 *                   DT
 158 * MMU_DTE_ADDR -> +-----+
 159 *                 |     |
 160 *                 +-----+     PT
 161 *                 | DTE | -> +-----+
 162 *                 +-----+    |     |     Memory
 163 *                 |     |    +-----+     Page
 164 *                 |     |    | PTE | -> +-----+
 165 *                 +-----+    +-----+    |     |
 166 *                            |     |    |     |
 167 *                            |     |    |     |
 168 *                            +-----+    |     |
 169 *                                       |     |
 170 *                                       |     |
 171 *                                       +-----+
 172 */
 173
 174/*
 175 * Each DTE has a PT address and a valid bit:
 176 * +---------------------+-----------+-+
 177 * | PT address          | Reserved  |V|
 178 * +---------------------+-----------+-+
 179 *  31:12 - PT address (PTs always starts on a 4 KB boundary)
 180 *  11: 1 - Reserved
 181 *      0 - 1 if PT @ PT address is valid
 182 */
 183#define RK_DTE_PT_ADDRESS_MASK    0xfffff000
 184#define RK_DTE_PT_VALID           BIT(0)
 185
 186static inline phys_addr_t rk_dte_pt_address(u32 dte)
 187{
 188        return (phys_addr_t)dte & RK_DTE_PT_ADDRESS_MASK;
 189}
 190
 191/*
 192 * In v2:
 193 * 31:12 - PT address bit 31:0
 194 * 11: 8 - PT address bit 35:32
 195 *  7: 4 - PT address bit 39:36
 196 *  3: 1 - Reserved
 197 *     0 - 1 if PT @ PT address is valid
 198 */
 199#define RK_DTE_PT_ADDRESS_MASK_V2 GENMASK_ULL(31, 4)
 200#define DTE_HI_MASK1    GENMASK(11, 8)
 201#define DTE_HI_MASK2    GENMASK(7, 4)
 202#define DTE_HI_SHIFT1   24 /* shift bit 8 to bit 32 */
 203#define DTE_HI_SHIFT2   32 /* shift bit 4 to bit 36 */
 204#define PAGE_DESC_HI_MASK1      GENMASK_ULL(39, 36)
 205#define PAGE_DESC_HI_MASK2      GENMASK_ULL(35, 32)
 206
 207static inline phys_addr_t rk_dte_pt_address_v2(u32 dte)
 208{
 209        u64 dte_v2 = dte;
 210
 211        dte_v2 = ((dte_v2 & DTE_HI_MASK2) << DTE_HI_SHIFT2) |
 212                 ((dte_v2 & DTE_HI_MASK1) << DTE_HI_SHIFT1) |
 213                 (dte_v2 & RK_DTE_PT_ADDRESS_MASK);
 214
 215        return (phys_addr_t)dte_v2;
 216}
 217
 218static inline bool rk_dte_is_pt_valid(u32 dte)
 219{
 220        return dte & RK_DTE_PT_VALID;
 221}
 222
 223static inline u32 rk_mk_dte(dma_addr_t pt_dma)
 224{
 225        return (pt_dma & RK_DTE_PT_ADDRESS_MASK) | RK_DTE_PT_VALID;
 226}
 227
 228static inline u32 rk_mk_dte_v2(dma_addr_t pt_dma)
 229{
 230        pt_dma = (pt_dma & RK_DTE_PT_ADDRESS_MASK) |
 231                 ((pt_dma & PAGE_DESC_HI_MASK1) >> DTE_HI_SHIFT1) |
 232                 (pt_dma & PAGE_DESC_HI_MASK2) >> DTE_HI_SHIFT2;
 233
 234        return (pt_dma & RK_DTE_PT_ADDRESS_MASK_V2) | RK_DTE_PT_VALID;
 235}
 236
 237/*
 238 * Each PTE has a Page address, some flags and a valid bit:
 239 * +---------------------+---+-------+-+
 240 * | Page address        |Rsv| Flags |V|
 241 * +---------------------+---+-------+-+
 242 *  31:12 - Page address (Pages always start on a 4 KB boundary)
 243 *  11: 9 - Reserved
 244 *   8: 1 - Flags
 245 *      8 - Read allocate - allocate cache space on read misses
 246 *      7 - Read cache - enable cache & prefetch of data
 247 *      6 - Write buffer - enable delaying writes on their way to memory
 248 *      5 - Write allocate - allocate cache space on write misses
 249 *      4 - Write cache - different writes can be merged together
 250 *      3 - Override cache attributes
 251 *          if 1, bits 4-8 control cache attributes
 252 *          if 0, the system bus defaults are used
 253 *      2 - Writable
 254 *      1 - Readable
 255 *      0 - 1 if Page @ Page address is valid
 256 */
 257#define RK_PTE_PAGE_ADDRESS_MASK  0xfffff000
 258#define RK_PTE_PAGE_FLAGS_MASK    0x000001fe
 259#define RK_PTE_PAGE_WRITABLE      BIT(2)
 260#define RK_PTE_PAGE_READABLE      BIT(1)
 261#define RK_PTE_PAGE_VALID         BIT(0)
 262
 263static inline bool rk_pte_is_page_valid(u32 pte)
 264{
 265        return pte & RK_PTE_PAGE_VALID;
 266}
 267
 268/* TODO: set cache flags per prot IOMMU_CACHE */
 269static u32 rk_mk_pte(phys_addr_t page, int prot)
 270{
 271        u32 flags = 0;
 272        flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE : 0;
 273        flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE : 0;
 274        page &= RK_PTE_PAGE_ADDRESS_MASK;
 275        return page | flags | RK_PTE_PAGE_VALID;
 276}
 277
 278/*
 279 * In v2:
 280 * 31:12 - Page address bit 31:0
 281 *  11:9 - Page address bit 34:32
 282 *   8:4 - Page address bit 39:35
 283 *     3 - Security
 284 *     2 - Readable
 285 *     1 - Writable
 286 *     0 - 1 if Page @ Page address is valid
 287 */
 288#define RK_PTE_PAGE_READABLE_V2      BIT(2)
 289#define RK_PTE_PAGE_WRITABLE_V2      BIT(1)
 290
 291static u32 rk_mk_pte_v2(phys_addr_t page, int prot)
 292{
 293        u32 flags = 0;
 294
 295        flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
 296        flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
 297
 298        return rk_mk_dte_v2(page) | flags;
 299}
 300
 301static u32 rk_mk_pte_invalid(u32 pte)
 302{
 303        return pte & ~RK_PTE_PAGE_VALID;
 304}
 305
 306/*
 307 * rk3288 iova (IOMMU Virtual Address) format
 308 *  31       22.21       12.11          0
 309 * +-----------+-----------+-------------+
 310 * | DTE index | PTE index | Page offset |
 311 * +-----------+-----------+-------------+
 312 *  31:22 - DTE index   - index of DTE in DT
 313 *  21:12 - PTE index   - index of PTE in PT @ DTE.pt_address
 314 *  11: 0 - Page offset - offset into page @ PTE.page_address
 315 */
 316#define RK_IOVA_DTE_MASK    0xffc00000
 317#define RK_IOVA_DTE_SHIFT   22
 318#define RK_IOVA_PTE_MASK    0x003ff000
 319#define RK_IOVA_PTE_SHIFT   12
 320#define RK_IOVA_PAGE_MASK   0x00000fff
 321#define RK_IOVA_PAGE_SHIFT  0
 322
 323static u32 rk_iova_dte_index(dma_addr_t iova)
 324{
 325        return (u32)(iova & RK_IOVA_DTE_MASK) >> RK_IOVA_DTE_SHIFT;
 326}
 327
 328static u32 rk_iova_pte_index(dma_addr_t iova)
 329{
 330        return (u32)(iova & RK_IOVA_PTE_MASK) >> RK_IOVA_PTE_SHIFT;
 331}
 332
 333static u32 rk_iova_page_offset(dma_addr_t iova)
 334{
 335        return (u32)(iova & RK_IOVA_PAGE_MASK) >> RK_IOVA_PAGE_SHIFT;
 336}
 337
 338static u32 rk_iommu_read(void __iomem *base, u32 offset)
 339{
 340        return readl(base + offset);
 341}
 342
 343static void rk_iommu_write(void __iomem *base, u32 offset, u32 value)
 344{
 345        writel(value, base + offset);
 346}
 347
 348static void rk_iommu_command(struct rk_iommu *iommu, u32 command)
 349{
 350        int i;
 351
 352        for (i = 0; i < iommu->num_mmu; i++)
 353                writel(command, iommu->bases[i] + RK_MMU_COMMAND);
 354}
 355
 356static void rk_iommu_base_command(void __iomem *base, u32 command)
 357{
 358        writel(command, base + RK_MMU_COMMAND);
 359}
 360static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start,
 361                               size_t size)
 362{
 363        int i;
 364        dma_addr_t iova_end = iova_start + size;
 365        /*
 366         * TODO(djkurtz): Figure out when it is more efficient to shootdown the
 367         * entire iotlb rather than iterate over individual iovas.
 368         */
 369        for (i = 0; i < iommu->num_mmu; i++) {
 370                dma_addr_t iova;
 371
 372                for (iova = iova_start; iova < iova_end; iova += SPAGE_SIZE)
 373                        rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova);
 374        }
 375}
 376
 377static bool rk_iommu_is_stall_active(struct rk_iommu *iommu)
 378{
 379        bool active = true;
 380        int i;
 381
 382        for (i = 0; i < iommu->num_mmu; i++)
 383                active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
 384                                           RK_MMU_STATUS_STALL_ACTIVE);
 385
 386        return active;
 387}
 388
 389static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu)
 390{
 391        bool enable = true;
 392        int i;
 393
 394        for (i = 0; i < iommu->num_mmu; i++)
 395                enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) &
 396                                           RK_MMU_STATUS_PAGING_ENABLED);
 397
 398        return enable;
 399}
 400
 401static bool rk_iommu_is_reset_done(struct rk_iommu *iommu)
 402{
 403        bool done = true;
 404        int i;
 405
 406        for (i = 0; i < iommu->num_mmu; i++)
 407                done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0;
 408
 409        return done;
 410}
 411
 412static int rk_iommu_enable_stall(struct rk_iommu *iommu)
 413{
 414        int ret, i;
 415        bool val;
 416
 417        if (rk_iommu_is_stall_active(iommu))
 418                return 0;
 419
 420        /* Stall can only be enabled if paging is enabled */
 421        if (!rk_iommu_is_paging_enabled(iommu))
 422                return 0;
 423
 424        rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL);
 425
 426        ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
 427                                 val, RK_MMU_POLL_PERIOD_US,
 428                                 RK_MMU_POLL_TIMEOUT_US);
 429        if (ret)
 430                for (i = 0; i < iommu->num_mmu; i++)
 431                        dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n",
 432                                rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
 433
 434        return ret;
 435}
 436
 437static int rk_iommu_disable_stall(struct rk_iommu *iommu)
 438{
 439        int ret, i;
 440        bool val;
 441
 442        if (!rk_iommu_is_stall_active(iommu))
 443                return 0;
 444
 445        rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL);
 446
 447        ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val,
 448                                 !val, RK_MMU_POLL_PERIOD_US,
 449                                 RK_MMU_POLL_TIMEOUT_US);
 450        if (ret)
 451                for (i = 0; i < iommu->num_mmu; i++)
 452                        dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n",
 453                                rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
 454
 455        return ret;
 456}
 457
 458static int rk_iommu_enable_paging(struct rk_iommu *iommu)
 459{
 460        int ret, i;
 461        bool val;
 462
 463        if (rk_iommu_is_paging_enabled(iommu))
 464                return 0;
 465
 466        rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING);
 467
 468        ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
 469                                 val, RK_MMU_POLL_PERIOD_US,
 470                                 RK_MMU_POLL_TIMEOUT_US);
 471        if (ret)
 472                for (i = 0; i < iommu->num_mmu; i++)
 473                        dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n",
 474                                rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
 475
 476        return ret;
 477}
 478
 479static int rk_iommu_disable_paging(struct rk_iommu *iommu)
 480{
 481        int ret, i;
 482        bool val;
 483
 484        if (!rk_iommu_is_paging_enabled(iommu))
 485                return 0;
 486
 487        rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING);
 488
 489        ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val,
 490                                 !val, RK_MMU_POLL_PERIOD_US,
 491                                 RK_MMU_POLL_TIMEOUT_US);
 492        if (ret)
 493                for (i = 0; i < iommu->num_mmu; i++)
 494                        dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n",
 495                                rk_iommu_read(iommu->bases[i], RK_MMU_STATUS));
 496
 497        return ret;
 498}
 499
 500static int rk_iommu_force_reset(struct rk_iommu *iommu)
 501{
 502        int ret, i;
 503        u32 dte_addr;
 504        bool val;
 505
 506        if (iommu->reset_disabled)
 507                return 0;
 508
 509        /*
 510         * Check if register DTE_ADDR is working by writing DTE_ADDR_DUMMY
 511         * and verifying that upper 5 nybbles are read back.
 512         */
 513        for (i = 0; i < iommu->num_mmu; i++) {
 514                dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY);
 515                rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr);
 516
 517                if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) {
 518                        dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n");
 519                        return -EFAULT;
 520                }
 521        }
 522
 523        rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET);
 524
 525        ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val,
 526                                 val, RK_MMU_FORCE_RESET_TIMEOUT_US,
 527                                 RK_MMU_POLL_TIMEOUT_US);
 528        if (ret) {
 529                dev_err(iommu->dev, "FORCE_RESET command timed out\n");
 530                return ret;
 531        }
 532
 533        return 0;
 534}
 535
 536static inline phys_addr_t rk_dte_addr_phys(u32 addr)
 537{
 538        return (phys_addr_t)addr;
 539}
 540
 541static inline u32 rk_dma_addr_dte(dma_addr_t dt_dma)
 542{
 543        return dt_dma;
 544}
 545
 546#define DT_HI_MASK GENMASK_ULL(39, 32)
 547#define DTE_BASE_HI_MASK GENMASK(11, 4)
 548#define DT_SHIFT   28
 549
 550static inline phys_addr_t rk_dte_addr_phys_v2(u32 addr)
 551{
 552        u64 addr64 = addr;
 553        return (phys_addr_t)(addr64 & RK_DTE_PT_ADDRESS_MASK) |
 554               ((addr64 & DTE_BASE_HI_MASK) << DT_SHIFT);
 555}
 556
 557static inline u32 rk_dma_addr_dte_v2(dma_addr_t dt_dma)
 558{
 559        return (dt_dma & RK_DTE_PT_ADDRESS_MASK) |
 560               ((dt_dma & DT_HI_MASK) >> DT_SHIFT);
 561}
 562
 563static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
 564{
 565        void __iomem *base = iommu->bases[index];
 566        u32 dte_index, pte_index, page_offset;
 567        u32 mmu_dte_addr;
 568        phys_addr_t mmu_dte_addr_phys, dte_addr_phys;
 569        u32 *dte_addr;
 570        u32 dte;
 571        phys_addr_t pte_addr_phys = 0;
 572        u32 *pte_addr = NULL;
 573        u32 pte = 0;
 574        phys_addr_t page_addr_phys = 0;
 575        u32 page_flags = 0;
 576
 577        dte_index = rk_iova_dte_index(iova);
 578        pte_index = rk_iova_pte_index(iova);
 579        page_offset = rk_iova_page_offset(iova);
 580
 581        mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
 582        mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr);
 583
 584        dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
 585        dte_addr = phys_to_virt(dte_addr_phys);
 586        dte = *dte_addr;
 587
 588        if (!rk_dte_is_pt_valid(dte))
 589                goto print_it;
 590
 591        pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4);
 592        pte_addr = phys_to_virt(pte_addr_phys);
 593        pte = *pte_addr;
 594
 595        if (!rk_pte_is_page_valid(pte))
 596                goto print_it;
 597
 598        page_addr_phys = rk_ops->pt_address(pte) + page_offset;
 599        page_flags = pte & RK_PTE_PAGE_FLAGS_MASK;
 600
 601print_it:
 602        dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n",
 603                &iova, dte_index, pte_index, page_offset);
 604        dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa flags: %#03x\n",
 605                &mmu_dte_addr_phys, &dte_addr_phys, dte,
 606                rk_dte_is_pt_valid(dte), &pte_addr_phys, pte,
 607                rk_pte_is_page_valid(pte), &page_addr_phys, page_flags);
 608}
 609
 610static irqreturn_t rk_iommu_irq(int irq, void *dev_id)
 611{
 612        struct rk_iommu *iommu = dev_id;
 613        u32 status;
 614        u32 int_status;
 615        dma_addr_t iova;
 616        irqreturn_t ret = IRQ_NONE;
 617        int i, err;
 618
 619        err = pm_runtime_get_if_in_use(iommu->dev);
 620        if (!err || WARN_ON_ONCE(err < 0))
 621                return ret;
 622
 623        if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)))
 624                goto out;
 625
 626        for (i = 0; i < iommu->num_mmu; i++) {
 627                int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS);
 628                if (int_status == 0)
 629                        continue;
 630
 631                ret = IRQ_HANDLED;
 632                iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR);
 633
 634                if (int_status & RK_MMU_IRQ_PAGE_FAULT) {
 635                        int flags;
 636
 637                        status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS);
 638                        flags = (status & RK_MMU_STATUS_PAGE_FAULT_IS_WRITE) ?
 639                                        IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
 640
 641                        dev_err(iommu->dev, "Page fault at %pad of type %s\n",
 642                                &iova,
 643                                (flags == IOMMU_FAULT_WRITE) ? "write" : "read");
 644
 645                        log_iova(iommu, i, iova);
 646
 647                        /*
 648                         * Report page fault to any installed handlers.
 649                         * Ignore the return code, though, since we always zap cache
 650                         * and clear the page fault anyway.
 651                         */
 652                        if (iommu->domain)
 653                                report_iommu_fault(iommu->domain, iommu->dev, iova,
 654                                                   flags);
 655                        else
 656                                dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n");
 657
 658                        rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
 659                        rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE);
 660                }
 661
 662                if (int_status & RK_MMU_IRQ_BUS_ERROR)
 663                        dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova);
 664
 665                if (int_status & ~RK_MMU_IRQ_MASK)
 666                        dev_err(iommu->dev, "unexpected int_status: %#08x\n",
 667                                int_status);
 668
 669                rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status);
 670        }
 671
 672        clk_bulk_disable(iommu->num_clocks, iommu->clocks);
 673
 674out:
 675        pm_runtime_put(iommu->dev);
 676        return ret;
 677}
 678
 679static phys_addr_t rk_iommu_iova_to_phys(struct iommu_domain *domain,
 680                                         dma_addr_t iova)
 681{
 682        struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
 683        unsigned long flags;
 684        phys_addr_t pt_phys, phys = 0;
 685        u32 dte, pte;
 686        u32 *page_table;
 687
 688        spin_lock_irqsave(&rk_domain->dt_lock, flags);
 689
 690        dte = rk_domain->dt[rk_iova_dte_index(iova)];
 691        if (!rk_dte_is_pt_valid(dte))
 692                goto out;
 693
 694        pt_phys = rk_ops->pt_address(dte);
 695        page_table = (u32 *)phys_to_virt(pt_phys);
 696        pte = page_table[rk_iova_pte_index(iova)];
 697        if (!rk_pte_is_page_valid(pte))
 698                goto out;
 699
 700        phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova);
 701out:
 702        spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
 703
 704        return phys;
 705}
 706
 707static void rk_iommu_zap_iova(struct rk_iommu_domain *rk_domain,
 708                              dma_addr_t iova, size_t size)
 709{
 710        struct list_head *pos;
 711        unsigned long flags;
 712
 713        /* shootdown these iova from all iommus using this domain */
 714        spin_lock_irqsave(&rk_domain->iommus_lock, flags);
 715        list_for_each(pos, &rk_domain->iommus) {
 716                struct rk_iommu *iommu;
 717                int ret;
 718
 719                iommu = list_entry(pos, struct rk_iommu, node);
 720
 721                /* Only zap TLBs of IOMMUs that are powered on. */
 722                ret = pm_runtime_get_if_in_use(iommu->dev);
 723                if (WARN_ON_ONCE(ret < 0))
 724                        continue;
 725                if (ret) {
 726                        WARN_ON(clk_bulk_enable(iommu->num_clocks,
 727                                                iommu->clocks));
 728                        rk_iommu_zap_lines(iommu, iova, size);
 729                        clk_bulk_disable(iommu->num_clocks, iommu->clocks);
 730                        pm_runtime_put(iommu->dev);
 731                }
 732        }
 733        spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
 734}
 735
 736static void rk_iommu_zap_iova_first_last(struct rk_iommu_domain *rk_domain,
 737                                         dma_addr_t iova, size_t size)
 738{
 739        rk_iommu_zap_iova(rk_domain, iova, SPAGE_SIZE);
 740        if (size > SPAGE_SIZE)
 741                rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE,
 742                                        SPAGE_SIZE);
 743}
 744
 745static u32 *rk_dte_get_page_table(struct rk_iommu_domain *rk_domain,
 746                                  dma_addr_t iova)
 747{
 748        u32 *page_table, *dte_addr;
 749        u32 dte_index, dte;
 750        phys_addr_t pt_phys;
 751        dma_addr_t pt_dma;
 752
 753        assert_spin_locked(&rk_domain->dt_lock);
 754
 755        dte_index = rk_iova_dte_index(iova);
 756        dte_addr = &rk_domain->dt[dte_index];
 757        dte = *dte_addr;
 758        if (rk_dte_is_pt_valid(dte))
 759                goto done;
 760
 761        page_table = (u32 *)get_zeroed_page(GFP_ATOMIC | GFP_DMA32);
 762        if (!page_table)
 763                return ERR_PTR(-ENOMEM);
 764
 765        pt_dma = dma_map_single(dma_dev, page_table, SPAGE_SIZE, DMA_TO_DEVICE);
 766        if (dma_mapping_error(dma_dev, pt_dma)) {
 767                dev_err(dma_dev, "DMA mapping error while allocating page table\n");
 768                free_page((unsigned long)page_table);
 769                return ERR_PTR(-ENOMEM);
 770        }
 771
 772        dte = rk_ops->mk_dtentries(pt_dma);
 773        *dte_addr = dte;
 774
 775        rk_table_flush(rk_domain,
 776                       rk_domain->dt_dma + dte_index * sizeof(u32), 1);
 777done:
 778        pt_phys = rk_ops->pt_address(dte);
 779        return (u32 *)phys_to_virt(pt_phys);
 780}
 781
 782static size_t rk_iommu_unmap_iova(struct rk_iommu_domain *rk_domain,
 783                                  u32 *pte_addr, dma_addr_t pte_dma,
 784                                  size_t size)
 785{
 786        unsigned int pte_count;
 787        unsigned int pte_total = size / SPAGE_SIZE;
 788
 789        assert_spin_locked(&rk_domain->dt_lock);
 790
 791        for (pte_count = 0; pte_count < pte_total; pte_count++) {
 792                u32 pte = pte_addr[pte_count];
 793                if (!rk_pte_is_page_valid(pte))
 794                        break;
 795
 796                pte_addr[pte_count] = rk_mk_pte_invalid(pte);
 797        }
 798
 799        rk_table_flush(rk_domain, pte_dma, pte_count);
 800
 801        return pte_count * SPAGE_SIZE;
 802}
 803
 804static int rk_iommu_map_iova(struct rk_iommu_domain *rk_domain, u32 *pte_addr,
 805                             dma_addr_t pte_dma, dma_addr_t iova,
 806                             phys_addr_t paddr, size_t size, int prot)
 807{
 808        unsigned int pte_count;
 809        unsigned int pte_total = size / SPAGE_SIZE;
 810        phys_addr_t page_phys;
 811
 812        assert_spin_locked(&rk_domain->dt_lock);
 813
 814        for (pte_count = 0; pte_count < pte_total; pte_count++) {
 815                u32 pte = pte_addr[pte_count];
 816
 817                if (rk_pte_is_page_valid(pte))
 818                        goto unwind;
 819
 820                pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot);
 821
 822                paddr += SPAGE_SIZE;
 823        }
 824
 825        rk_table_flush(rk_domain, pte_dma, pte_total);
 826
 827        /*
 828         * Zap the first and last iova to evict from iotlb any previously
 829         * mapped cachelines holding stale values for its dte and pte.
 830         * We only zap the first and last iova, since only they could have
 831         * dte or pte shared with an existing mapping.
 832         */
 833        rk_iommu_zap_iova_first_last(rk_domain, iova, size);
 834
 835        return 0;
 836unwind:
 837        /* Unmap the range of iovas that we just mapped */
 838        rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma,
 839                            pte_count * SPAGE_SIZE);
 840
 841        iova += pte_count * SPAGE_SIZE;
 842        page_phys = rk_ops->pt_address(pte_addr[pte_count]);
 843        pr_err("iova: %pad already mapped to %pa cannot remap to phys: %pa prot: %#x\n",
 844               &iova, &page_phys, &paddr, prot);
 845
 846        return -EADDRINUSE;
 847}
 848
 849static int rk_iommu_map(struct iommu_domain *domain, unsigned long _iova,
 850                        phys_addr_t paddr, size_t size, int prot, gfp_t gfp)
 851{
 852        struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
 853        unsigned long flags;
 854        dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
 855        u32 *page_table, *pte_addr;
 856        u32 dte_index, pte_index;
 857        int ret;
 858
 859        spin_lock_irqsave(&rk_domain->dt_lock, flags);
 860
 861        /*
 862         * pgsize_bitmap specifies iova sizes that fit in one page table
 863         * (1024 4-KiB pages = 4 MiB).
 864         * So, size will always be 4096 <= size <= 4194304.
 865         * Since iommu_map() guarantees that both iova and size will be
 866         * aligned, we will always only be mapping from a single dte here.
 867         */
 868        page_table = rk_dte_get_page_table(rk_domain, iova);
 869        if (IS_ERR(page_table)) {
 870                spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
 871                return PTR_ERR(page_table);
 872        }
 873
 874        dte_index = rk_domain->dt[rk_iova_dte_index(iova)];
 875        pte_index = rk_iova_pte_index(iova);
 876        pte_addr = &page_table[pte_index];
 877
 878        pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32);
 879        ret = rk_iommu_map_iova(rk_domain, pte_addr, pte_dma, iova,
 880                                paddr, size, prot);
 881
 882        spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
 883
 884        return ret;
 885}
 886
 887static size_t rk_iommu_unmap(struct iommu_domain *domain, unsigned long _iova,
 888                             size_t size, struct iommu_iotlb_gather *gather)
 889{
 890        struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
 891        unsigned long flags;
 892        dma_addr_t pte_dma, iova = (dma_addr_t)_iova;
 893        phys_addr_t pt_phys;
 894        u32 dte;
 895        u32 *pte_addr;
 896        size_t unmap_size;
 897
 898        spin_lock_irqsave(&rk_domain->dt_lock, flags);
 899
 900        /*
 901         * pgsize_bitmap specifies iova sizes that fit in one page table
 902         * (1024 4-KiB pages = 4 MiB).
 903         * So, size will always be 4096 <= size <= 4194304.
 904         * Since iommu_unmap() guarantees that both iova and size will be
 905         * aligned, we will always only be unmapping from a single dte here.
 906         */
 907        dte = rk_domain->dt[rk_iova_dte_index(iova)];
 908        /* Just return 0 if iova is unmapped */
 909        if (!rk_dte_is_pt_valid(dte)) {
 910                spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
 911                return 0;
 912        }
 913
 914        pt_phys = rk_ops->pt_address(dte);
 915        pte_addr = (u32 *)phys_to_virt(pt_phys) + rk_iova_pte_index(iova);
 916        pte_dma = pt_phys + rk_iova_pte_index(iova) * sizeof(u32);
 917        unmap_size = rk_iommu_unmap_iova(rk_domain, pte_addr, pte_dma, size);
 918
 919        spin_unlock_irqrestore(&rk_domain->dt_lock, flags);
 920
 921        /* Shootdown iotlb entries for iova range that was just unmapped */
 922        rk_iommu_zap_iova(rk_domain, iova, unmap_size);
 923
 924        return unmap_size;
 925}
 926
 927static struct rk_iommu *rk_iommu_from_dev(struct device *dev)
 928{
 929        struct rk_iommudata *data = dev_iommu_priv_get(dev);
 930
 931        return data ? data->iommu : NULL;
 932}
 933
 934/* Must be called with iommu powered on and attached */
 935static void rk_iommu_disable(struct rk_iommu *iommu)
 936{
 937        int i;
 938
 939        /* Ignore error while disabling, just keep going */
 940        WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks));
 941        rk_iommu_enable_stall(iommu);
 942        rk_iommu_disable_paging(iommu);
 943        for (i = 0; i < iommu->num_mmu; i++) {
 944                rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
 945                rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0);
 946        }
 947        rk_iommu_disable_stall(iommu);
 948        clk_bulk_disable(iommu->num_clocks, iommu->clocks);
 949}
 950
 951/* Must be called with iommu powered on and attached */
 952static int rk_iommu_enable(struct rk_iommu *iommu)
 953{
 954        struct iommu_domain *domain = iommu->domain;
 955        struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
 956        int ret, i;
 957
 958        ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks);
 959        if (ret)
 960                return ret;
 961
 962        ret = rk_iommu_enable_stall(iommu);
 963        if (ret)
 964                goto out_disable_clocks;
 965
 966        ret = rk_iommu_force_reset(iommu);
 967        if (ret)
 968                goto out_disable_stall;
 969
 970        for (i = 0; i < iommu->num_mmu; i++) {
 971                rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
 972                               rk_ops->dma_addr_dte(rk_domain->dt_dma));
 973                rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
 974                rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
 975        }
 976
 977        ret = rk_iommu_enable_paging(iommu);
 978
 979out_disable_stall:
 980        rk_iommu_disable_stall(iommu);
 981out_disable_clocks:
 982        clk_bulk_disable(iommu->num_clocks, iommu->clocks);
 983        return ret;
 984}
 985
 986static void rk_iommu_detach_device(struct iommu_domain *domain,
 987                                   struct device *dev)
 988{
 989        struct rk_iommu *iommu;
 990        struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
 991        unsigned long flags;
 992        int ret;
 993
 994        /* Allow 'virtual devices' (eg drm) to detach from domain */
 995        iommu = rk_iommu_from_dev(dev);
 996        if (!iommu)
 997                return;
 998
 999        dev_dbg(dev, "Detaching from iommu domain\n");
1000
1001        /* iommu already detached */
1002        if (iommu->domain != domain)
1003                return;
1004
1005        iommu->domain = NULL;
1006
1007        spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1008        list_del_init(&iommu->node);
1009        spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1010
1011        ret = pm_runtime_get_if_in_use(iommu->dev);
1012        WARN_ON_ONCE(ret < 0);
1013        if (ret > 0) {
1014                rk_iommu_disable(iommu);
1015                pm_runtime_put(iommu->dev);
1016        }
1017}
1018
1019static int rk_iommu_attach_device(struct iommu_domain *domain,
1020                struct device *dev)
1021{
1022        struct rk_iommu *iommu;
1023        struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1024        unsigned long flags;
1025        int ret;
1026
1027        /*
1028         * Allow 'virtual devices' (e.g., drm) to attach to domain.
1029         * Such a device does not belong to an iommu group.
1030         */
1031        iommu = rk_iommu_from_dev(dev);
1032        if (!iommu)
1033                return 0;
1034
1035        dev_dbg(dev, "Attaching to iommu domain\n");
1036
1037        /* iommu already attached */
1038        if (iommu->domain == domain)
1039                return 0;
1040
1041        if (iommu->domain)
1042                rk_iommu_detach_device(iommu->domain, dev);
1043
1044        iommu->domain = domain;
1045
1046        spin_lock_irqsave(&rk_domain->iommus_lock, flags);
1047        list_add_tail(&iommu->node, &rk_domain->iommus);
1048        spin_unlock_irqrestore(&rk_domain->iommus_lock, flags);
1049
1050        ret = pm_runtime_get_if_in_use(iommu->dev);
1051        if (!ret || WARN_ON_ONCE(ret < 0))
1052                return 0;
1053
1054        ret = rk_iommu_enable(iommu);
1055        if (ret)
1056                rk_iommu_detach_device(iommu->domain, dev);
1057
1058        pm_runtime_put(iommu->dev);
1059
1060        return ret;
1061}
1062
1063static struct iommu_domain *rk_iommu_domain_alloc(unsigned type)
1064{
1065        struct rk_iommu_domain *rk_domain;
1066
1067        if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
1068                return NULL;
1069
1070        if (!dma_dev)
1071                return NULL;
1072
1073        rk_domain = kzalloc(sizeof(*rk_domain), GFP_KERNEL);
1074        if (!rk_domain)
1075                return NULL;
1076
1077        if (type == IOMMU_DOMAIN_DMA &&
1078            iommu_get_dma_cookie(&rk_domain->domain))
1079                goto err_free_domain;
1080
1081        /*
1082         * rk32xx iommus use a 2 level pagetable.
1083         * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries.
1084         * Allocate one 4 KiB page for each table.
1085         */
1086        rk_domain->dt = (u32 *)get_zeroed_page(GFP_KERNEL | GFP_DMA32);
1087        if (!rk_domain->dt)
1088                goto err_put_cookie;
1089
1090        rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt,
1091                                           SPAGE_SIZE, DMA_TO_DEVICE);
1092        if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) {
1093                dev_err(dma_dev, "DMA map error for DT\n");
1094                goto err_free_dt;
1095        }
1096
1097        spin_lock_init(&rk_domain->iommus_lock);
1098        spin_lock_init(&rk_domain->dt_lock);
1099        INIT_LIST_HEAD(&rk_domain->iommus);
1100
1101        rk_domain->domain.geometry.aperture_start = 0;
1102        rk_domain->domain.geometry.aperture_end   = DMA_BIT_MASK(32);
1103        rk_domain->domain.geometry.force_aperture = true;
1104
1105        return &rk_domain->domain;
1106
1107err_free_dt:
1108        free_page((unsigned long)rk_domain->dt);
1109err_put_cookie:
1110        if (type == IOMMU_DOMAIN_DMA)
1111                iommu_put_dma_cookie(&rk_domain->domain);
1112err_free_domain:
1113        kfree(rk_domain);
1114
1115        return NULL;
1116}
1117
1118static void rk_iommu_domain_free(struct iommu_domain *domain)
1119{
1120        struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
1121        int i;
1122
1123        WARN_ON(!list_empty(&rk_domain->iommus));
1124
1125        for (i = 0; i < NUM_DT_ENTRIES; i++) {
1126                u32 dte = rk_domain->dt[i];
1127                if (rk_dte_is_pt_valid(dte)) {
1128                        phys_addr_t pt_phys = rk_ops->pt_address(dte);
1129                        u32 *page_table = phys_to_virt(pt_phys);
1130                        dma_unmap_single(dma_dev, pt_phys,
1131                                         SPAGE_SIZE, DMA_TO_DEVICE);
1132                        free_page((unsigned long)page_table);
1133                }
1134        }
1135
1136        dma_unmap_single(dma_dev, rk_domain->dt_dma,
1137                         SPAGE_SIZE, DMA_TO_DEVICE);
1138        free_page((unsigned long)rk_domain->dt);
1139
1140        if (domain->type == IOMMU_DOMAIN_DMA)
1141                iommu_put_dma_cookie(&rk_domain->domain);
1142        kfree(rk_domain);
1143}
1144
1145static struct iommu_device *rk_iommu_probe_device(struct device *dev)
1146{
1147        struct rk_iommudata *data;
1148        struct rk_iommu *iommu;
1149
1150        data = dev_iommu_priv_get(dev);
1151        if (!data)
1152                return ERR_PTR(-ENODEV);
1153
1154        iommu = rk_iommu_from_dev(dev);
1155
1156        data->link = device_link_add(dev, iommu->dev,
1157                                     DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
1158
1159        return &iommu->iommu;
1160}
1161
1162static void rk_iommu_release_device(struct device *dev)
1163{
1164        struct rk_iommudata *data = dev_iommu_priv_get(dev);
1165
1166        device_link_del(data->link);
1167}
1168
1169static struct iommu_group *rk_iommu_device_group(struct device *dev)
1170{
1171        struct rk_iommu *iommu;
1172
1173        iommu = rk_iommu_from_dev(dev);
1174
1175        return iommu_group_ref_get(iommu->group);
1176}
1177
1178static int rk_iommu_of_xlate(struct device *dev,
1179                             struct of_phandle_args *args)
1180{
1181        struct platform_device *iommu_dev;
1182        struct rk_iommudata *data;
1183
1184        data = devm_kzalloc(dma_dev, sizeof(*data), GFP_KERNEL);
1185        if (!data)
1186                return -ENOMEM;
1187
1188        iommu_dev = of_find_device_by_node(args->np);
1189
1190        data->iommu = platform_get_drvdata(iommu_dev);
1191        dev_iommu_priv_set(dev, data);
1192
1193        platform_device_put(iommu_dev);
1194
1195        return 0;
1196}
1197
1198static const struct iommu_ops rk_iommu_ops = {
1199        .domain_alloc = rk_iommu_domain_alloc,
1200        .domain_free = rk_iommu_domain_free,
1201        .attach_dev = rk_iommu_attach_device,
1202        .detach_dev = rk_iommu_detach_device,
1203        .map = rk_iommu_map,
1204        .unmap = rk_iommu_unmap,
1205        .probe_device = rk_iommu_probe_device,
1206        .release_device = rk_iommu_release_device,
1207        .iova_to_phys = rk_iommu_iova_to_phys,
1208        .device_group = rk_iommu_device_group,
1209        .pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
1210        .of_xlate = rk_iommu_of_xlate,
1211};
1212
1213static int rk_iommu_probe(struct platform_device *pdev)
1214{
1215        struct device *dev = &pdev->dev;
1216        struct rk_iommu *iommu;
1217        struct resource *res;
1218        const struct rk_iommu_ops *ops;
1219        int num_res = pdev->num_resources;
1220        int err, i;
1221
1222        iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
1223        if (!iommu)
1224                return -ENOMEM;
1225
1226        platform_set_drvdata(pdev, iommu);
1227        iommu->dev = dev;
1228        iommu->num_mmu = 0;
1229
1230        ops = of_device_get_match_data(dev);
1231        if (!rk_ops)
1232                rk_ops = ops;
1233
1234        /*
1235         * That should not happen unless different versions of the
1236         * hardware block are embedded the same SoC
1237         */
1238        if (WARN_ON(rk_ops != ops))
1239                return -EINVAL;
1240
1241        iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases),
1242                                    GFP_KERNEL);
1243        if (!iommu->bases)
1244                return -ENOMEM;
1245
1246        for (i = 0; i < num_res; i++) {
1247                res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1248                if (!res)
1249                        continue;
1250                iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res);
1251                if (IS_ERR(iommu->bases[i]))
1252                        continue;
1253                iommu->num_mmu++;
1254        }
1255        if (iommu->num_mmu == 0)
1256                return PTR_ERR(iommu->bases[0]);
1257
1258        iommu->num_irq = platform_irq_count(pdev);
1259        if (iommu->num_irq < 0)
1260                return iommu->num_irq;
1261
1262        iommu->reset_disabled = device_property_read_bool(dev,
1263                                        "rockchip,disable-mmu-reset");
1264
1265        iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks);
1266        iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks,
1267                                     sizeof(*iommu->clocks), GFP_KERNEL);
1268        if (!iommu->clocks)
1269                return -ENOMEM;
1270
1271        for (i = 0; i < iommu->num_clocks; ++i)
1272                iommu->clocks[i].id = rk_iommu_clocks[i];
1273
1274        /*
1275         * iommu clocks should be present for all new devices and devicetrees
1276         * but there are older devicetrees without clocks out in the wild.
1277         * So clocks as optional for the time being.
1278         */
1279        err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks);
1280        if (err == -ENOENT)
1281                iommu->num_clocks = 0;
1282        else if (err)
1283                return err;
1284
1285        err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks);
1286        if (err)
1287                return err;
1288
1289        iommu->group = iommu_group_alloc();
1290        if (IS_ERR(iommu->group)) {
1291                err = PTR_ERR(iommu->group);
1292                goto err_unprepare_clocks;
1293        }
1294
1295        err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev));
1296        if (err)
1297                goto err_put_group;
1298
1299        err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev);
1300        if (err)
1301                goto err_remove_sysfs;
1302
1303        /*
1304         * Use the first registered IOMMU device for domain to use with DMA
1305         * API, since a domain might not physically correspond to a single
1306         * IOMMU device..
1307         */
1308        if (!dma_dev)
1309                dma_dev = &pdev->dev;
1310
1311        bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
1312
1313        pm_runtime_enable(dev);
1314
1315        for (i = 0; i < iommu->num_irq; i++) {
1316                int irq = platform_get_irq(pdev, i);
1317
1318                if (irq < 0)
1319                        return irq;
1320
1321                err = devm_request_irq(iommu->dev, irq, rk_iommu_irq,
1322                                       IRQF_SHARED, dev_name(dev), iommu);
1323                if (err) {
1324                        pm_runtime_disable(dev);
1325                        goto err_remove_sysfs;
1326                }
1327        }
1328
1329        dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask);
1330
1331        return 0;
1332err_remove_sysfs:
1333        iommu_device_sysfs_remove(&iommu->iommu);
1334err_put_group:
1335        iommu_group_put(iommu->group);
1336err_unprepare_clocks:
1337        clk_bulk_unprepare(iommu->num_clocks, iommu->clocks);
1338        return err;
1339}
1340
1341static void rk_iommu_shutdown(struct platform_device *pdev)
1342{
1343        struct rk_iommu *iommu = platform_get_drvdata(pdev);
1344        int i;
1345
1346        for (i = 0; i < iommu->num_irq; i++) {
1347                int irq = platform_get_irq(pdev, i);
1348
1349                devm_free_irq(iommu->dev, irq, iommu);
1350        }
1351
1352        pm_runtime_force_suspend(&pdev->dev);
1353}
1354
1355static int __maybe_unused rk_iommu_suspend(struct device *dev)
1356{
1357        struct rk_iommu *iommu = dev_get_drvdata(dev);
1358
1359        if (!iommu->domain)
1360                return 0;
1361
1362        rk_iommu_disable(iommu);
1363        return 0;
1364}
1365
1366static int __maybe_unused rk_iommu_resume(struct device *dev)
1367{
1368        struct rk_iommu *iommu = dev_get_drvdata(dev);
1369
1370        if (!iommu->domain)
1371                return 0;
1372
1373        return rk_iommu_enable(iommu);
1374}
1375
1376static const struct dev_pm_ops rk_iommu_pm_ops = {
1377        SET_RUNTIME_PM_OPS(rk_iommu_suspend, rk_iommu_resume, NULL)
1378        SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1379                                pm_runtime_force_resume)
1380};
1381
1382static struct rk_iommu_ops iommu_data_ops_v1 = {
1383        .pt_address = &rk_dte_pt_address,
1384        .mk_dtentries = &rk_mk_dte,
1385        .mk_ptentries = &rk_mk_pte,
1386        .dte_addr_phys = &rk_dte_addr_phys,
1387        .dma_addr_dte = &rk_dma_addr_dte,
1388        .dma_bit_mask = DMA_BIT_MASK(32),
1389};
1390
1391static struct rk_iommu_ops iommu_data_ops_v2 = {
1392        .pt_address = &rk_dte_pt_address_v2,
1393        .mk_dtentries = &rk_mk_dte_v2,
1394        .mk_ptentries = &rk_mk_pte_v2,
1395        .dte_addr_phys = &rk_dte_addr_phys_v2,
1396        .dma_addr_dte = &rk_dma_addr_dte_v2,
1397        .dma_bit_mask = DMA_BIT_MASK(40),
1398};
1399
1400static const struct of_device_id rk_iommu_dt_ids[] = {
1401        {       .compatible = "rockchip,iommu",
1402                .data = &iommu_data_ops_v1,
1403        },
1404        {       .compatible = "rockchip,rk3568-iommu",
1405                .data = &iommu_data_ops_v2,
1406        },
1407        { /* sentinel */ }
1408};
1409
1410static struct platform_driver rk_iommu_driver = {
1411        .probe = rk_iommu_probe,
1412        .shutdown = rk_iommu_shutdown,
1413        .driver = {
1414                   .name = "rk_iommu",
1415                   .of_match_table = rk_iommu_dt_ids,
1416                   .pm = &rk_iommu_pm_ops,
1417                   .suppress_bind_attrs = true,
1418        },
1419};
1420
1421static int __init rk_iommu_init(void)
1422{
1423        return platform_driver_register(&rk_iommu_driver);
1424}
1425subsys_initcall(rk_iommu_init);
1426