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48#include <linux/io.h>
49#include <rdma/rdma_vt.h>
50#include <rdma/rdmavt_qp.h>
51
52#include "hfi.h"
53#include "qp.h"
54#include "rc.h"
55#include "verbs_txreq.h"
56#include "trace.h"
57
58struct rvt_ack_entry *find_prev_entry(struct rvt_qp *qp, u32 psn, u8 *prev,
59 u8 *prev_ack, bool *scheduled)
60 __must_hold(&qp->s_lock)
61{
62 struct rvt_ack_entry *e = NULL;
63 u8 i, p;
64 bool s = true;
65
66 for (i = qp->r_head_ack_queue; ; i = p) {
67 if (i == qp->s_tail_ack_queue)
68 s = false;
69 if (i)
70 p = i - 1;
71 else
72 p = rvt_size_atomic(ib_to_rvt(qp->ibqp.device));
73 if (p == qp->r_head_ack_queue) {
74 e = NULL;
75 break;
76 }
77 e = &qp->s_ack_queue[p];
78 if (!e->opcode) {
79 e = NULL;
80 break;
81 }
82 if (cmp_psn(psn, e->psn) >= 0) {
83 if (p == qp->s_tail_ack_queue &&
84 cmp_psn(psn, e->lpsn) <= 0)
85 s = false;
86 break;
87 }
88 }
89 if (prev)
90 *prev = p;
91 if (prev_ack)
92 *prev_ack = i;
93 if (scheduled)
94 *scheduled = s;
95 return e;
96}
97
98
99
100
101
102
103
104
105
106
107
108
109static int make_rc_ack(struct hfi1_ibdev *dev, struct rvt_qp *qp,
110 struct ib_other_headers *ohdr,
111 struct hfi1_pkt_state *ps)
112{
113 struct rvt_ack_entry *e;
114 u32 hwords, hdrlen;
115 u32 len = 0;
116 u32 bth0 = 0, bth2 = 0;
117 u32 bth1 = qp->remote_qpn | (HFI1_CAP_IS_KSET(OPFN) << IB_BTHE_E_SHIFT);
118 int middle = 0;
119 u32 pmtu = qp->pmtu;
120 struct hfi1_qp_priv *qpriv = qp->priv;
121 bool last_pkt;
122 u32 delta;
123 u8 next = qp->s_tail_ack_queue;
124 struct tid_rdma_request *req;
125
126 trace_hfi1_rsp_make_rc_ack(qp, 0);
127 lockdep_assert_held(&qp->s_lock);
128
129 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK))
130 goto bail;
131
132 if (qpriv->hdr_type == HFI1_PKT_TYPE_9B)
133
134 hwords = 5;
135 else
136
137 hwords = 7;
138
139 switch (qp->s_ack_state) {
140 case OP(RDMA_READ_RESPONSE_LAST):
141 case OP(RDMA_READ_RESPONSE_ONLY):
142 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
143 release_rdma_sge_mr(e);
144 fallthrough;
145 case OP(ATOMIC_ACKNOWLEDGE):
146
147
148
149
150
151 if (++next > rvt_size_atomic(&dev->rdi))
152 next = 0;
153
154
155
156
157 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
158 if (e->opcode != TID_OP(WRITE_REQ) &&
159 qp->s_acked_ack_queue == qp->s_tail_ack_queue)
160 qp->s_acked_ack_queue = next;
161 qp->s_tail_ack_queue = next;
162 trace_hfi1_rsp_make_rc_ack(qp, e->psn);
163 fallthrough;
164 case OP(SEND_ONLY):
165 case OP(ACKNOWLEDGE):
166
167 if (qp->r_head_ack_queue == qp->s_tail_ack_queue) {
168 if (qp->s_flags & RVT_S_ACK_PENDING)
169 goto normal;
170 goto bail;
171 }
172
173 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
174
175 if ((qpriv->s_flags & HFI1_R_TID_WAIT_INTERLCK) ||
176 hfi1_tid_rdma_ack_interlock(qp, e)) {
177 iowait_set_flag(&qpriv->s_iowait, IOWAIT_PENDING_IB);
178 goto bail;
179 }
180 if (e->opcode == OP(RDMA_READ_REQUEST)) {
181
182
183
184
185
186
187 len = e->rdma_sge.sge_length;
188 if (len && !e->rdma_sge.mr) {
189 if (qp->s_acked_ack_queue ==
190 qp->s_tail_ack_queue)
191 qp->s_acked_ack_queue =
192 qp->r_head_ack_queue;
193 qp->s_tail_ack_queue = qp->r_head_ack_queue;
194 goto bail;
195 }
196
197 ps->s_txreq->mr = e->rdma_sge.mr;
198 if (ps->s_txreq->mr)
199 rvt_get_mr(ps->s_txreq->mr);
200 qp->s_ack_rdma_sge.sge = e->rdma_sge;
201 qp->s_ack_rdma_sge.num_sge = 1;
202 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
203 if (len > pmtu) {
204 len = pmtu;
205 qp->s_ack_state = OP(RDMA_READ_RESPONSE_FIRST);
206 } else {
207 qp->s_ack_state = OP(RDMA_READ_RESPONSE_ONLY);
208 e->sent = 1;
209 }
210 ohdr->u.aeth = rvt_compute_aeth(qp);
211 hwords++;
212 qp->s_ack_rdma_psn = e->psn;
213 bth2 = mask_psn(qp->s_ack_rdma_psn++);
214 } else if (e->opcode == TID_OP(WRITE_REQ)) {
215
216
217
218
219
220
221
222 req = ack_to_tid_req(e);
223 if (req->state == TID_REQUEST_RESEND ||
224 req->state == TID_REQUEST_INIT_RESEND)
225 goto bail;
226 qp->s_ack_state = TID_OP(WRITE_RESP);
227 qp->s_ack_rdma_psn = mask_psn(e->psn + req->cur_seg);
228 goto write_resp;
229 } else if (e->opcode == TID_OP(READ_REQ)) {
230
231
232
233
234
235
236 len = e->rdma_sge.sge_length;
237 if (len && !e->rdma_sge.mr) {
238 if (qp->s_acked_ack_queue ==
239 qp->s_tail_ack_queue)
240 qp->s_acked_ack_queue =
241 qp->r_head_ack_queue;
242 qp->s_tail_ack_queue = qp->r_head_ack_queue;
243 goto bail;
244 }
245
246 ps->s_txreq->mr = e->rdma_sge.mr;
247 if (ps->s_txreq->mr)
248 rvt_get_mr(ps->s_txreq->mr);
249 qp->s_ack_rdma_sge.sge = e->rdma_sge;
250 qp->s_ack_rdma_sge.num_sge = 1;
251 qp->s_ack_state = TID_OP(READ_RESP);
252 goto read_resp;
253 } else {
254
255 ps->s_txreq->ss = NULL;
256 len = 0;
257 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
258 ohdr->u.at.aeth = rvt_compute_aeth(qp);
259 ib_u64_put(e->atomic_data, &ohdr->u.at.atomic_ack_eth);
260 hwords += sizeof(ohdr->u.at) / sizeof(u32);
261 bth2 = mask_psn(e->psn);
262 e->sent = 1;
263 }
264 trace_hfi1_tid_write_rsp_make_rc_ack(qp);
265 bth0 = qp->s_ack_state << 24;
266 break;
267
268 case OP(RDMA_READ_RESPONSE_FIRST):
269 qp->s_ack_state = OP(RDMA_READ_RESPONSE_MIDDLE);
270 fallthrough;
271 case OP(RDMA_READ_RESPONSE_MIDDLE):
272 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
273 ps->s_txreq->mr = qp->s_ack_rdma_sge.sge.mr;
274 if (ps->s_txreq->mr)
275 rvt_get_mr(ps->s_txreq->mr);
276 len = qp->s_ack_rdma_sge.sge.sge_length;
277 if (len > pmtu) {
278 len = pmtu;
279 middle = HFI1_CAP_IS_KSET(SDMA_AHG);
280 } else {
281 ohdr->u.aeth = rvt_compute_aeth(qp);
282 hwords++;
283 qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
284 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
285 e->sent = 1;
286 }
287 bth0 = qp->s_ack_state << 24;
288 bth2 = mask_psn(qp->s_ack_rdma_psn++);
289 break;
290
291 case TID_OP(WRITE_RESP):
292write_resp:
293
294
295
296
297
298
299
300
301
302
303
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306
307
308
309
310
311
312 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
313 req = ack_to_tid_req(e);
314
315
316
317
318
319
320 if (qpriv->rnr_nak_state == TID_RNR_NAK_SEND &&
321 qp->s_tail_ack_queue == qpriv->r_tid_alloc &&
322 req->cur_seg == req->alloc_seg) {
323 qpriv->rnr_nak_state = TID_RNR_NAK_SENT;
324 goto normal_no_state;
325 }
326
327 bth2 = mask_psn(qp->s_ack_rdma_psn);
328 hdrlen = hfi1_build_tid_rdma_write_resp(qp, e, ohdr, &bth1,
329 bth2, &len,
330 &ps->s_txreq->ss);
331 if (!hdrlen)
332 return 0;
333
334 hwords += hdrlen;
335 bth0 = qp->s_ack_state << 24;
336 qp->s_ack_rdma_psn++;
337 trace_hfi1_tid_req_make_rc_ack_write(qp, 0, e->opcode, e->psn,
338 e->lpsn, req);
339 if (req->cur_seg != req->total_segs)
340 break;
341
342 e->sent = 1;
343
344 qp->s_ack_state = OP(ATOMIC_ACKNOWLEDGE);
345 break;
346
347 case TID_OP(READ_RESP):
348read_resp:
349 e = &qp->s_ack_queue[qp->s_tail_ack_queue];
350 ps->s_txreq->ss = &qp->s_ack_rdma_sge;
351 delta = hfi1_build_tid_rdma_read_resp(qp, e, ohdr, &bth0,
352 &bth1, &bth2, &len,
353 &last_pkt);
354 if (delta == 0)
355 goto error_qp;
356 hwords += delta;
357 if (last_pkt) {
358 e->sent = 1;
359
360
361
362
363 qp->s_ack_state = OP(RDMA_READ_RESPONSE_LAST);
364 }
365 break;
366 case TID_OP(READ_REQ):
367 goto bail;
368
369 default:
370normal:
371
372
373
374
375
376
377 qp->s_ack_state = OP(SEND_ONLY);
378normal_no_state:
379 if (qp->s_nak_state)
380 ohdr->u.aeth =
381 cpu_to_be32((qp->r_msn & IB_MSN_MASK) |
382 (qp->s_nak_state <<
383 IB_AETH_CREDIT_SHIFT));
384 else
385 ohdr->u.aeth = rvt_compute_aeth(qp);
386 hwords++;
387 len = 0;
388 bth0 = OP(ACKNOWLEDGE) << 24;
389 bth2 = mask_psn(qp->s_ack_psn);
390 qp->s_flags &= ~RVT_S_ACK_PENDING;
391 ps->s_txreq->txreq.flags |= SDMA_TXREQ_F_VIP;
392 ps->s_txreq->ss = NULL;
393 }
394 qp->s_rdma_ack_cnt++;
395 ps->s_txreq->sde = qpriv->s_sde;
396 ps->s_txreq->s_cur_size = len;
397 ps->s_txreq->hdr_dwords = hwords;
398 hfi1_make_ruc_header(qp, ohdr, bth0, bth1, bth2, middle, ps);
399 return 1;
400error_qp:
401 spin_unlock_irqrestore(&qp->s_lock, ps->flags);
402 spin_lock_irqsave(&qp->r_lock, ps->flags);
403 spin_lock(&qp->s_lock);
404 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
405 spin_unlock(&qp->s_lock);
406 spin_unlock_irqrestore(&qp->r_lock, ps->flags);
407 spin_lock_irqsave(&qp->s_lock, ps->flags);
408bail:
409 qp->s_ack_state = OP(ACKNOWLEDGE);
410
411
412
413
414 smp_wmb();
415 qp->s_flags &= ~(RVT_S_RESP_PENDING
416 | RVT_S_ACK_PENDING
417 | HFI1_S_AHG_VALID);
418 return 0;
419}
420
421
422
423
424
425
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427
428
429
430int hfi1_make_rc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
431{
432 struct hfi1_qp_priv *priv = qp->priv;
433 struct hfi1_ibdev *dev = to_idev(qp->ibqp.device);
434 struct ib_other_headers *ohdr;
435 struct rvt_sge_state *ss = NULL;
436 struct rvt_swqe *wqe;
437 struct hfi1_swqe_priv *wpriv;
438 struct tid_rdma_request *req = NULL;
439
440 u32 hwords = 5;
441 u32 len = 0;
442 u32 bth0 = 0, bth2 = 0;
443 u32 bth1 = qp->remote_qpn | (HFI1_CAP_IS_KSET(OPFN) << IB_BTHE_E_SHIFT);
444 u32 pmtu = qp->pmtu;
445 char newreq;
446 int middle = 0;
447 int delta;
448 struct tid_rdma_flow *flow = NULL;
449 struct tid_rdma_params *remote;
450
451 trace_hfi1_sender_make_rc_req(qp);
452 lockdep_assert_held(&qp->s_lock);
453 ps->s_txreq = get_txreq(ps->dev, qp);
454 if (!ps->s_txreq)
455 goto bail_no_tx;
456
457 if (priv->hdr_type == HFI1_PKT_TYPE_9B) {
458
459 hwords = 5;
460 if (rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH)
461 ohdr = &ps->s_txreq->phdr.hdr.ibh.u.l.oth;
462 else
463 ohdr = &ps->s_txreq->phdr.hdr.ibh.u.oth;
464 } else {
465
466 hwords = 7;
467 if ((rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH) &&
468 (hfi1_check_mcast(rdma_ah_get_dlid(&qp->remote_ah_attr))))
469 ohdr = &ps->s_txreq->phdr.hdr.opah.u.l.oth;
470 else
471 ohdr = &ps->s_txreq->phdr.hdr.opah.u.oth;
472 }
473
474
475 if ((qp->s_flags & RVT_S_RESP_PENDING) &&
476 make_rc_ack(dev, qp, ohdr, ps))
477 return 1;
478
479 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_SEND_OK)) {
480 if (!(ib_rvt_state_ops[qp->state] & RVT_FLUSH_SEND))
481 goto bail;
482
483 if (qp->s_last == READ_ONCE(qp->s_head))
484 goto bail;
485
486 if (iowait_sdma_pending(&priv->s_iowait)) {
487 qp->s_flags |= RVT_S_WAIT_DMA;
488 goto bail;
489 }
490 clear_ahg(qp);
491 wqe = rvt_get_swqe_ptr(qp, qp->s_last);
492 hfi1_trdma_send_complete(qp, wqe, qp->s_last != qp->s_acked ?
493 IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR);
494
495 goto done_free_tx;
496 }
497
498 if (qp->s_flags & (RVT_S_WAIT_RNR | RVT_S_WAIT_ACK | HFI1_S_WAIT_HALT))
499 goto bail;
500
501 if (cmp_psn(qp->s_psn, qp->s_sending_hpsn) <= 0) {
502 if (cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0) {
503 qp->s_flags |= RVT_S_WAIT_PSN;
504 goto bail;
505 }
506 qp->s_sending_psn = qp->s_psn;
507 qp->s_sending_hpsn = qp->s_psn - 1;
508 }
509
510
511 wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
512check_s_state:
513 switch (qp->s_state) {
514 default:
515 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_NEXT_SEND_OK))
516 goto bail;
517
518
519
520
521
522
523
524 newreq = 0;
525 if (qp->s_cur == qp->s_tail) {
526
527 if (qp->s_tail == READ_ONCE(qp->s_head)) {
528 clear_ahg(qp);
529 goto bail;
530 }
531
532
533
534
535
536
537 if ((wqe->wr.send_flags & IB_SEND_FENCE) &&
538 qp->s_num_rd_atomic &&
539 (wqe->wr.opcode != IB_WR_TID_RDMA_READ ||
540 priv->pending_tid_r_segs < qp->s_num_rd_atomic)) {
541 qp->s_flags |= RVT_S_WAIT_FENCE;
542 goto bail;
543 }
544
545
546
547
548 if (wqe->wr.opcode == IB_WR_REG_MR ||
549 wqe->wr.opcode == IB_WR_LOCAL_INV) {
550 int local_ops = 0;
551 int err = 0;
552
553 if (qp->s_last != qp->s_cur)
554 goto bail;
555 if (++qp->s_cur == qp->s_size)
556 qp->s_cur = 0;
557 if (++qp->s_tail == qp->s_size)
558 qp->s_tail = 0;
559 if (!(wqe->wr.send_flags &
560 RVT_SEND_COMPLETION_ONLY)) {
561 err = rvt_invalidate_rkey(
562 qp,
563 wqe->wr.ex.invalidate_rkey);
564 local_ops = 1;
565 }
566 rvt_send_complete(qp, wqe,
567 err ? IB_WC_LOC_PROT_ERR
568 : IB_WC_SUCCESS);
569 if (local_ops)
570 atomic_dec(&qp->local_ops_pending);
571 goto done_free_tx;
572 }
573
574 newreq = 1;
575 qp->s_psn = wqe->psn;
576 }
577
578
579
580
581
582 len = wqe->length;
583 ss = &qp->s_sge;
584 bth2 = mask_psn(qp->s_psn);
585
586
587
588
589
590 if ((priv->s_flags & HFI1_S_TID_WAIT_INTERLCK) ||
591 hfi1_tid_rdma_wqe_interlock(qp, wqe))
592 goto bail;
593
594 switch (wqe->wr.opcode) {
595 case IB_WR_SEND:
596 case IB_WR_SEND_WITH_IMM:
597 case IB_WR_SEND_WITH_INV:
598
599 if (!rvt_rc_credit_avail(qp, wqe))
600 goto bail;
601 if (len > pmtu) {
602 qp->s_state = OP(SEND_FIRST);
603 len = pmtu;
604 break;
605 }
606 if (wqe->wr.opcode == IB_WR_SEND) {
607 qp->s_state = OP(SEND_ONLY);
608 } else if (wqe->wr.opcode == IB_WR_SEND_WITH_IMM) {
609 qp->s_state = OP(SEND_ONLY_WITH_IMMEDIATE);
610
611 ohdr->u.imm_data = wqe->wr.ex.imm_data;
612 hwords += 1;
613 } else {
614 qp->s_state = OP(SEND_ONLY_WITH_INVALIDATE);
615
616 ohdr->u.ieth = cpu_to_be32(
617 wqe->wr.ex.invalidate_rkey);
618 hwords += 1;
619 }
620 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
621 bth0 |= IB_BTH_SOLICITED;
622 bth2 |= IB_BTH_REQ_ACK;
623 if (++qp->s_cur == qp->s_size)
624 qp->s_cur = 0;
625 break;
626
627 case IB_WR_RDMA_WRITE:
628 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
629 qp->s_lsn++;
630 goto no_flow_control;
631 case IB_WR_RDMA_WRITE_WITH_IMM:
632
633 if (!rvt_rc_credit_avail(qp, wqe))
634 goto bail;
635no_flow_control:
636 put_ib_reth_vaddr(
637 wqe->rdma_wr.remote_addr,
638 &ohdr->u.rc.reth);
639 ohdr->u.rc.reth.rkey =
640 cpu_to_be32(wqe->rdma_wr.rkey);
641 ohdr->u.rc.reth.length = cpu_to_be32(len);
642 hwords += sizeof(struct ib_reth) / sizeof(u32);
643 if (len > pmtu) {
644 qp->s_state = OP(RDMA_WRITE_FIRST);
645 len = pmtu;
646 break;
647 }
648 if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
649 qp->s_state = OP(RDMA_WRITE_ONLY);
650 } else {
651 qp->s_state =
652 OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
653
654 ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
655 hwords += 1;
656 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
657 bth0 |= IB_BTH_SOLICITED;
658 }
659 bth2 |= IB_BTH_REQ_ACK;
660 if (++qp->s_cur == qp->s_size)
661 qp->s_cur = 0;
662 break;
663
664 case IB_WR_TID_RDMA_WRITE:
665 if (newreq) {
666
667
668
669 if (atomic_read(&priv->n_tid_requests) >=
670 HFI1_TID_RDMA_WRITE_CNT)
671 goto bail;
672
673 if (!(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
674 qp->s_lsn++;
675 }
676
677 hwords += hfi1_build_tid_rdma_write_req(qp, wqe, ohdr,
678 &bth1, &bth2,
679 &len);
680 ss = NULL;
681 if (priv->s_tid_cur == HFI1_QP_WQE_INVALID) {
682 priv->s_tid_cur = qp->s_cur;
683 if (priv->s_tid_tail == HFI1_QP_WQE_INVALID) {
684 priv->s_tid_tail = qp->s_cur;
685 priv->s_state = TID_OP(WRITE_RESP);
686 }
687 } else if (priv->s_tid_cur == priv->s_tid_head) {
688 struct rvt_swqe *__w;
689 struct tid_rdma_request *__r;
690
691 __w = rvt_get_swqe_ptr(qp, priv->s_tid_cur);
692 __r = wqe_to_tid_req(__w);
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714 if (__w->wr.opcode != IB_WR_TID_RDMA_WRITE ||
715 __r->state == TID_REQUEST_INACTIVE ||
716 __r->state == TID_REQUEST_COMPLETE ||
717 ((__r->state == TID_REQUEST_ACTIVE ||
718 __r->state == TID_REQUEST_SYNC) &&
719 __r->comp_seg == __r->total_segs)) {
720 if (priv->s_tid_tail ==
721 priv->s_tid_cur &&
722 priv->s_state ==
723 TID_OP(WRITE_DATA_LAST)) {
724 priv->s_tid_tail = qp->s_cur;
725 priv->s_state =
726 TID_OP(WRITE_RESP);
727 }
728 priv->s_tid_cur = qp->s_cur;
729 }
730
731
732
733
734
735
736
737
738
739
740 if (priv->s_tid_tail == qp->s_cur &&
741 priv->s_state == TID_OP(WRITE_DATA_LAST))
742 priv->s_state = TID_OP(WRITE_RESP);
743 }
744 req = wqe_to_tid_req(wqe);
745 if (newreq) {
746 priv->s_tid_head = qp->s_cur;
747 priv->pending_tid_w_resp += req->total_segs;
748 atomic_inc(&priv->n_tid_requests);
749 atomic_dec(&priv->n_requests);
750 } else {
751 req->state = TID_REQUEST_RESEND;
752 req->comp_seg = delta_psn(bth2, wqe->psn);
753
754
755
756
757 req->setup_head = req->clear_tail;
758 priv->pending_tid_w_resp +=
759 delta_psn(wqe->lpsn, bth2) + 1;
760 }
761
762 trace_hfi1_tid_write_sender_make_req(qp, newreq);
763 trace_hfi1_tid_req_make_req_write(qp, newreq,
764 wqe->wr.opcode,
765 wqe->psn, wqe->lpsn,
766 req);
767 if (++qp->s_cur == qp->s_size)
768 qp->s_cur = 0;
769 break;
770
771 case IB_WR_RDMA_READ:
772
773
774
775
776 if (qp->s_num_rd_atomic >=
777 qp->s_max_rd_atomic) {
778 qp->s_flags |= RVT_S_WAIT_RDMAR;
779 goto bail;
780 }
781 qp->s_num_rd_atomic++;
782 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
783 qp->s_lsn++;
784 put_ib_reth_vaddr(
785 wqe->rdma_wr.remote_addr,
786 &ohdr->u.rc.reth);
787 ohdr->u.rc.reth.rkey =
788 cpu_to_be32(wqe->rdma_wr.rkey);
789 ohdr->u.rc.reth.length = cpu_to_be32(len);
790 qp->s_state = OP(RDMA_READ_REQUEST);
791 hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
792 ss = NULL;
793 len = 0;
794 bth2 |= IB_BTH_REQ_ACK;
795 if (++qp->s_cur == qp->s_size)
796 qp->s_cur = 0;
797 break;
798
799 case IB_WR_TID_RDMA_READ:
800 trace_hfi1_tid_read_sender_make_req(qp, newreq);
801 wpriv = wqe->priv;
802 req = wqe_to_tid_req(wqe);
803 trace_hfi1_tid_req_make_req_read(qp, newreq,
804 wqe->wr.opcode,
805 wqe->psn, wqe->lpsn,
806 req);
807 delta = cmp_psn(qp->s_psn, wqe->psn);
808
809
810
811
812
813
814
815
816
817
818
819 if (qp->s_num_rd_atomic >= qp->s_max_rd_atomic) {
820 qp->s_flags |= RVT_S_WAIT_RDMAR;
821 goto bail;
822 }
823 if (newreq) {
824 struct tid_rdma_flow *flow =
825 &req->flows[req->setup_head];
826
827
828
829
830
831
832
833 if (!flow->npagesets) {
834 qp->s_sge.sge = wqe->sg_list[0];
835 qp->s_sge.sg_list = wqe->sg_list + 1;
836 qp->s_sge.num_sge = wqe->wr.num_sge;
837 qp->s_sge.total_len = wqe->length;
838 qp->s_len = wqe->length;
839 req->isge = 0;
840 req->clear_tail = req->setup_head;
841 req->flow_idx = req->setup_head;
842 req->state = TID_REQUEST_ACTIVE;
843 }
844 } else if (delta == 0) {
845
846 req->cur_seg = 0;
847 req->comp_seg = 0;
848 req->ack_pending = 0;
849 req->flow_idx = req->clear_tail;
850 req->state = TID_REQUEST_RESEND;
851 }
852 req->s_next_psn = qp->s_psn;
853
854 len = min_t(u32, req->seg_len,
855 wqe->length - req->seg_len * req->cur_seg);
856 delta = hfi1_build_tid_rdma_read_req(qp, wqe, ohdr,
857 &bth1, &bth2,
858 &len);
859 if (delta <= 0) {
860
861 goto bail;
862 }
863 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
864 qp->s_lsn++;
865 hwords += delta;
866 ss = &wpriv->ss;
867
868 if (req->cur_seg >= req->total_segs &&
869 ++qp->s_cur == qp->s_size)
870 qp->s_cur = 0;
871 break;
872
873 case IB_WR_ATOMIC_CMP_AND_SWP:
874 case IB_WR_ATOMIC_FETCH_AND_ADD:
875
876
877
878
879 if (qp->s_num_rd_atomic >=
880 qp->s_max_rd_atomic) {
881 qp->s_flags |= RVT_S_WAIT_RDMAR;
882 goto bail;
883 }
884 qp->s_num_rd_atomic++;
885 fallthrough;
886 case IB_WR_OPFN:
887 if (newreq && !(qp->s_flags & RVT_S_UNLIMITED_CREDIT))
888 qp->s_lsn++;
889 if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
890 wqe->wr.opcode == IB_WR_OPFN) {
891 qp->s_state = OP(COMPARE_SWAP);
892 put_ib_ateth_swap(wqe->atomic_wr.swap,
893 &ohdr->u.atomic_eth);
894 put_ib_ateth_compare(wqe->atomic_wr.compare_add,
895 &ohdr->u.atomic_eth);
896 } else {
897 qp->s_state = OP(FETCH_ADD);
898 put_ib_ateth_swap(wqe->atomic_wr.compare_add,
899 &ohdr->u.atomic_eth);
900 put_ib_ateth_compare(0, &ohdr->u.atomic_eth);
901 }
902 put_ib_ateth_vaddr(wqe->atomic_wr.remote_addr,
903 &ohdr->u.atomic_eth);
904 ohdr->u.atomic_eth.rkey = cpu_to_be32(
905 wqe->atomic_wr.rkey);
906 hwords += sizeof(struct ib_atomic_eth) / sizeof(u32);
907 ss = NULL;
908 len = 0;
909 bth2 |= IB_BTH_REQ_ACK;
910 if (++qp->s_cur == qp->s_size)
911 qp->s_cur = 0;
912 break;
913
914 default:
915 goto bail;
916 }
917 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ) {
918 qp->s_sge.sge = wqe->sg_list[0];
919 qp->s_sge.sg_list = wqe->sg_list + 1;
920 qp->s_sge.num_sge = wqe->wr.num_sge;
921 qp->s_sge.total_len = wqe->length;
922 qp->s_len = wqe->length;
923 }
924 if (newreq) {
925 qp->s_tail++;
926 if (qp->s_tail >= qp->s_size)
927 qp->s_tail = 0;
928 }
929 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
930 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
931 qp->s_psn = wqe->lpsn + 1;
932 else if (wqe->wr.opcode == IB_WR_TID_RDMA_READ)
933 qp->s_psn = req->s_next_psn;
934 else
935 qp->s_psn++;
936 break;
937
938 case OP(RDMA_READ_RESPONSE_FIRST):
939
940
941
942
943
944
945
946
947
948 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
949 fallthrough;
950 case OP(SEND_FIRST):
951 qp->s_state = OP(SEND_MIDDLE);
952 fallthrough;
953 case OP(SEND_MIDDLE):
954 bth2 = mask_psn(qp->s_psn++);
955 ss = &qp->s_sge;
956 len = qp->s_len;
957 if (len > pmtu) {
958 len = pmtu;
959 middle = HFI1_CAP_IS_KSET(SDMA_AHG);
960 break;
961 }
962 if (wqe->wr.opcode == IB_WR_SEND) {
963 qp->s_state = OP(SEND_LAST);
964 } else if (wqe->wr.opcode == IB_WR_SEND_WITH_IMM) {
965 qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
966
967 ohdr->u.imm_data = wqe->wr.ex.imm_data;
968 hwords += 1;
969 } else {
970 qp->s_state = OP(SEND_LAST_WITH_INVALIDATE);
971
972 ohdr->u.ieth = cpu_to_be32(wqe->wr.ex.invalidate_rkey);
973 hwords += 1;
974 }
975 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
976 bth0 |= IB_BTH_SOLICITED;
977 bth2 |= IB_BTH_REQ_ACK;
978 qp->s_cur++;
979 if (qp->s_cur >= qp->s_size)
980 qp->s_cur = 0;
981 break;
982
983 case OP(RDMA_READ_RESPONSE_LAST):
984
985
986
987
988
989
990
991
992
993 qp->s_len = restart_sge(&qp->s_sge, wqe, qp->s_psn, pmtu);
994 fallthrough;
995 case OP(RDMA_WRITE_FIRST):
996 qp->s_state = OP(RDMA_WRITE_MIDDLE);
997 fallthrough;
998 case OP(RDMA_WRITE_MIDDLE):
999 bth2 = mask_psn(qp->s_psn++);
1000 ss = &qp->s_sge;
1001 len = qp->s_len;
1002 if (len > pmtu) {
1003 len = pmtu;
1004 middle = HFI1_CAP_IS_KSET(SDMA_AHG);
1005 break;
1006 }
1007 if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
1008 qp->s_state = OP(RDMA_WRITE_LAST);
1009 } else {
1010 qp->s_state = OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
1011
1012 ohdr->u.imm_data = wqe->wr.ex.imm_data;
1013 hwords += 1;
1014 if (wqe->wr.send_flags & IB_SEND_SOLICITED)
1015 bth0 |= IB_BTH_SOLICITED;
1016 }
1017 bth2 |= IB_BTH_REQ_ACK;
1018 qp->s_cur++;
1019 if (qp->s_cur >= qp->s_size)
1020 qp->s_cur = 0;
1021 break;
1022
1023 case OP(RDMA_READ_RESPONSE_MIDDLE):
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033 len = (delta_psn(qp->s_psn, wqe->psn)) * pmtu;
1034 put_ib_reth_vaddr(
1035 wqe->rdma_wr.remote_addr + len,
1036 &ohdr->u.rc.reth);
1037 ohdr->u.rc.reth.rkey =
1038 cpu_to_be32(wqe->rdma_wr.rkey);
1039 ohdr->u.rc.reth.length = cpu_to_be32(wqe->length - len);
1040 qp->s_state = OP(RDMA_READ_REQUEST);
1041 hwords += sizeof(ohdr->u.rc.reth) / sizeof(u32);
1042 bth2 = mask_psn(qp->s_psn) | IB_BTH_REQ_ACK;
1043 qp->s_psn = wqe->lpsn + 1;
1044 ss = NULL;
1045 len = 0;
1046 qp->s_cur++;
1047 if (qp->s_cur == qp->s_size)
1048 qp->s_cur = 0;
1049 break;
1050
1051 case TID_OP(WRITE_RESP):
1052
1053
1054
1055
1056
1057 req = wqe_to_tid_req(wqe);
1058 req->state = TID_REQUEST_RESEND;
1059 rcu_read_lock();
1060 remote = rcu_dereference(priv->tid_rdma.remote);
1061 req->comp_seg = delta_psn(qp->s_psn, wqe->psn);
1062 len = wqe->length - (req->comp_seg * remote->max_len);
1063 rcu_read_unlock();
1064
1065 bth2 = mask_psn(qp->s_psn);
1066 hwords += hfi1_build_tid_rdma_write_req(qp, wqe, ohdr, &bth1,
1067 &bth2, &len);
1068 qp->s_psn = wqe->lpsn + 1;
1069 ss = NULL;
1070 qp->s_state = TID_OP(WRITE_REQ);
1071 priv->pending_tid_w_resp += delta_psn(wqe->lpsn, bth2) + 1;
1072 priv->s_tid_cur = qp->s_cur;
1073 if (++qp->s_cur == qp->s_size)
1074 qp->s_cur = 0;
1075 trace_hfi1_tid_req_make_req_write(qp, 0, wqe->wr.opcode,
1076 wqe->psn, wqe->lpsn, req);
1077 break;
1078
1079 case TID_OP(READ_RESP):
1080 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ)
1081 goto bail;
1082
1083 req = wqe_to_tid_req(wqe);
1084 wpriv = wqe->priv;
1085
1086
1087
1088
1089
1090 req->cur_seg = delta_psn(qp->s_psn, wqe->psn) / priv->pkts_ps;
1091
1092
1093
1094
1095
1096
1097
1098 req->state = TID_REQUEST_RESEND;
1099 hfi1_tid_rdma_restart_req(qp, wqe, &bth2);
1100 if (req->state != TID_REQUEST_ACTIVE) {
1101
1102
1103
1104
1105 hfi1_kern_exp_rcv_clear_all(req);
1106 hfi1_kern_clear_hw_flow(priv->rcd, qp);
1107
1108 hfi1_trdma_send_complete(qp, wqe, IB_WC_LOC_QP_OP_ERR);
1109 goto bail;
1110 }
1111 req->state = TID_REQUEST_RESEND;
1112 len = min_t(u32, req->seg_len,
1113 wqe->length - req->seg_len * req->cur_seg);
1114 flow = &req->flows[req->flow_idx];
1115 len -= flow->sent;
1116 req->s_next_psn = flow->flow_state.ib_lpsn + 1;
1117 delta = hfi1_build_tid_rdma_read_packet(wqe, ohdr, &bth1,
1118 &bth2, &len);
1119 if (delta <= 0) {
1120
1121 goto bail;
1122 }
1123 hwords += delta;
1124 ss = &wpriv->ss;
1125
1126 if (req->cur_seg >= req->total_segs &&
1127 ++qp->s_cur == qp->s_size)
1128 qp->s_cur = 0;
1129 qp->s_psn = req->s_next_psn;
1130 trace_hfi1_tid_req_make_req_read(qp, 0, wqe->wr.opcode,
1131 wqe->psn, wqe->lpsn, req);
1132 break;
1133 case TID_OP(READ_REQ):
1134 req = wqe_to_tid_req(wqe);
1135 delta = cmp_psn(qp->s_psn, wqe->psn);
1136
1137
1138
1139
1140
1141 if (wqe->wr.opcode != IB_WR_TID_RDMA_READ || delta == 0 ||
1142 qp->s_cur == qp->s_tail) {
1143 qp->s_state = OP(RDMA_READ_REQUEST);
1144 if (delta == 0 || qp->s_cur == qp->s_tail)
1145 goto check_s_state;
1146 else
1147 goto bail;
1148 }
1149
1150
1151 if (qp->s_num_rd_atomic >= qp->s_max_rd_atomic) {
1152 qp->s_flags |= RVT_S_WAIT_RDMAR;
1153 goto bail;
1154 }
1155
1156 wpriv = wqe->priv;
1157
1158 len = min_t(u32, req->seg_len,
1159 wqe->length - req->seg_len * req->cur_seg);
1160 delta = hfi1_build_tid_rdma_read_req(qp, wqe, ohdr, &bth1,
1161 &bth2, &len);
1162 if (delta <= 0) {
1163
1164 goto bail;
1165 }
1166 hwords += delta;
1167 ss = &wpriv->ss;
1168
1169 if (req->cur_seg >= req->total_segs &&
1170 ++qp->s_cur == qp->s_size)
1171 qp->s_cur = 0;
1172 qp->s_psn = req->s_next_psn;
1173 trace_hfi1_tid_req_make_req_read(qp, 0, wqe->wr.opcode,
1174 wqe->psn, wqe->lpsn, req);
1175 break;
1176 }
1177 qp->s_sending_hpsn = bth2;
1178 delta = delta_psn(bth2, wqe->psn);
1179 if (delta && delta % HFI1_PSN_CREDIT == 0 &&
1180 wqe->wr.opcode != IB_WR_TID_RDMA_WRITE)
1181 bth2 |= IB_BTH_REQ_ACK;
1182 if (qp->s_flags & RVT_S_SEND_ONE) {
1183 qp->s_flags &= ~RVT_S_SEND_ONE;
1184 qp->s_flags |= RVT_S_WAIT_ACK;
1185 bth2 |= IB_BTH_REQ_ACK;
1186 }
1187 qp->s_len -= len;
1188 ps->s_txreq->hdr_dwords = hwords;
1189 ps->s_txreq->sde = priv->s_sde;
1190 ps->s_txreq->ss = ss;
1191 ps->s_txreq->s_cur_size = len;
1192 hfi1_make_ruc_header(
1193 qp,
1194 ohdr,
1195 bth0 | (qp->s_state << 24),
1196 bth1,
1197 bth2,
1198 middle,
1199 ps);
1200 return 1;
1201
1202done_free_tx:
1203 hfi1_put_txreq(ps->s_txreq);
1204 ps->s_txreq = NULL;
1205 return 1;
1206
1207bail:
1208 hfi1_put_txreq(ps->s_txreq);
1209
1210bail_no_tx:
1211 ps->s_txreq = NULL;
1212 qp->s_flags &= ~RVT_S_BUSY;
1213
1214
1215
1216
1217
1218 iowait_set_flag(&priv->s_iowait, IOWAIT_PENDING_IB);
1219 return 0;
1220}
1221
1222static inline void hfi1_make_bth_aeth(struct rvt_qp *qp,
1223 struct ib_other_headers *ohdr,
1224 u32 bth0, u32 bth1)
1225{
1226 if (qp->r_nak_state)
1227 ohdr->u.aeth = cpu_to_be32((qp->r_msn & IB_MSN_MASK) |
1228 (qp->r_nak_state <<
1229 IB_AETH_CREDIT_SHIFT));
1230 else
1231 ohdr->u.aeth = rvt_compute_aeth(qp);
1232
1233 ohdr->bth[0] = cpu_to_be32(bth0);
1234 ohdr->bth[1] = cpu_to_be32(bth1 | qp->remote_qpn);
1235 ohdr->bth[2] = cpu_to_be32(mask_psn(qp->r_ack_psn));
1236}
1237
1238static inline void hfi1_queue_rc_ack(struct hfi1_packet *packet, bool is_fecn)
1239{
1240 struct rvt_qp *qp = packet->qp;
1241 struct hfi1_ibport *ibp;
1242 unsigned long flags;
1243
1244 spin_lock_irqsave(&qp->s_lock, flags);
1245 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK))
1246 goto unlock;
1247 ibp = rcd_to_iport(packet->rcd);
1248 this_cpu_inc(*ibp->rvp.rc_qacks);
1249 qp->s_flags |= RVT_S_ACK_PENDING | RVT_S_RESP_PENDING;
1250 qp->s_nak_state = qp->r_nak_state;
1251 qp->s_ack_psn = qp->r_ack_psn;
1252 if (is_fecn)
1253 qp->s_flags |= RVT_S_ECN;
1254
1255
1256 hfi1_schedule_send(qp);
1257unlock:
1258 spin_unlock_irqrestore(&qp->s_lock, flags);
1259}
1260
1261static inline void hfi1_make_rc_ack_9B(struct hfi1_packet *packet,
1262 struct hfi1_opa_header *opa_hdr,
1263 u8 sc5, bool is_fecn,
1264 u64 *pbc_flags, u32 *hwords,
1265 u32 *nwords)
1266{
1267 struct rvt_qp *qp = packet->qp;
1268 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
1269 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1270 struct ib_header *hdr = &opa_hdr->ibh;
1271 struct ib_other_headers *ohdr;
1272 u16 lrh0 = HFI1_LRH_BTH;
1273 u16 pkey;
1274 u32 bth0, bth1;
1275
1276 opa_hdr->hdr_type = HFI1_PKT_TYPE_9B;
1277 ohdr = &hdr->u.oth;
1278
1279 *hwords = 6;
1280
1281 if (unlikely(rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH)) {
1282 *hwords += hfi1_make_grh(ibp, &hdr->u.l.grh,
1283 rdma_ah_read_grh(&qp->remote_ah_attr),
1284 *hwords - 2, SIZE_OF_CRC);
1285 ohdr = &hdr->u.l.oth;
1286 lrh0 = HFI1_LRH_GRH;
1287 }
1288
1289 *pbc_flags |= ((!!(sc5 & 0x10)) << PBC_DC_INFO_SHIFT);
1290
1291
1292 pkey = hfi1_get_pkey(ibp, qp->s_pkey_index);
1293
1294 lrh0 |= (sc5 & IB_SC_MASK) << IB_SC_SHIFT |
1295 (rdma_ah_get_sl(&qp->remote_ah_attr) & IB_SL_MASK) <<
1296 IB_SL_SHIFT;
1297
1298 hfi1_make_ib_hdr(hdr, lrh0, *hwords + SIZE_OF_CRC,
1299 opa_get_lid(rdma_ah_get_dlid(&qp->remote_ah_attr), 9B),
1300 ppd->lid | rdma_ah_get_path_bits(&qp->remote_ah_attr));
1301
1302 bth0 = pkey | (OP(ACKNOWLEDGE) << 24);
1303 if (qp->s_mig_state == IB_MIG_MIGRATED)
1304 bth0 |= IB_BTH_MIG_REQ;
1305 bth1 = (!!is_fecn) << IB_BECN_SHIFT;
1306
1307
1308
1309
1310 bth1 |= HFI1_CAP_IS_KSET(OPFN) << IB_BTHE_E_SHIFT;
1311 hfi1_make_bth_aeth(qp, ohdr, bth0, bth1);
1312}
1313
1314static inline void hfi1_make_rc_ack_16B(struct hfi1_packet *packet,
1315 struct hfi1_opa_header *opa_hdr,
1316 u8 sc5, bool is_fecn,
1317 u64 *pbc_flags, u32 *hwords,
1318 u32 *nwords)
1319{
1320 struct rvt_qp *qp = packet->qp;
1321 struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
1322 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1323 struct hfi1_16b_header *hdr = &opa_hdr->opah;
1324 struct ib_other_headers *ohdr;
1325 u32 bth0, bth1 = 0;
1326 u16 len, pkey;
1327 bool becn = is_fecn;
1328 u8 l4 = OPA_16B_L4_IB_LOCAL;
1329 u8 extra_bytes;
1330
1331 opa_hdr->hdr_type = HFI1_PKT_TYPE_16B;
1332 ohdr = &hdr->u.oth;
1333
1334 *hwords = 8;
1335 extra_bytes = hfi1_get_16b_padding(*hwords << 2, 0);
1336 *nwords = SIZE_OF_CRC + ((extra_bytes + SIZE_OF_LT) >> 2);
1337
1338 if (unlikely(rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH) &&
1339 hfi1_check_mcast(rdma_ah_get_dlid(&qp->remote_ah_attr))) {
1340 *hwords += hfi1_make_grh(ibp, &hdr->u.l.grh,
1341 rdma_ah_read_grh(&qp->remote_ah_attr),
1342 *hwords - 4, *nwords);
1343 ohdr = &hdr->u.l.oth;
1344 l4 = OPA_16B_L4_IB_GLOBAL;
1345 }
1346 *pbc_flags |= PBC_PACKET_BYPASS | PBC_INSERT_BYPASS_ICRC;
1347
1348
1349 pkey = hfi1_get_pkey(ibp, qp->s_pkey_index);
1350
1351
1352 len = (*hwords + *nwords) >> 1;
1353
1354 hfi1_make_16b_hdr(hdr, ppd->lid |
1355 (rdma_ah_get_path_bits(&qp->remote_ah_attr) &
1356 ((1 << ppd->lmc) - 1)),
1357 opa_get_lid(rdma_ah_get_dlid(&qp->remote_ah_attr),
1358 16B), len, pkey, becn, 0, l4, sc5);
1359
1360 bth0 = pkey | (OP(ACKNOWLEDGE) << 24);
1361 bth0 |= extra_bytes << 20;
1362 if (qp->s_mig_state == IB_MIG_MIGRATED)
1363 bth1 = OPA_BTH_MIG_REQ;
1364 hfi1_make_bth_aeth(qp, ohdr, bth0, bth1);
1365}
1366
1367typedef void (*hfi1_make_rc_ack)(struct hfi1_packet *packet,
1368 struct hfi1_opa_header *opa_hdr,
1369 u8 sc5, bool is_fecn,
1370 u64 *pbc_flags, u32 *hwords,
1371 u32 *nwords);
1372
1373
1374static const hfi1_make_rc_ack hfi1_make_rc_ack_tbl[2] = {
1375 [HFI1_PKT_TYPE_9B] = &hfi1_make_rc_ack_9B,
1376 [HFI1_PKT_TYPE_16B] = &hfi1_make_rc_ack_16B
1377};
1378
1379
1380
1381
1382
1383
1384
1385
1386void hfi1_send_rc_ack(struct hfi1_packet *packet, bool is_fecn)
1387{
1388 struct hfi1_ctxtdata *rcd = packet->rcd;
1389 struct rvt_qp *qp = packet->qp;
1390 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
1391 struct hfi1_qp_priv *priv = qp->priv;
1392 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1393 u8 sc5 = ibp->sl_to_sc[rdma_ah_get_sl(&qp->remote_ah_attr)];
1394 u64 pbc, pbc_flags = 0;
1395 u32 hwords = 0;
1396 u32 nwords = 0;
1397 u32 plen;
1398 struct pio_buf *pbuf;
1399 struct hfi1_opa_header opa_hdr;
1400
1401
1402 qp->r_adefered = 0;
1403
1404
1405 if (qp->s_flags & RVT_S_RESP_PENDING) {
1406 hfi1_queue_rc_ack(packet, is_fecn);
1407 return;
1408 }
1409
1410
1411 if (qp->s_rdma_ack_cnt) {
1412 hfi1_queue_rc_ack(packet, is_fecn);
1413 return;
1414 }
1415
1416
1417 if (driver_lstate(ppd) != IB_PORT_ACTIVE)
1418 return;
1419
1420
1421 hfi1_make_rc_ack_tbl[priv->hdr_type](packet, &opa_hdr, sc5, is_fecn,
1422 &pbc_flags, &hwords, &nwords);
1423
1424 plen = 2 + hwords + nwords;
1425 pbc = create_pbc(ppd, pbc_flags, qp->srate_mbps,
1426 sc_to_vlt(ppd->dd, sc5), plen);
1427 pbuf = sc_buffer_alloc(rcd->sc, plen, NULL, NULL);
1428 if (IS_ERR_OR_NULL(pbuf)) {
1429
1430
1431
1432
1433
1434
1435 hfi1_queue_rc_ack(packet, is_fecn);
1436 return;
1437 }
1438 trace_ack_output_ibhdr(dd_from_ibdev(qp->ibqp.device),
1439 &opa_hdr, ib_is_sc5(sc5));
1440
1441
1442 ppd->dd->pio_inline_send(ppd->dd, pbuf, pbc,
1443 (priv->hdr_type == HFI1_PKT_TYPE_9B ?
1444 (void *)&opa_hdr.ibh :
1445 (void *)&opa_hdr.opah), hwords);
1446 return;
1447}
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459static void update_num_rd_atomic(struct rvt_qp *qp, u32 psn,
1460 struct rvt_swqe *wqe)
1461{
1462 u32 opcode = wqe->wr.opcode;
1463
1464 if (opcode == IB_WR_RDMA_READ ||
1465 opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
1466 opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
1467 qp->s_num_rd_atomic++;
1468 } else if (opcode == IB_WR_TID_RDMA_READ) {
1469 struct tid_rdma_request *req = wqe_to_tid_req(wqe);
1470 struct hfi1_qp_priv *priv = qp->priv;
1471
1472 if (cmp_psn(psn, wqe->lpsn) <= 0) {
1473 u32 cur_seg;
1474
1475 cur_seg = (psn - wqe->psn) / priv->pkts_ps;
1476 req->ack_pending = cur_seg - req->comp_seg;
1477 priv->pending_tid_r_segs += req->ack_pending;
1478 qp->s_num_rd_atomic += req->ack_pending;
1479 trace_hfi1_tid_req_update_num_rd_atomic(qp, 0,
1480 wqe->wr.opcode,
1481 wqe->psn,
1482 wqe->lpsn,
1483 req);
1484 } else {
1485 priv->pending_tid_r_segs += req->total_segs;
1486 qp->s_num_rd_atomic += req->total_segs;
1487 }
1488 }
1489}
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500static void reset_psn(struct rvt_qp *qp, u32 psn)
1501{
1502 u32 n = qp->s_acked;
1503 struct rvt_swqe *wqe = rvt_get_swqe_ptr(qp, n);
1504 u32 opcode;
1505 struct hfi1_qp_priv *priv = qp->priv;
1506
1507 lockdep_assert_held(&qp->s_lock);
1508 qp->s_cur = n;
1509 priv->pending_tid_r_segs = 0;
1510 priv->pending_tid_w_resp = 0;
1511 qp->s_num_rd_atomic = 0;
1512
1513
1514
1515
1516
1517 if (cmp_psn(psn, wqe->psn) <= 0) {
1518 qp->s_state = OP(SEND_LAST);
1519 goto done;
1520 }
1521 update_num_rd_atomic(qp, psn, wqe);
1522
1523
1524 for (;;) {
1525 int diff;
1526
1527 if (++n == qp->s_size)
1528 n = 0;
1529 if (n == qp->s_tail)
1530 break;
1531 wqe = rvt_get_swqe_ptr(qp, n);
1532 diff = cmp_psn(psn, wqe->psn);
1533 if (diff < 0) {
1534
1535 wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
1536 break;
1537 }
1538 qp->s_cur = n;
1539
1540
1541
1542
1543 if (diff == 0) {
1544 qp->s_state = OP(SEND_LAST);
1545 goto done;
1546 }
1547
1548 update_num_rd_atomic(qp, psn, wqe);
1549 }
1550 opcode = wqe->wr.opcode;
1551
1552
1553
1554
1555
1556
1557 switch (opcode) {
1558 case IB_WR_SEND:
1559 case IB_WR_SEND_WITH_IMM:
1560 qp->s_state = OP(RDMA_READ_RESPONSE_FIRST);
1561 break;
1562
1563 case IB_WR_RDMA_WRITE:
1564 case IB_WR_RDMA_WRITE_WITH_IMM:
1565 qp->s_state = OP(RDMA_READ_RESPONSE_LAST);
1566 break;
1567
1568 case IB_WR_TID_RDMA_WRITE:
1569 qp->s_state = TID_OP(WRITE_RESP);
1570 break;
1571
1572 case IB_WR_RDMA_READ:
1573 qp->s_state = OP(RDMA_READ_RESPONSE_MIDDLE);
1574 break;
1575
1576 case IB_WR_TID_RDMA_READ:
1577 qp->s_state = TID_OP(READ_RESP);
1578 break;
1579
1580 default:
1581
1582
1583
1584
1585 qp->s_state = OP(SEND_LAST);
1586 }
1587done:
1588 priv->s_flags &= ~HFI1_S_TID_WAIT_INTERLCK;
1589 qp->s_psn = psn;
1590
1591
1592
1593
1594
1595 if ((cmp_psn(qp->s_psn, qp->s_sending_hpsn) <= 0) &&
1596 (cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0))
1597 qp->s_flags |= RVT_S_WAIT_PSN;
1598 qp->s_flags &= ~HFI1_S_AHG_VALID;
1599 trace_hfi1_sender_reset_psn(qp);
1600}
1601
1602
1603
1604
1605
1606void hfi1_restart_rc(struct rvt_qp *qp, u32 psn, int wait)
1607{
1608 struct hfi1_qp_priv *priv = qp->priv;
1609 struct rvt_swqe *wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
1610 struct hfi1_ibport *ibp;
1611
1612 lockdep_assert_held(&qp->r_lock);
1613 lockdep_assert_held(&qp->s_lock);
1614 trace_hfi1_sender_restart_rc(qp);
1615 if (qp->s_retry == 0) {
1616 if (qp->s_mig_state == IB_MIG_ARMED) {
1617 hfi1_migrate_qp(qp);
1618 qp->s_retry = qp->s_retry_cnt;
1619 } else if (qp->s_last == qp->s_acked) {
1620
1621
1622
1623
1624 if (wqe->wr.opcode == IB_WR_OPFN) {
1625 struct hfi1_ibport *ibp =
1626 to_iport(qp->ibqp.device, qp->port_num);
1627
1628
1629
1630
1631
1632 opfn_conn_reply(qp, priv->opfn.curr);
1633 wqe = do_rc_completion(qp, wqe, ibp);
1634 qp->s_flags &= ~RVT_S_WAIT_ACK;
1635 } else {
1636 trace_hfi1_tid_write_sender_restart_rc(qp, 0);
1637 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ) {
1638 struct tid_rdma_request *req;
1639
1640 req = wqe_to_tid_req(wqe);
1641 hfi1_kern_exp_rcv_clear_all(req);
1642 hfi1_kern_clear_hw_flow(priv->rcd, qp);
1643 }
1644
1645 hfi1_trdma_send_complete(qp, wqe,
1646 IB_WC_RETRY_EXC_ERR);
1647 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
1648 }
1649 return;
1650 } else {
1651 return;
1652 }
1653 } else {
1654 qp->s_retry--;
1655 }
1656
1657 ibp = to_iport(qp->ibqp.device, qp->port_num);
1658 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
1659 wqe->wr.opcode == IB_WR_TID_RDMA_READ)
1660 ibp->rvp.n_rc_resends++;
1661 else
1662 ibp->rvp.n_rc_resends += delta_psn(qp->s_psn, psn);
1663
1664 qp->s_flags &= ~(RVT_S_WAIT_FENCE | RVT_S_WAIT_RDMAR |
1665 RVT_S_WAIT_SSN_CREDIT | RVT_S_WAIT_PSN |
1666 RVT_S_WAIT_ACK | HFI1_S_WAIT_TID_RESP);
1667 if (wait)
1668 qp->s_flags |= RVT_S_SEND_ONE;
1669 reset_psn(qp, psn);
1670}
1671
1672
1673
1674
1675
1676
1677static void reset_sending_psn(struct rvt_qp *qp, u32 psn)
1678{
1679 struct rvt_swqe *wqe;
1680 u32 n = qp->s_last;
1681
1682 lockdep_assert_held(&qp->s_lock);
1683
1684 for (;;) {
1685 wqe = rvt_get_swqe_ptr(qp, n);
1686 if (cmp_psn(psn, wqe->lpsn) <= 0) {
1687 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
1688 wqe->wr.opcode == IB_WR_TID_RDMA_READ ||
1689 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
1690 qp->s_sending_psn = wqe->lpsn + 1;
1691 else
1692 qp->s_sending_psn = psn + 1;
1693 break;
1694 }
1695 if (++n == qp->s_size)
1696 n = 0;
1697 if (n == qp->s_tail)
1698 break;
1699 }
1700}
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714void hfi1_rc_verbs_aborted(struct rvt_qp *qp, struct hfi1_opa_header *opah)
1715{
1716 struct ib_other_headers *ohdr = hfi1_get_rc_ohdr(opah);
1717 u8 opcode = ib_bth_get_opcode(ohdr);
1718 u32 psn;
1719
1720
1721 if ((opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
1722 opcode <= OP(ATOMIC_ACKNOWLEDGE)) ||
1723 opcode == TID_OP(READ_RESP) ||
1724 opcode == TID_OP(WRITE_RESP))
1725 return;
1726
1727 psn = ib_bth_get_psn(ohdr) | IB_BTH_REQ_ACK;
1728 ohdr->bth[2] = cpu_to_be32(psn);
1729 qp->s_flags |= RVT_S_SEND_ONE;
1730}
1731
1732
1733
1734
1735void hfi1_rc_send_complete(struct rvt_qp *qp, struct hfi1_opa_header *opah)
1736{
1737 struct ib_other_headers *ohdr;
1738 struct hfi1_qp_priv *priv = qp->priv;
1739 struct rvt_swqe *wqe;
1740 u32 opcode, head, tail;
1741 u32 psn;
1742 struct tid_rdma_request *req;
1743
1744 lockdep_assert_held(&qp->s_lock);
1745 if (!(ib_rvt_state_ops[qp->state] & RVT_SEND_OR_FLUSH_OR_RECV_OK))
1746 return;
1747
1748 ohdr = hfi1_get_rc_ohdr(opah);
1749 opcode = ib_bth_get_opcode(ohdr);
1750 if ((opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
1751 opcode <= OP(ATOMIC_ACKNOWLEDGE)) ||
1752 opcode == TID_OP(READ_RESP) ||
1753 opcode == TID_OP(WRITE_RESP)) {
1754 WARN_ON(!qp->s_rdma_ack_cnt);
1755 qp->s_rdma_ack_cnt--;
1756 return;
1757 }
1758
1759 psn = ib_bth_get_psn(ohdr);
1760
1761
1762
1763
1764 if (opcode != TID_OP(WRITE_DATA) &&
1765 opcode != TID_OP(WRITE_DATA_LAST) &&
1766 opcode != TID_OP(ACK) && opcode != TID_OP(RESYNC))
1767 reset_sending_psn(qp, psn);
1768
1769
1770 if (opcode >= TID_OP(WRITE_REQ) &&
1771 opcode <= TID_OP(WRITE_DATA_LAST)) {
1772 head = priv->s_tid_head;
1773 tail = priv->s_tid_cur;
1774
1775
1776
1777
1778
1779
1780
1781
1782 wqe = rvt_get_swqe_ptr(qp, tail);
1783 req = wqe_to_tid_req(wqe);
1784 if (head == tail && req->comp_seg < req->total_segs) {
1785 if (tail == 0)
1786 tail = qp->s_size - 1;
1787 else
1788 tail -= 1;
1789 }
1790 } else {
1791 head = qp->s_tail;
1792 tail = qp->s_acked;
1793 }
1794
1795
1796
1797
1798
1799 if ((psn & IB_BTH_REQ_ACK) && tail != head &&
1800 opcode != TID_OP(WRITE_DATA) && opcode != TID_OP(WRITE_DATA_LAST) &&
1801 opcode != TID_OP(RESYNC) &&
1802 !(qp->s_flags &
1803 (RVT_S_TIMER | RVT_S_WAIT_RNR | RVT_S_WAIT_PSN)) &&
1804 (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK)) {
1805 if (opcode == TID_OP(READ_REQ))
1806 rvt_add_retry_timer_ext(qp, priv->timeout_shift);
1807 else
1808 rvt_add_retry_timer(qp);
1809 }
1810
1811
1812 if ((opcode == TID_OP(WRITE_DATA) ||
1813 opcode == TID_OP(WRITE_DATA_LAST) ||
1814 opcode == TID_OP(RESYNC)) &&
1815 (psn & IB_BTH_REQ_ACK) &&
1816 !(priv->s_flags & HFI1_S_TID_RETRY_TIMER) &&
1817 (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK)) {
1818
1819
1820
1821
1822
1823 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
1824 req = wqe_to_tid_req(wqe);
1825 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
1826 req->ack_seg < req->cur_seg)
1827 hfi1_add_tid_retry_timer(qp);
1828 }
1829
1830 while (qp->s_last != qp->s_acked) {
1831 wqe = rvt_get_swqe_ptr(qp, qp->s_last);
1832 if (cmp_psn(wqe->lpsn, qp->s_sending_psn) >= 0 &&
1833 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0)
1834 break;
1835 trdma_clean_swqe(qp, wqe);
1836 trace_hfi1_qp_send_completion(qp, wqe, qp->s_last);
1837 rvt_qp_complete_swqe(qp,
1838 wqe,
1839 ib_hfi1_wc_opcode[wqe->wr.opcode],
1840 IB_WC_SUCCESS);
1841 }
1842
1843
1844
1845
1846 trace_hfi1_sendcomplete(qp, psn);
1847 if (qp->s_flags & RVT_S_WAIT_PSN &&
1848 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
1849 qp->s_flags &= ~RVT_S_WAIT_PSN;
1850 qp->s_sending_psn = qp->s_psn;
1851 qp->s_sending_hpsn = qp->s_psn - 1;
1852 hfi1_schedule_send(qp);
1853 }
1854}
1855
1856static inline void update_last_psn(struct rvt_qp *qp, u32 psn)
1857{
1858 qp->s_last_psn = psn;
1859}
1860
1861
1862
1863
1864
1865
1866struct rvt_swqe *do_rc_completion(struct rvt_qp *qp,
1867 struct rvt_swqe *wqe,
1868 struct hfi1_ibport *ibp)
1869{
1870 struct hfi1_qp_priv *priv = qp->priv;
1871
1872 lockdep_assert_held(&qp->s_lock);
1873
1874
1875
1876
1877
1878 trace_hfi1_rc_completion(qp, wqe->lpsn);
1879 if (cmp_psn(wqe->lpsn, qp->s_sending_psn) < 0 ||
1880 cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) > 0) {
1881 trdma_clean_swqe(qp, wqe);
1882 trace_hfi1_qp_send_completion(qp, wqe, qp->s_last);
1883 rvt_qp_complete_swqe(qp,
1884 wqe,
1885 ib_hfi1_wc_opcode[wqe->wr.opcode],
1886 IB_WC_SUCCESS);
1887 } else {
1888 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1889
1890 this_cpu_inc(*ibp->rvp.rc_delayed_comp);
1891
1892
1893
1894
1895 if (ppd->dd->flags & HFI1_HAS_SEND_DMA) {
1896 struct sdma_engine *engine;
1897 u8 sl = rdma_ah_get_sl(&qp->remote_ah_attr);
1898 u8 sc5;
1899
1900
1901 sc5 = ibp->sl_to_sc[sl];
1902 engine = qp_to_sdma_engine(qp, sc5);
1903 sdma_engine_progress_schedule(engine);
1904 }
1905 }
1906
1907 qp->s_retry = qp->s_retry_cnt;
1908
1909
1910
1911
1912
1913
1914
1915
1916 if (wqe->wr.opcode != IB_WR_TID_RDMA_WRITE)
1917 update_last_psn(qp, wqe->lpsn);
1918
1919
1920
1921
1922
1923
1924 if (qp->s_acked == qp->s_cur) {
1925 if (++qp->s_cur >= qp->s_size)
1926 qp->s_cur = 0;
1927 qp->s_acked = qp->s_cur;
1928 wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
1929 if (qp->s_acked != qp->s_tail) {
1930 qp->s_state = OP(SEND_LAST);
1931 qp->s_psn = wqe->psn;
1932 }
1933 } else {
1934 if (++qp->s_acked >= qp->s_size)
1935 qp->s_acked = 0;
1936 if (qp->state == IB_QPS_SQD && qp->s_acked == qp->s_cur)
1937 qp->s_draining = 0;
1938 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
1939 }
1940 if (priv->s_flags & HFI1_S_TID_WAIT_INTERLCK) {
1941 priv->s_flags &= ~HFI1_S_TID_WAIT_INTERLCK;
1942 hfi1_schedule_send(qp);
1943 }
1944 return wqe;
1945}
1946
1947static void set_restart_qp(struct rvt_qp *qp, struct hfi1_ctxtdata *rcd)
1948{
1949
1950 if (!(qp->r_flags & RVT_R_RDMAR_SEQ)) {
1951 qp->r_flags |= RVT_R_RDMAR_SEQ;
1952 hfi1_restart_rc(qp, qp->s_last_psn + 1, 0);
1953 if (list_empty(&qp->rspwait)) {
1954 qp->r_flags |= RVT_R_RSP_SEND;
1955 rvt_get_qp(qp);
1956 list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
1957 }
1958 }
1959}
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972static void update_qp_retry_state(struct rvt_qp *qp, u32 psn, u32 spsn,
1973 u32 lpsn)
1974{
1975 struct hfi1_qp_priv *qpriv = qp->priv;
1976
1977 qp->s_psn = psn + 1;
1978
1979
1980
1981
1982
1983
1984 if (cmp_psn(psn, lpsn) >= 0) {
1985 qp->s_cur = qpriv->s_tid_cur + 1;
1986 if (qp->s_cur >= qp->s_size)
1987 qp->s_cur = 0;
1988 qp->s_state = TID_OP(WRITE_REQ);
1989 } else if (!cmp_psn(psn, spsn)) {
1990 qp->s_cur = qpriv->s_tid_cur;
1991 qp->s_state = TID_OP(WRITE_RESP);
1992 }
1993}
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006int do_rc_ack(struct rvt_qp *qp, u32 aeth, u32 psn, int opcode,
2007 u64 val, struct hfi1_ctxtdata *rcd)
2008{
2009 struct hfi1_ibport *ibp;
2010 enum ib_wc_status status;
2011 struct hfi1_qp_priv *qpriv = qp->priv;
2012 struct rvt_swqe *wqe;
2013 int ret = 0;
2014 u32 ack_psn;
2015 int diff;
2016 struct rvt_dev_info *rdi;
2017
2018 lockdep_assert_held(&qp->s_lock);
2019
2020
2021
2022
2023
2024
2025 ack_psn = psn;
2026 if (aeth >> IB_AETH_NAK_SHIFT)
2027 ack_psn--;
2028 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2029 ibp = rcd_to_iport(rcd);
2030
2031
2032
2033
2034
2035 while ((diff = delta_psn(ack_psn, wqe->lpsn)) >= 0) {
2036
2037
2038
2039
2040
2041
2042 if (wqe->wr.opcode == IB_WR_RDMA_READ &&
2043 opcode == OP(RDMA_READ_RESPONSE_ONLY) &&
2044 diff == 0) {
2045 ret = 1;
2046 goto bail_stop;
2047 }
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057 if ((wqe->wr.opcode == IB_WR_RDMA_READ &&
2058 (opcode != OP(RDMA_READ_RESPONSE_LAST) || diff != 0)) ||
2059 (wqe->wr.opcode == IB_WR_TID_RDMA_READ &&
2060 (opcode != TID_OP(READ_RESP) || diff != 0)) ||
2061 ((wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2062 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) &&
2063 (opcode != OP(ATOMIC_ACKNOWLEDGE) || diff != 0)) ||
2064 (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2065 (delta_psn(psn, qp->s_last_psn) != 1))) {
2066 set_restart_qp(qp, rcd);
2067
2068
2069
2070
2071 goto bail_stop;
2072 }
2073 if (wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2074 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {
2075 u64 *vaddr = wqe->sg_list[0].vaddr;
2076 *vaddr = val;
2077 }
2078 if (wqe->wr.opcode == IB_WR_OPFN)
2079 opfn_conn_reply(qp, val);
2080
2081 if (qp->s_num_rd_atomic &&
2082 (wqe->wr.opcode == IB_WR_RDMA_READ ||
2083 wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2084 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)) {
2085 qp->s_num_rd_atomic--;
2086
2087 if ((qp->s_flags & RVT_S_WAIT_FENCE) &&
2088 !qp->s_num_rd_atomic) {
2089 qp->s_flags &= ~(RVT_S_WAIT_FENCE |
2090 RVT_S_WAIT_ACK);
2091 hfi1_schedule_send(qp);
2092 } else if (qp->s_flags & RVT_S_WAIT_RDMAR) {
2093 qp->s_flags &= ~(RVT_S_WAIT_RDMAR |
2094 RVT_S_WAIT_ACK);
2095 hfi1_schedule_send(qp);
2096 }
2097 }
2098
2099
2100
2101
2102
2103 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE)
2104 break;
2105
2106 wqe = do_rc_completion(qp, wqe, ibp);
2107 if (qp->s_acked == qp->s_tail)
2108 break;
2109 }
2110
2111 trace_hfi1_rc_ack_do(qp, aeth, psn, wqe);
2112 trace_hfi1_sender_do_rc_ack(qp);
2113 switch (aeth >> IB_AETH_NAK_SHIFT) {
2114 case 0:
2115 this_cpu_inc(*ibp->rvp.rc_acks);
2116 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ) {
2117 if (wqe_to_tid_req(wqe)->ack_pending)
2118 rvt_mod_retry_timer_ext(qp,
2119 qpriv->timeout_shift);
2120 else
2121 rvt_stop_rc_timers(qp);
2122 } else if (qp->s_acked != qp->s_tail) {
2123 struct rvt_swqe *__w = NULL;
2124
2125 if (qpriv->s_tid_cur != HFI1_QP_WQE_INVALID)
2126 __w = rvt_get_swqe_ptr(qp, qpriv->s_tid_cur);
2127
2128
2129
2130
2131
2132 if (__w && __w->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2133 opcode == TID_OP(WRITE_RESP)) {
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146 if (cmp_psn(psn, qp->s_last_psn + 1)) {
2147 set_restart_qp(qp, rcd);
2148 goto bail_stop;
2149 }
2150
2151
2152
2153
2154 if (qp->s_cur != qp->s_tail &&
2155 cmp_psn(qp->s_psn, psn) <= 0)
2156 update_qp_retry_state(qp, psn,
2157 __w->psn,
2158 __w->lpsn);
2159 else if (--qpriv->pending_tid_w_resp)
2160 rvt_mod_retry_timer(qp);
2161 else
2162 rvt_stop_rc_timers(qp);
2163 } else {
2164
2165
2166
2167
2168 rvt_mod_retry_timer(qp);
2169
2170
2171
2172
2173
2174 if (cmp_psn(qp->s_psn, psn) <= 0)
2175 reset_psn(qp, psn + 1);
2176 }
2177 } else {
2178
2179 rvt_stop_rc_timers(qp);
2180 if (cmp_psn(qp->s_psn, psn) <= 0) {
2181 qp->s_state = OP(SEND_LAST);
2182 qp->s_psn = psn + 1;
2183 }
2184 }
2185 if (qp->s_flags & RVT_S_WAIT_ACK) {
2186 qp->s_flags &= ~RVT_S_WAIT_ACK;
2187 hfi1_schedule_send(qp);
2188 }
2189 rvt_get_credit(qp, aeth);
2190 qp->s_rnr_retry = qp->s_rnr_retry_cnt;
2191 qp->s_retry = qp->s_retry_cnt;
2192
2193
2194
2195
2196
2197 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE &&
2198 opcode != TID_OP(WRITE_RESP) &&
2199 cmp_psn(psn, wqe->psn) >= 0)
2200 return 1;
2201 update_last_psn(qp, psn);
2202 return 1;
2203
2204 case 1:
2205 ibp->rvp.n_rnr_naks++;
2206 if (qp->s_acked == qp->s_tail)
2207 goto bail_stop;
2208 if (qp->s_flags & RVT_S_WAIT_RNR)
2209 goto bail_stop;
2210 rdi = ib_to_rvt(qp->ibqp.device);
2211 if (!(rdi->post_parms[wqe->wr.opcode].flags &
2212 RVT_OPERATION_IGN_RNR_CNT)) {
2213 if (qp->s_rnr_retry == 0) {
2214 status = IB_WC_RNR_RETRY_EXC_ERR;
2215 goto class_b;
2216 }
2217 if (qp->s_rnr_retry_cnt < 7 && qp->s_rnr_retry_cnt > 0)
2218 qp->s_rnr_retry--;
2219 }
2220
2221
2222
2223
2224
2225
2226
2227 if (wqe->wr.opcode == IB_WR_TID_RDMA_WRITE) {
2228 reset_psn(qp, qp->s_last_psn + 1);
2229 } else {
2230 update_last_psn(qp, psn - 1);
2231 reset_psn(qp, psn);
2232 }
2233
2234 ibp->rvp.n_rc_resends += delta_psn(qp->s_psn, psn);
2235 qp->s_flags &= ~(RVT_S_WAIT_SSN_CREDIT | RVT_S_WAIT_ACK);
2236 rvt_stop_rc_timers(qp);
2237 rvt_add_rnr_timer(qp, aeth);
2238 return 0;
2239
2240 case 3:
2241 if (qp->s_acked == qp->s_tail)
2242 goto bail_stop;
2243
2244 update_last_psn(qp, psn - 1);
2245 switch ((aeth >> IB_AETH_CREDIT_SHIFT) &
2246 IB_AETH_CREDIT_MASK) {
2247 case 0:
2248 ibp->rvp.n_seq_naks++;
2249
2250
2251
2252
2253
2254
2255 hfi1_restart_rc(qp, psn, 0);
2256 hfi1_schedule_send(qp);
2257 break;
2258
2259 case 1:
2260 status = IB_WC_REM_INV_REQ_ERR;
2261 ibp->rvp.n_other_naks++;
2262 goto class_b;
2263
2264 case 2:
2265 status = IB_WC_REM_ACCESS_ERR;
2266 ibp->rvp.n_other_naks++;
2267 goto class_b;
2268
2269 case 3:
2270 status = IB_WC_REM_OP_ERR;
2271 ibp->rvp.n_other_naks++;
2272class_b:
2273 if (qp->s_last == qp->s_acked) {
2274 if (wqe->wr.opcode == IB_WR_TID_RDMA_READ)
2275 hfi1_kern_read_tid_flow_free(qp);
2276
2277 hfi1_trdma_send_complete(qp, wqe, status);
2278 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
2279 }
2280 break;
2281
2282 default:
2283
2284 goto reserved;
2285 }
2286 qp->s_retry = qp->s_retry_cnt;
2287 qp->s_rnr_retry = qp->s_rnr_retry_cnt;
2288 goto bail_stop;
2289
2290 default:
2291reserved:
2292
2293 goto bail_stop;
2294 }
2295
2296bail_stop:
2297 rvt_stop_rc_timers(qp);
2298 return ret;
2299}
2300
2301
2302
2303
2304
2305static void rdma_seq_err(struct rvt_qp *qp, struct hfi1_ibport *ibp, u32 psn,
2306 struct hfi1_ctxtdata *rcd)
2307{
2308 struct rvt_swqe *wqe;
2309
2310 lockdep_assert_held(&qp->s_lock);
2311
2312 rvt_stop_rc_timers(qp);
2313
2314 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2315
2316 while (cmp_psn(psn, wqe->lpsn) > 0) {
2317 if (wqe->wr.opcode == IB_WR_RDMA_READ ||
2318 wqe->wr.opcode == IB_WR_TID_RDMA_READ ||
2319 wqe->wr.opcode == IB_WR_TID_RDMA_WRITE ||
2320 wqe->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP ||
2321 wqe->wr.opcode == IB_WR_ATOMIC_FETCH_AND_ADD)
2322 break;
2323 wqe = do_rc_completion(qp, wqe, ibp);
2324 }
2325
2326 ibp->rvp.n_rdma_seq++;
2327 qp->r_flags |= RVT_R_RDMAR_SEQ;
2328 hfi1_restart_rc(qp, qp->s_last_psn + 1, 0);
2329 if (list_empty(&qp->rspwait)) {
2330 qp->r_flags |= RVT_R_RSP_SEND;
2331 rvt_get_qp(qp);
2332 list_add_tail(&qp->rspwait, &rcd->qp_wait_list);
2333 }
2334}
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344static void rc_rcv_resp(struct hfi1_packet *packet)
2345{
2346 struct hfi1_ctxtdata *rcd = packet->rcd;
2347 void *data = packet->payload;
2348 u32 tlen = packet->tlen;
2349 struct rvt_qp *qp = packet->qp;
2350 struct hfi1_ibport *ibp;
2351 struct ib_other_headers *ohdr = packet->ohdr;
2352 struct rvt_swqe *wqe;
2353 enum ib_wc_status status;
2354 unsigned long flags;
2355 int diff;
2356 u64 val;
2357 u32 aeth;
2358 u32 psn = ib_bth_get_psn(packet->ohdr);
2359 u32 pmtu = qp->pmtu;
2360 u16 hdrsize = packet->hlen;
2361 u8 opcode = packet->opcode;
2362 u8 pad = packet->pad;
2363 u8 extra_bytes = pad + packet->extra_byte + (SIZE_OF_CRC << 2);
2364
2365 spin_lock_irqsave(&qp->s_lock, flags);
2366 trace_hfi1_ack(qp, psn);
2367
2368
2369 if (cmp_psn(psn, READ_ONCE(qp->s_next_psn)) >= 0)
2370 goto ack_done;
2371
2372
2373 diff = cmp_psn(psn, qp->s_last_psn);
2374 if (unlikely(diff <= 0)) {
2375
2376 if (diff == 0 && opcode == OP(ACKNOWLEDGE)) {
2377 aeth = be32_to_cpu(ohdr->u.aeth);
2378 if ((aeth >> IB_AETH_NAK_SHIFT) == 0)
2379 rvt_get_credit(qp, aeth);
2380 }
2381 goto ack_done;
2382 }
2383
2384
2385
2386
2387
2388 if (qp->r_flags & RVT_R_RDMAR_SEQ) {
2389 if (cmp_psn(psn, qp->s_last_psn + 1) != 0)
2390 goto ack_done;
2391 qp->r_flags &= ~RVT_R_RDMAR_SEQ;
2392 }
2393
2394 if (unlikely(qp->s_acked == qp->s_tail))
2395 goto ack_done;
2396 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2397 status = IB_WC_SUCCESS;
2398
2399 switch (opcode) {
2400 case OP(ACKNOWLEDGE):
2401 case OP(ATOMIC_ACKNOWLEDGE):
2402 case OP(RDMA_READ_RESPONSE_FIRST):
2403 aeth = be32_to_cpu(ohdr->u.aeth);
2404 if (opcode == OP(ATOMIC_ACKNOWLEDGE))
2405 val = ib_u64_get(&ohdr->u.at.atomic_ack_eth);
2406 else
2407 val = 0;
2408 if (!do_rc_ack(qp, aeth, psn, opcode, val, rcd) ||
2409 opcode != OP(RDMA_READ_RESPONSE_FIRST))
2410 goto ack_done;
2411 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2412 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2413 goto ack_op_err;
2414
2415
2416
2417
2418
2419 qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
2420 wqe, psn, pmtu);
2421 goto read_middle;
2422
2423 case OP(RDMA_READ_RESPONSE_MIDDLE):
2424
2425 if (unlikely(cmp_psn(psn, qp->s_last_psn + 1)))
2426 goto ack_seq_err;
2427 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2428 goto ack_op_err;
2429read_middle:
2430 if (unlikely(tlen != (hdrsize + pmtu + extra_bytes)))
2431 goto ack_len_err;
2432 if (unlikely(pmtu >= qp->s_rdma_read_len))
2433 goto ack_len_err;
2434
2435
2436
2437
2438
2439 rvt_mod_retry_timer(qp);
2440 if (qp->s_flags & RVT_S_WAIT_ACK) {
2441 qp->s_flags &= ~RVT_S_WAIT_ACK;
2442 hfi1_schedule_send(qp);
2443 }
2444
2445 if (opcode == OP(RDMA_READ_RESPONSE_MIDDLE))
2446 qp->s_retry = qp->s_retry_cnt;
2447
2448
2449
2450
2451
2452 qp->s_rdma_read_len -= pmtu;
2453 update_last_psn(qp, psn);
2454 spin_unlock_irqrestore(&qp->s_lock, flags);
2455 rvt_copy_sge(qp, &qp->s_rdma_read_sge,
2456 data, pmtu, false, false);
2457 goto bail;
2458
2459 case OP(RDMA_READ_RESPONSE_ONLY):
2460 aeth = be32_to_cpu(ohdr->u.aeth);
2461 if (!do_rc_ack(qp, aeth, psn, opcode, 0, rcd))
2462 goto ack_done;
2463
2464
2465
2466
2467 if (unlikely(tlen < (hdrsize + extra_bytes)))
2468 goto ack_len_err;
2469
2470
2471
2472
2473
2474 wqe = rvt_get_swqe_ptr(qp, qp->s_acked);
2475 qp->s_rdma_read_len = restart_sge(&qp->s_rdma_read_sge,
2476 wqe, psn, pmtu);
2477 goto read_last;
2478
2479 case OP(RDMA_READ_RESPONSE_LAST):
2480
2481 if (unlikely(cmp_psn(psn, qp->s_last_psn + 1)))
2482 goto ack_seq_err;
2483 if (unlikely(wqe->wr.opcode != IB_WR_RDMA_READ))
2484 goto ack_op_err;
2485
2486
2487
2488
2489 if (unlikely(tlen <= (hdrsize + extra_bytes)))
2490 goto ack_len_err;
2491read_last:
2492 tlen -= hdrsize + extra_bytes;
2493 if (unlikely(tlen != qp->s_rdma_read_len))
2494 goto ack_len_err;
2495 aeth = be32_to_cpu(ohdr->u.aeth);
2496 rvt_copy_sge(qp, &qp->s_rdma_read_sge,
2497 data, tlen, false, false);
2498 WARN_ON(qp->s_rdma_read_sge.num_sge);
2499 (void)do_rc_ack(qp, aeth, psn,
2500 OP(RDMA_READ_RESPONSE_LAST), 0, rcd);
2501 goto ack_done;
2502 }
2503
2504ack_op_err:
2505 status = IB_WC_LOC_QP_OP_ERR;
2506 goto ack_err;
2507
2508ack_seq_err:
2509 ibp = rcd_to_iport(rcd);
2510 rdma_seq_err(qp, ibp, psn, rcd);
2511 goto ack_done;
2512
2513ack_len_err:
2514 status = IB_WC_LOC_LEN_ERR;
2515ack_err:
2516 if (qp->s_last == qp->s_acked) {
2517 rvt_send_complete(qp, wqe, status);
2518 rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
2519 }
2520ack_done:
2521 spin_unlock_irqrestore(&qp->s_lock, flags);
2522bail:
2523 return;
2524}
2525
2526static inline void rc_cancel_ack(struct rvt_qp *qp)
2527{
2528 qp->r_adefered = 0;
2529 if (list_empty(&qp->rspwait))
2530 return;
2531 list_del_init(&qp->rspwait);
2532 qp->r_flags &= ~RVT_R_RSP_NAK;
2533 rvt_put_qp(qp);
2534}
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552static noinline int rc_rcv_error(struct ib_other_headers *ohdr, void *data,
2553 struct rvt_qp *qp, u32 opcode, u32 psn,
2554 int diff, struct hfi1_ctxtdata *rcd)
2555{
2556 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
2557 struct rvt_ack_entry *e;
2558 unsigned long flags;
2559 u8 prev;
2560 u8 mra;
2561 bool old_req;
2562
2563 trace_hfi1_rcv_error(qp, psn);
2564 if (diff > 0) {
2565
2566
2567
2568
2569
2570 if (!qp->r_nak_state) {
2571 ibp->rvp.n_rc_seqnak++;
2572 qp->r_nak_state = IB_NAK_PSN_ERROR;
2573
2574 qp->r_ack_psn = qp->r_psn;
2575
2576
2577
2578
2579
2580 rc_defered_ack(rcd, qp);
2581 }
2582 goto done;
2583 }
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601 e = NULL;
2602 old_req = true;
2603 ibp->rvp.n_rc_dupreq++;
2604
2605 spin_lock_irqsave(&qp->s_lock, flags);
2606
2607 e = find_prev_entry(qp, psn, &prev, &mra, &old_req);
2608
2609 switch (opcode) {
2610 case OP(RDMA_READ_REQUEST): {
2611 struct ib_reth *reth;
2612 u32 offset;
2613 u32 len;
2614
2615
2616
2617
2618
2619 if (!e || e->opcode != OP(RDMA_READ_REQUEST))
2620 goto unlock_done;
2621
2622 reth = &ohdr->u.rc.reth;
2623
2624
2625
2626
2627
2628
2629
2630 offset = delta_psn(psn, e->psn) * qp->pmtu;
2631 len = be32_to_cpu(reth->length);
2632 if (unlikely(offset + len != e->rdma_sge.sge_length))
2633 goto unlock_done;
2634 release_rdma_sge_mr(e);
2635 if (len != 0) {
2636 u32 rkey = be32_to_cpu(reth->rkey);
2637 u64 vaddr = get_ib_reth_vaddr(reth);
2638 int ok;
2639
2640 ok = rvt_rkey_ok(qp, &e->rdma_sge, len, vaddr, rkey,
2641 IB_ACCESS_REMOTE_READ);
2642 if (unlikely(!ok))
2643 goto unlock_done;
2644 } else {
2645 e->rdma_sge.vaddr = NULL;
2646 e->rdma_sge.length = 0;
2647 e->rdma_sge.sge_length = 0;
2648 }
2649 e->psn = psn;
2650 if (old_req)
2651 goto unlock_done;
2652 if (qp->s_acked_ack_queue == qp->s_tail_ack_queue)
2653 qp->s_acked_ack_queue = prev;
2654 qp->s_tail_ack_queue = prev;
2655 break;
2656 }
2657
2658 case OP(COMPARE_SWAP):
2659 case OP(FETCH_ADD): {
2660
2661
2662
2663
2664
2665 if (!e || e->opcode != (u8)opcode || old_req)
2666 goto unlock_done;
2667 if (qp->s_tail_ack_queue == qp->s_acked_ack_queue)
2668 qp->s_acked_ack_queue = prev;
2669 qp->s_tail_ack_queue = prev;
2670 break;
2671 }
2672
2673 default:
2674
2675
2676
2677
2678 if (!(psn & IB_BTH_REQ_ACK) || old_req)
2679 goto unlock_done;
2680
2681
2682
2683
2684 if (mra == qp->r_head_ack_queue) {
2685 spin_unlock_irqrestore(&qp->s_lock, flags);
2686 qp->r_nak_state = 0;
2687 qp->r_ack_psn = qp->r_psn - 1;
2688 goto send_ack;
2689 }
2690
2691
2692
2693
2694
2695 if (qp->s_tail_ack_queue == qp->s_acked_ack_queue)
2696 qp->s_acked_ack_queue = mra;
2697 qp->s_tail_ack_queue = mra;
2698 break;
2699 }
2700 qp->s_ack_state = OP(ACKNOWLEDGE);
2701 qp->s_flags |= RVT_S_RESP_PENDING;
2702 qp->r_nak_state = 0;
2703 hfi1_schedule_send(qp);
2704
2705unlock_done:
2706 spin_unlock_irqrestore(&qp->s_lock, flags);
2707done:
2708 return 1;
2709
2710send_ack:
2711 return 0;
2712}
2713
2714static void log_cca_event(struct hfi1_pportdata *ppd, u8 sl, u32 rlid,
2715 u32 lqpn, u32 rqpn, u8 svc_type)
2716{
2717 struct opa_hfi1_cong_log_event_internal *cc_event;
2718 unsigned long flags;
2719
2720 if (sl >= OPA_MAX_SLS)
2721 return;
2722
2723 spin_lock_irqsave(&ppd->cc_log_lock, flags);
2724
2725 ppd->threshold_cong_event_map[sl / 8] |= 1 << (sl % 8);
2726 ppd->threshold_event_counter++;
2727
2728 cc_event = &ppd->cc_events[ppd->cc_log_idx++];
2729 if (ppd->cc_log_idx == OPA_CONG_LOG_ELEMS)
2730 ppd->cc_log_idx = 0;
2731 cc_event->lqpn = lqpn & RVT_QPN_MASK;
2732 cc_event->rqpn = rqpn & RVT_QPN_MASK;
2733 cc_event->sl = sl;
2734 cc_event->svc_type = svc_type;
2735 cc_event->rlid = rlid;
2736
2737 cc_event->timestamp = ktime_get_ns() / 1024;
2738
2739 spin_unlock_irqrestore(&ppd->cc_log_lock, flags);
2740}
2741
2742void process_becn(struct hfi1_pportdata *ppd, u8 sl, u32 rlid, u32 lqpn,
2743 u32 rqpn, u8 svc_type)
2744{
2745 struct cca_timer *cca_timer;
2746 u16 ccti, ccti_incr, ccti_timer, ccti_limit;
2747 u8 trigger_threshold;
2748 struct cc_state *cc_state;
2749 unsigned long flags;
2750
2751 if (sl >= OPA_MAX_SLS)
2752 return;
2753
2754 cc_state = get_cc_state(ppd);
2755
2756 if (!cc_state)
2757 return;
2758
2759
2760
2761
2762
2763
2764 ccti_limit = cc_state->cct.ccti_limit;
2765 ccti_incr = cc_state->cong_setting.entries[sl].ccti_increase;
2766 ccti_timer = cc_state->cong_setting.entries[sl].ccti_timer;
2767 trigger_threshold =
2768 cc_state->cong_setting.entries[sl].trigger_threshold;
2769
2770 spin_lock_irqsave(&ppd->cca_timer_lock, flags);
2771
2772 cca_timer = &ppd->cca_timer[sl];
2773 if (cca_timer->ccti < ccti_limit) {
2774 if (cca_timer->ccti + ccti_incr <= ccti_limit)
2775 cca_timer->ccti += ccti_incr;
2776 else
2777 cca_timer->ccti = ccti_limit;
2778 set_link_ipg(ppd);
2779 }
2780
2781 ccti = cca_timer->ccti;
2782
2783 if (!hrtimer_active(&cca_timer->hrtimer)) {
2784
2785 unsigned long nsec = 1024 * ccti_timer;
2786
2787 hrtimer_start(&cca_timer->hrtimer, ns_to_ktime(nsec),
2788 HRTIMER_MODE_REL_PINNED);
2789 }
2790
2791 spin_unlock_irqrestore(&ppd->cca_timer_lock, flags);
2792
2793 if ((trigger_threshold != 0) && (ccti >= trigger_threshold))
2794 log_cca_event(ppd, sl, rlid, lqpn, rqpn, svc_type);
2795}
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805void hfi1_rc_rcv(struct hfi1_packet *packet)
2806{
2807 struct hfi1_ctxtdata *rcd = packet->rcd;
2808 void *data = packet->payload;
2809 u32 tlen = packet->tlen;
2810 struct rvt_qp *qp = packet->qp;
2811 struct hfi1_qp_priv *qpriv = qp->priv;
2812 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
2813 struct ib_other_headers *ohdr = packet->ohdr;
2814 u32 opcode = packet->opcode;
2815 u32 hdrsize = packet->hlen;
2816 u32 psn = ib_bth_get_psn(packet->ohdr);
2817 u32 pad = packet->pad;
2818 struct ib_wc wc;
2819 u32 pmtu = qp->pmtu;
2820 int diff;
2821 struct ib_reth *reth;
2822 unsigned long flags;
2823 int ret;
2824 bool copy_last = false, fecn;
2825 u32 rkey;
2826 u8 extra_bytes = pad + packet->extra_byte + (SIZE_OF_CRC << 2);
2827
2828 lockdep_assert_held(&qp->r_lock);
2829
2830 if (hfi1_ruc_check_hdr(ibp, packet))
2831 return;
2832
2833 fecn = process_ecn(qp, packet);
2834 opfn_trigger_conn_request(qp, be32_to_cpu(ohdr->bth[1]));
2835
2836
2837
2838
2839
2840
2841
2842 if (opcode >= OP(RDMA_READ_RESPONSE_FIRST) &&
2843 opcode <= OP(ATOMIC_ACKNOWLEDGE)) {
2844 rc_rcv_resp(packet);
2845 return;
2846 }
2847
2848
2849 diff = delta_psn(psn, qp->r_psn);
2850 if (unlikely(diff)) {
2851 if (rc_rcv_error(ohdr, data, qp, opcode, psn, diff, rcd))
2852 return;
2853 goto send_ack;
2854 }
2855
2856
2857 switch (qp->r_state) {
2858 case OP(SEND_FIRST):
2859 case OP(SEND_MIDDLE):
2860 if (opcode == OP(SEND_MIDDLE) ||
2861 opcode == OP(SEND_LAST) ||
2862 opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
2863 opcode == OP(SEND_LAST_WITH_INVALIDATE))
2864 break;
2865 goto nack_inv;
2866
2867 case OP(RDMA_WRITE_FIRST):
2868 case OP(RDMA_WRITE_MIDDLE):
2869 if (opcode == OP(RDMA_WRITE_MIDDLE) ||
2870 opcode == OP(RDMA_WRITE_LAST) ||
2871 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
2872 break;
2873 goto nack_inv;
2874
2875 default:
2876 if (opcode == OP(SEND_MIDDLE) ||
2877 opcode == OP(SEND_LAST) ||
2878 opcode == OP(SEND_LAST_WITH_IMMEDIATE) ||
2879 opcode == OP(SEND_LAST_WITH_INVALIDATE) ||
2880 opcode == OP(RDMA_WRITE_MIDDLE) ||
2881 opcode == OP(RDMA_WRITE_LAST) ||
2882 opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
2883 goto nack_inv;
2884
2885
2886
2887
2888
2889 break;
2890 }
2891
2892 if (qp->state == IB_QPS_RTR && !(qp->r_flags & RVT_R_COMM_EST))
2893 rvt_comm_est(qp);
2894
2895
2896 switch (opcode) {
2897 case OP(SEND_FIRST):
2898 ret = rvt_get_rwqe(qp, false);
2899 if (ret < 0)
2900 goto nack_op_err;
2901 if (!ret)
2902 goto rnr_nak;
2903 qp->r_rcv_len = 0;
2904 fallthrough;
2905 case OP(SEND_MIDDLE):
2906 case OP(RDMA_WRITE_MIDDLE):
2907send_middle:
2908
2909
2910
2911
2912
2913
2914 if (unlikely(tlen != (hdrsize + pmtu + extra_bytes)))
2915 goto nack_inv;
2916 qp->r_rcv_len += pmtu;
2917 if (unlikely(qp->r_rcv_len > qp->r_len))
2918 goto nack_inv;
2919 rvt_copy_sge(qp, &qp->r_sge, data, pmtu, true, false);
2920 break;
2921
2922 case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
2923
2924 ret = rvt_get_rwqe(qp, true);
2925 if (ret < 0)
2926 goto nack_op_err;
2927 if (!ret)
2928 goto rnr_nak;
2929 goto send_last_imm;
2930
2931 case OP(SEND_ONLY):
2932 case OP(SEND_ONLY_WITH_IMMEDIATE):
2933 case OP(SEND_ONLY_WITH_INVALIDATE):
2934 ret = rvt_get_rwqe(qp, false);
2935 if (ret < 0)
2936 goto nack_op_err;
2937 if (!ret)
2938 goto rnr_nak;
2939 qp->r_rcv_len = 0;
2940 if (opcode == OP(SEND_ONLY))
2941 goto no_immediate_data;
2942 if (opcode == OP(SEND_ONLY_WITH_INVALIDATE))
2943 goto send_last_inv;
2944 fallthrough;
2945 case OP(SEND_LAST_WITH_IMMEDIATE):
2946send_last_imm:
2947 wc.ex.imm_data = ohdr->u.imm_data;
2948 wc.wc_flags = IB_WC_WITH_IMM;
2949 goto send_last;
2950 case OP(SEND_LAST_WITH_INVALIDATE):
2951send_last_inv:
2952 rkey = be32_to_cpu(ohdr->u.ieth);
2953 if (rvt_invalidate_rkey(qp, rkey))
2954 goto no_immediate_data;
2955 wc.ex.invalidate_rkey = rkey;
2956 wc.wc_flags = IB_WC_WITH_INVALIDATE;
2957 goto send_last;
2958 case OP(RDMA_WRITE_LAST):
2959 copy_last = rvt_is_user_qp(qp);
2960 fallthrough;
2961 case OP(SEND_LAST):
2962no_immediate_data:
2963 wc.wc_flags = 0;
2964 wc.ex.imm_data = 0;
2965send_last:
2966
2967
2968 if (unlikely(tlen < (hdrsize + extra_bytes)))
2969 goto nack_inv;
2970
2971 tlen -= (hdrsize + extra_bytes);
2972 wc.byte_len = tlen + qp->r_rcv_len;
2973 if (unlikely(wc.byte_len > qp->r_len))
2974 goto nack_inv;
2975 rvt_copy_sge(qp, &qp->r_sge, data, tlen, true, copy_last);
2976 rvt_put_ss(&qp->r_sge);
2977 qp->r_msn++;
2978 if (!__test_and_clear_bit(RVT_R_WRID_VALID, &qp->r_aflags))
2979 break;
2980 wc.wr_id = qp->r_wr_id;
2981 wc.status = IB_WC_SUCCESS;
2982 if (opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE) ||
2983 opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
2984 wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
2985 else
2986 wc.opcode = IB_WC_RECV;
2987 wc.qp = &qp->ibqp;
2988 wc.src_qp = qp->remote_qpn;
2989 wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr) & U16_MAX;
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001 wc.sl = rdma_ah_get_sl(&qp->remote_ah_attr);
3002
3003 wc.vendor_err = 0;
3004 wc.pkey_index = 0;
3005 wc.dlid_path_bits = 0;
3006 wc.port_num = 0;
3007
3008 rvt_recv_cq(qp, &wc, ib_bth_is_solicited(ohdr));
3009 break;
3010
3011 case OP(RDMA_WRITE_ONLY):
3012 copy_last = rvt_is_user_qp(qp);
3013 fallthrough;
3014 case OP(RDMA_WRITE_FIRST):
3015 case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
3016 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_WRITE)))
3017 goto nack_inv;
3018
3019 reth = &ohdr->u.rc.reth;
3020 qp->r_len = be32_to_cpu(reth->length);
3021 qp->r_rcv_len = 0;
3022 qp->r_sge.sg_list = NULL;
3023 if (qp->r_len != 0) {
3024 u32 rkey = be32_to_cpu(reth->rkey);
3025 u64 vaddr = get_ib_reth_vaddr(reth);
3026 int ok;
3027
3028
3029 ok = rvt_rkey_ok(qp, &qp->r_sge.sge, qp->r_len, vaddr,
3030 rkey, IB_ACCESS_REMOTE_WRITE);
3031 if (unlikely(!ok))
3032 goto nack_acc;
3033 qp->r_sge.num_sge = 1;
3034 } else {
3035 qp->r_sge.num_sge = 0;
3036 qp->r_sge.sge.mr = NULL;
3037 qp->r_sge.sge.vaddr = NULL;
3038 qp->r_sge.sge.length = 0;
3039 qp->r_sge.sge.sge_length = 0;
3040 }
3041 if (opcode == OP(RDMA_WRITE_FIRST))
3042 goto send_middle;
3043 else if (opcode == OP(RDMA_WRITE_ONLY))
3044 goto no_immediate_data;
3045 ret = rvt_get_rwqe(qp, true);
3046 if (ret < 0)
3047 goto nack_op_err;
3048 if (!ret) {
3049
3050 rvt_put_ss(&qp->r_sge);
3051 goto rnr_nak;
3052 }
3053 wc.ex.imm_data = ohdr->u.rc.imm_data;
3054 wc.wc_flags = IB_WC_WITH_IMM;
3055 goto send_last;
3056
3057 case OP(RDMA_READ_REQUEST): {
3058 struct rvt_ack_entry *e;
3059 u32 len;
3060 u8 next;
3061
3062 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_READ)))
3063 goto nack_inv;
3064 next = qp->r_head_ack_queue + 1;
3065
3066 if (next > rvt_size_atomic(ib_to_rvt(qp->ibqp.device)))
3067 next = 0;
3068 spin_lock_irqsave(&qp->s_lock, flags);
3069 if (unlikely(next == qp->s_acked_ack_queue)) {
3070 if (!qp->s_ack_queue[next].sent)
3071 goto nack_inv_unlck;
3072 update_ack_queue(qp, next);
3073 }
3074 e = &qp->s_ack_queue[qp->r_head_ack_queue];
3075 release_rdma_sge_mr(e);
3076 reth = &ohdr->u.rc.reth;
3077 len = be32_to_cpu(reth->length);
3078 if (len) {
3079 u32 rkey = be32_to_cpu(reth->rkey);
3080 u64 vaddr = get_ib_reth_vaddr(reth);
3081 int ok;
3082
3083
3084 ok = rvt_rkey_ok(qp, &e->rdma_sge, len, vaddr,
3085 rkey, IB_ACCESS_REMOTE_READ);
3086 if (unlikely(!ok))
3087 goto nack_acc_unlck;
3088
3089
3090
3091
3092 qp->r_psn += rvt_div_mtu(qp, len - 1);
3093 } else {
3094 e->rdma_sge.mr = NULL;
3095 e->rdma_sge.vaddr = NULL;
3096 e->rdma_sge.length = 0;
3097 e->rdma_sge.sge_length = 0;
3098 }
3099 e->opcode = opcode;
3100 e->sent = 0;
3101 e->psn = psn;
3102 e->lpsn = qp->r_psn;
3103
3104
3105
3106
3107
3108 qp->r_msn++;
3109 qp->r_psn++;
3110 qp->r_state = opcode;
3111 qp->r_nak_state = 0;
3112 qp->r_head_ack_queue = next;
3113 qpriv->r_tid_alloc = qp->r_head_ack_queue;
3114
3115
3116 qp->s_flags |= RVT_S_RESP_PENDING;
3117 if (fecn)
3118 qp->s_flags |= RVT_S_ECN;
3119 hfi1_schedule_send(qp);
3120
3121 spin_unlock_irqrestore(&qp->s_lock, flags);
3122 return;
3123 }
3124
3125 case OP(COMPARE_SWAP):
3126 case OP(FETCH_ADD): {
3127 struct ib_atomic_eth *ateth = &ohdr->u.atomic_eth;
3128 u64 vaddr = get_ib_ateth_vaddr(ateth);
3129 bool opfn = opcode == OP(COMPARE_SWAP) &&
3130 vaddr == HFI1_VERBS_E_ATOMIC_VADDR;
3131 struct rvt_ack_entry *e;
3132 atomic64_t *maddr;
3133 u64 sdata;
3134 u32 rkey;
3135 u8 next;
3136
3137 if (unlikely(!(qp->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) &&
3138 !opfn))
3139 goto nack_inv;
3140 next = qp->r_head_ack_queue + 1;
3141 if (next > rvt_size_atomic(ib_to_rvt(qp->ibqp.device)))
3142 next = 0;
3143 spin_lock_irqsave(&qp->s_lock, flags);
3144 if (unlikely(next == qp->s_acked_ack_queue)) {
3145 if (!qp->s_ack_queue[next].sent)
3146 goto nack_inv_unlck;
3147 update_ack_queue(qp, next);
3148 }
3149 e = &qp->s_ack_queue[qp->r_head_ack_queue];
3150 release_rdma_sge_mr(e);
3151
3152 if (opfn) {
3153 opfn_conn_response(qp, e, ateth);
3154 goto ack;
3155 }
3156 if (unlikely(vaddr & (sizeof(u64) - 1)))
3157 goto nack_inv_unlck;
3158 rkey = be32_to_cpu(ateth->rkey);
3159
3160 if (unlikely(!rvt_rkey_ok(qp, &qp->r_sge.sge, sizeof(u64),
3161 vaddr, rkey,
3162 IB_ACCESS_REMOTE_ATOMIC)))
3163 goto nack_acc_unlck;
3164
3165 maddr = (atomic64_t *)qp->r_sge.sge.vaddr;
3166 sdata = get_ib_ateth_swap(ateth);
3167 e->atomic_data = (opcode == OP(FETCH_ADD)) ?
3168 (u64)atomic64_add_return(sdata, maddr) - sdata :
3169 (u64)cmpxchg((u64 *)qp->r_sge.sge.vaddr,
3170 get_ib_ateth_compare(ateth),
3171 sdata);
3172 rvt_put_mr(qp->r_sge.sge.mr);
3173 qp->r_sge.num_sge = 0;
3174ack:
3175 e->opcode = opcode;
3176 e->sent = 0;
3177 e->psn = psn;
3178 e->lpsn = psn;
3179 qp->r_msn++;
3180 qp->r_psn++;
3181 qp->r_state = opcode;
3182 qp->r_nak_state = 0;
3183 qp->r_head_ack_queue = next;
3184 qpriv->r_tid_alloc = qp->r_head_ack_queue;
3185
3186
3187 qp->s_flags |= RVT_S_RESP_PENDING;
3188 if (fecn)
3189 qp->s_flags |= RVT_S_ECN;
3190 hfi1_schedule_send(qp);
3191
3192 spin_unlock_irqrestore(&qp->s_lock, flags);
3193 return;
3194 }
3195
3196 default:
3197
3198 goto nack_inv;
3199 }
3200 qp->r_psn++;
3201 qp->r_state = opcode;
3202 qp->r_ack_psn = psn;
3203 qp->r_nak_state = 0;
3204
3205 if (psn & IB_BTH_REQ_ACK || fecn) {
3206 if (packet->numpkt == 0 || fecn ||
3207 qp->r_adefered >= HFI1_PSN_CREDIT) {
3208 rc_cancel_ack(qp);
3209 goto send_ack;
3210 }
3211 qp->r_adefered++;
3212 rc_defered_ack(rcd, qp);
3213 }
3214 return;
3215
3216rnr_nak:
3217 qp->r_nak_state = qp->r_min_rnr_timer | IB_RNR_NAK;
3218 qp->r_ack_psn = qp->r_psn;
3219
3220 rc_defered_ack(rcd, qp);
3221 return;
3222
3223nack_op_err:
3224 rvt_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
3225 qp->r_nak_state = IB_NAK_REMOTE_OPERATIONAL_ERROR;
3226 qp->r_ack_psn = qp->r_psn;
3227
3228 rc_defered_ack(rcd, qp);
3229 return;
3230
3231nack_inv_unlck:
3232 spin_unlock_irqrestore(&qp->s_lock, flags);
3233nack_inv:
3234 rvt_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
3235 qp->r_nak_state = IB_NAK_INVALID_REQUEST;
3236 qp->r_ack_psn = qp->r_psn;
3237
3238 rc_defered_ack(rcd, qp);
3239 return;
3240
3241nack_acc_unlck:
3242 spin_unlock_irqrestore(&qp->s_lock, flags);
3243nack_acc:
3244 rvt_rc_error(qp, IB_WC_LOC_PROT_ERR);
3245 qp->r_nak_state = IB_NAK_REMOTE_ACCESS_ERROR;
3246 qp->r_ack_psn = qp->r_psn;
3247send_ack:
3248 hfi1_send_rc_ack(packet, fecn);
3249}
3250
3251void hfi1_rc_hdrerr(
3252 struct hfi1_ctxtdata *rcd,
3253 struct hfi1_packet *packet,
3254 struct rvt_qp *qp)
3255{
3256 struct hfi1_ibport *ibp = rcd_to_iport(rcd);
3257 int diff;
3258 u32 opcode;
3259 u32 psn;
3260
3261 if (hfi1_ruc_check_hdr(ibp, packet))
3262 return;
3263
3264 psn = ib_bth_get_psn(packet->ohdr);
3265 opcode = ib_bth_get_opcode(packet->ohdr);
3266
3267
3268 if (opcode < IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST) {
3269 diff = delta_psn(psn, qp->r_psn);
3270 if (!qp->r_nak_state && diff >= 0) {
3271 ibp->rvp.n_rc_seqnak++;
3272 qp->r_nak_state = IB_NAK_PSN_ERROR;
3273
3274 qp->r_ack_psn = qp->r_psn;
3275
3276
3277
3278
3279
3280
3281
3282
3283 rc_defered_ack(rcd, qp);
3284 }
3285 }
3286}
3287