linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
<<
>>
Prefs
   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   3 */
   4
   5#ifndef _DPU_HW_UTIL_H
   6#define _DPU_HW_UTIL_H
   7
   8#include <linux/io.h>
   9#include <linux/slab.h>
  10#include "dpu_hw_mdss.h"
  11
  12#define REG_MASK(n)                     ((BIT(n)) - 1)
  13
  14/*
  15 * This is the common struct maintained by each sub block
  16 * for mapping the register offsets in this block to the
  17 * absoulute IO address
  18 * @base_off:     mdp register mapped offset
  19 * @blk_off:      pipe offset relative to mdss offset
  20 * @length        length of register block offset
  21 * @xin_id        xin id
  22 * @hwversion     mdss hw version number
  23 */
  24struct dpu_hw_blk_reg_map {
  25        void __iomem *base_off;
  26        u32 blk_off;
  27        u32 length;
  28        u32 xin_id;
  29        u32 hwversion;
  30        u32 log_mask;
  31};
  32
  33/**
  34 * struct dpu_hw_scaler3_de_cfg : QSEEDv3 detail enhancer configuration
  35 * @enable:         detail enhancer enable/disable
  36 * @sharpen_level1: sharpening strength for noise
  37 * @sharpen_level2: sharpening strength for signal
  38 * @ clip:          clip shift
  39 * @ limit:         limit value
  40 * @ thr_quiet:     quiet threshold
  41 * @ thr_dieout:    dieout threshold
  42 * @ thr_high:      low threshold
  43 * @ thr_high:      high threshold
  44 * @ prec_shift:    precision shift
  45 * @ adjust_a:      A-coefficients for mapping curve
  46 * @ adjust_b:      B-coefficients for mapping curve
  47 * @ adjust_c:      C-coefficients for mapping curve
  48 */
  49struct dpu_hw_scaler3_de_cfg {
  50        u32 enable;
  51        int16_t sharpen_level1;
  52        int16_t sharpen_level2;
  53        uint16_t clip;
  54        uint16_t limit;
  55        uint16_t thr_quiet;
  56        uint16_t thr_dieout;
  57        uint16_t thr_low;
  58        uint16_t thr_high;
  59        uint16_t prec_shift;
  60        int16_t adjust_a[DPU_MAX_DE_CURVES];
  61        int16_t adjust_b[DPU_MAX_DE_CURVES];
  62        int16_t adjust_c[DPU_MAX_DE_CURVES];
  63};
  64
  65
  66/**
  67 * struct dpu_hw_scaler3_cfg : QSEEDv3 configuration
  68 * @enable:        scaler enable
  69 * @dir_en:        direction detection block enable
  70 * @ init_phase_x: horizontal initial phase
  71 * @ phase_step_x: horizontal phase step
  72 * @ init_phase_y: vertical initial phase
  73 * @ phase_step_y: vertical phase step
  74 * @ preload_x:    horizontal preload value
  75 * @ preload_y:    vertical preload value
  76 * @ src_width:    source width
  77 * @ src_height:   source height
  78 * @ dst_width:    destination width
  79 * @ dst_height:   destination height
  80 * @ y_rgb_filter_cfg: y/rgb plane filter configuration
  81 * @ uv_filter_cfg: uv plane filter configuration
  82 * @ alpha_filter_cfg: alpha filter configuration
  83 * @ blend_cfg:    blend coefficients configuration
  84 * @ lut_flag:     scaler LUT update flags
  85 *                 0x1 swap LUT bank
  86 *                 0x2 update 2D filter LUT
  87 *                 0x4 update y circular filter LUT
  88 *                 0x8 update uv circular filter LUT
  89 *                 0x10 update y separable filter LUT
  90 *                 0x20 update uv separable filter LUT
  91 * @ dir_lut_idx:  2D filter LUT index
  92 * @ y_rgb_cir_lut_idx: y circular filter LUT index
  93 * @ uv_cir_lut_idx: uv circular filter LUT index
  94 * @ y_rgb_sep_lut_idx: y circular filter LUT index
  95 * @ uv_sep_lut_idx: uv separable filter LUT index
  96 * @ dir_lut:      pointer to 2D LUT
  97 * @ cir_lut:      pointer to circular filter LUT
  98 * @ sep_lut:      pointer to separable filter LUT
  99 * @ de: detail enhancer configuration
 100 * @ dir_weight:   Directional weight
 101 */
 102struct dpu_hw_scaler3_cfg {
 103        u32 enable;
 104        u32 dir_en;
 105        int32_t init_phase_x[DPU_MAX_PLANES];
 106        int32_t phase_step_x[DPU_MAX_PLANES];
 107        int32_t init_phase_y[DPU_MAX_PLANES];
 108        int32_t phase_step_y[DPU_MAX_PLANES];
 109
 110        u32 preload_x[DPU_MAX_PLANES];
 111        u32 preload_y[DPU_MAX_PLANES];
 112        u32 src_width[DPU_MAX_PLANES];
 113        u32 src_height[DPU_MAX_PLANES];
 114
 115        u32 dst_width;
 116        u32 dst_height;
 117
 118        u32 y_rgb_filter_cfg;
 119        u32 uv_filter_cfg;
 120        u32 alpha_filter_cfg;
 121        u32 blend_cfg;
 122
 123        u32 lut_flag;
 124        u32 dir_lut_idx;
 125
 126        u32 y_rgb_cir_lut_idx;
 127        u32 uv_cir_lut_idx;
 128        u32 y_rgb_sep_lut_idx;
 129        u32 uv_sep_lut_idx;
 130        u32 *dir_lut;
 131        size_t dir_len;
 132        u32 *cir_lut;
 133        size_t cir_len;
 134        u32 *sep_lut;
 135        size_t sep_len;
 136
 137        /*
 138         * Detail enhancer settings
 139         */
 140        struct dpu_hw_scaler3_de_cfg de;
 141
 142        u32 dir_weight;
 143};
 144
 145/**
 146 * struct dpu_drm_pix_ext_v1 - version 1 of pixel ext structure
 147 * @num_ext_pxls_lr: Number of total horizontal pixels
 148 * @num_ext_pxls_tb: Number of total vertical lines
 149 * @left_ftch:       Number of extra pixels to overfetch from left
 150 * @right_ftch:      Number of extra pixels to overfetch from right
 151 * @top_ftch:        Number of extra lines to overfetch from top
 152 * @btm_ftch:        Number of extra lines to overfetch from bottom
 153 * @left_rpt:        Number of extra pixels to repeat from left
 154 * @right_rpt:       Number of extra pixels to repeat from right
 155 * @top_rpt:         Number of extra lines to repeat from top
 156 * @btm_rpt:         Number of extra lines to repeat from bottom
 157 */
 158struct dpu_drm_pix_ext_v1 {
 159        /*
 160         * Number of pixels ext in left, right, top and bottom direction
 161         * for all color components.
 162         */
 163        int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
 164        int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
 165
 166        /*
 167         * Number of pixels needs to be overfetched in left, right, top
 168         * and bottom directions from source image for scaling.
 169         */
 170        int32_t left_ftch[DPU_MAX_PLANES];
 171        int32_t right_ftch[DPU_MAX_PLANES];
 172        int32_t top_ftch[DPU_MAX_PLANES];
 173        int32_t btm_ftch[DPU_MAX_PLANES];
 174        /*
 175         * Number of pixels needs to be repeated in left, right, top and
 176         * bottom directions for scaling.
 177         */
 178        int32_t left_rpt[DPU_MAX_PLANES];
 179        int32_t right_rpt[DPU_MAX_PLANES];
 180        int32_t top_rpt[DPU_MAX_PLANES];
 181        int32_t btm_rpt[DPU_MAX_PLANES];
 182
 183};
 184
 185/**
 186 * struct dpu_drm_de_v1 - version 1 of detail enhancer structure
 187 * @enable:         Enables/disables detail enhancer
 188 * @sharpen_level1: Sharpening strength for noise
 189 * @sharpen_level2: Sharpening strength for context
 190 * @clip:           Clip coefficient
 191 * @limit:          Detail enhancer limit factor
 192 * @thr_quiet:      Quite zone threshold
 193 * @thr_dieout:     Die-out zone threshold
 194 * @thr_low:        Linear zone left threshold
 195 * @thr_high:       Linear zone right threshold
 196 * @prec_shift:     Detail enhancer precision
 197 * @adjust_a:       Mapping curves A coefficients
 198 * @adjust_b:       Mapping curves B coefficients
 199 * @adjust_c:       Mapping curves C coefficients
 200 */
 201struct dpu_drm_de_v1 {
 202        uint32_t enable;
 203        int16_t sharpen_level1;
 204        int16_t sharpen_level2;
 205        uint16_t clip;
 206        uint16_t limit;
 207        uint16_t thr_quiet;
 208        uint16_t thr_dieout;
 209        uint16_t thr_low;
 210        uint16_t thr_high;
 211        uint16_t prec_shift;
 212        int16_t adjust_a[DPU_MAX_DE_CURVES];
 213        int16_t adjust_b[DPU_MAX_DE_CURVES];
 214        int16_t adjust_c[DPU_MAX_DE_CURVES];
 215};
 216
 217/**
 218 * struct dpu_drm_scaler_v2 - version 2 of struct dpu_drm_scaler
 219 * @enable:            Scaler enable
 220 * @dir_en:            Detail enhancer enable
 221 * @pe:                Pixel extension settings
 222 * @horz_decimate:     Horizontal decimation factor
 223 * @vert_decimate:     Vertical decimation factor
 224 * @init_phase_x:      Initial scaler phase values for x
 225 * @phase_step_x:      Phase step values for x
 226 * @init_phase_y:      Initial scaler phase values for y
 227 * @phase_step_y:      Phase step values for y
 228 * @preload_x:         Horizontal preload value
 229 * @preload_y:         Vertical preload value
 230 * @src_width:         Source width
 231 * @src_height:        Source height
 232 * @dst_width:         Destination width
 233 * @dst_height:        Destination height
 234 * @y_rgb_filter_cfg:  Y/RGB plane filter configuration
 235 * @uv_filter_cfg:     UV plane filter configuration
 236 * @alpha_filter_cfg:  Alpha filter configuration
 237 * @blend_cfg:         Selection of blend coefficients
 238 * @lut_flag:          LUT configuration flags
 239 * @dir_lut_idx:       2d 4x4 LUT index
 240 * @y_rgb_cir_lut_idx: Y/RGB circular LUT index
 241 * @uv_cir_lut_idx:    UV circular LUT index
 242 * @y_rgb_sep_lut_idx: Y/RGB separable LUT index
 243 * @uv_sep_lut_idx:    UV separable LUT index
 244 * @de:                Detail enhancer settings
 245 */
 246struct dpu_drm_scaler_v2 {
 247        /*
 248         * General definitions
 249         */
 250        uint32_t enable;
 251        uint32_t dir_en;
 252
 253        /*
 254         * Pix ext settings
 255         */
 256        struct dpu_drm_pix_ext_v1 pe;
 257
 258        /*
 259         * Decimation settings
 260         */
 261        uint32_t horz_decimate;
 262        uint32_t vert_decimate;
 263
 264        /*
 265         * Phase settings
 266         */
 267        int32_t init_phase_x[DPU_MAX_PLANES];
 268        int32_t phase_step_x[DPU_MAX_PLANES];
 269        int32_t init_phase_y[DPU_MAX_PLANES];
 270        int32_t phase_step_y[DPU_MAX_PLANES];
 271
 272        uint32_t preload_x[DPU_MAX_PLANES];
 273        uint32_t preload_y[DPU_MAX_PLANES];
 274        uint32_t src_width[DPU_MAX_PLANES];
 275        uint32_t src_height[DPU_MAX_PLANES];
 276
 277        uint32_t dst_width;
 278        uint32_t dst_height;
 279
 280        uint32_t y_rgb_filter_cfg;
 281        uint32_t uv_filter_cfg;
 282        uint32_t alpha_filter_cfg;
 283        uint32_t blend_cfg;
 284
 285        uint32_t lut_flag;
 286        uint32_t dir_lut_idx;
 287
 288        /* for Y(RGB) and UV planes*/
 289        uint32_t y_rgb_cir_lut_idx;
 290        uint32_t uv_cir_lut_idx;
 291        uint32_t y_rgb_sep_lut_idx;
 292        uint32_t uv_sep_lut_idx;
 293
 294        /*
 295         * Detail enhancer settings
 296         */
 297        struct dpu_drm_de_v1 de;
 298};
 299
 300
 301u32 *dpu_hw_util_get_log_mask_ptr(void);
 302
 303void dpu_reg_write(struct dpu_hw_blk_reg_map *c,
 304                u32 reg_off,
 305                u32 val,
 306                const char *name);
 307int dpu_reg_read(struct dpu_hw_blk_reg_map *c, u32 reg_off);
 308
 309#define DPU_REG_WRITE(c, off, val) dpu_reg_write(c, off, val, #off)
 310#define DPU_REG_READ(c, off) dpu_reg_read(c, off)
 311
 312void *dpu_hw_util_get_dir(void);
 313
 314void dpu_hw_setup_scaler3(struct dpu_hw_blk_reg_map *c,
 315                struct dpu_hw_scaler3_cfg *scaler3_cfg,
 316                u32 scaler_offset, u32 scaler_version,
 317                const struct dpu_format *format);
 318
 319u32 dpu_hw_get_scaler3_ver(struct dpu_hw_blk_reg_map *c,
 320                u32 scaler_offset);
 321
 322void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map  *c,
 323                u32 csc_reg_off,
 324                struct dpu_csc_cfg *data, bool csc10);
 325
 326#endif /* _DPU_HW_UTIL_H */
 327