linux/drivers/gpu/drm/i915/selftests/intel_uncore.c
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   1/*
   2 * Copyright © 2016 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 *
  23 */
  24
  25#include "../i915_selftest.h"
  26
  27static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
  28                                unsigned int num_ranges,
  29                                bool is_watertight)
  30{
  31        unsigned int i;
  32        s32 prev;
  33
  34        for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
  35                /* Check that the table is watertight */
  36                if (is_watertight && (prev + 1) != (s32)ranges->start) {
  37                        pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
  38                               __func__, i, ranges->start, ranges->end, prev);
  39                        return -EINVAL;
  40                }
  41
  42                /* Check that the table never goes backwards */
  43                if (prev >= (s32)ranges->start) {
  44                        pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
  45                               __func__, i, ranges->start, ranges->end, prev);
  46                        return -EINVAL;
  47                }
  48
  49                /* Check that the entry is valid */
  50                if (ranges->start >= ranges->end) {
  51                        pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
  52                               __func__, i, ranges->start, ranges->end);
  53                        return -EINVAL;
  54                }
  55
  56                prev = ranges->end;
  57        }
  58
  59        return 0;
  60}
  61
  62static int intel_shadow_table_check(void)
  63{
  64        struct {
  65                const i915_reg_t *regs;
  66                unsigned int size;
  67        } reg_lists[] = {
  68                { gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
  69                { gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
  70                { gen12_shadowed_regs, ARRAY_SIZE(gen12_shadowed_regs) },
  71        };
  72        const i915_reg_t *reg;
  73        unsigned int i, j;
  74        s32 prev;
  75
  76        for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
  77                reg = reg_lists[j].regs;
  78                for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
  79                        u32 offset = i915_mmio_reg_offset(*reg);
  80
  81                        if (prev >= (s32)offset) {
  82                                pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
  83                                       __func__, i, offset, prev);
  84                                return -EINVAL;
  85                        }
  86
  87                        prev = offset;
  88                }
  89        }
  90
  91        return 0;
  92}
  93
  94int intel_uncore_mock_selftests(void)
  95{
  96        struct {
  97                const struct intel_forcewake_range *ranges;
  98                unsigned int num_ranges;
  99                bool is_watertight;
 100        } fw[] = {
 101                { __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
 102                { __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
 103                { __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
 104                { __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
 105                { __gen12_fw_ranges, ARRAY_SIZE(__gen12_fw_ranges), true },
 106        };
 107        int err, i;
 108
 109        for (i = 0; i < ARRAY_SIZE(fw); i++) {
 110                err = intel_fw_table_check(fw[i].ranges,
 111                                           fw[i].num_ranges,
 112                                           fw[i].is_watertight);
 113                if (err)
 114                        return err;
 115        }
 116
 117        err = intel_shadow_table_check();
 118        if (err)
 119                return err;
 120
 121        return 0;
 122}
 123
 124static int live_forcewake_ops(void *arg)
 125{
 126        static const struct reg {
 127                const char *name;
 128                u8 min_graphics_ver;
 129                u8 max_graphics_ver;
 130                unsigned long platforms;
 131                unsigned int offset;
 132        } registers[] = {
 133                {
 134                        "RING_START",
 135                        6, 7,
 136                        0x38,
 137                },
 138                {
 139                        "RING_MI_MODE",
 140                        8, U8_MAX,
 141                        0x9c,
 142                }
 143        };
 144        const struct reg *r;
 145        struct intel_gt *gt = arg;
 146        struct intel_uncore_forcewake_domain *domain;
 147        struct intel_uncore *uncore = gt->uncore;
 148        struct intel_engine_cs *engine;
 149        enum intel_engine_id id;
 150        intel_wakeref_t wakeref;
 151        unsigned int tmp;
 152        int err = 0;
 153
 154        GEM_BUG_ON(gt->awake);
 155
 156        /* vlv/chv with their pcu behave differently wrt reads */
 157        if (IS_VALLEYVIEW(gt->i915) || IS_CHERRYVIEW(gt->i915)) {
 158                pr_debug("PCU fakes forcewake badly; skipping\n");
 159                return 0;
 160        }
 161
 162        /*
 163         * Not quite as reliable across the gen as one would hope.
 164         *
 165         * Either our theory of operation is incorrect, or there remain
 166         * external parties interfering with the powerwells.
 167         *
 168         * https://bugs.freedesktop.org/show_bug.cgi?id=110210
 169         */
 170        if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
 171                return 0;
 172
 173        /* We have to pick carefully to get the exact behaviour we need */
 174        for (r = registers; r->name; r++)
 175                if (IS_GRAPHICS_VER(gt->i915, r->min_graphics_ver, r->max_graphics_ver))
 176                        break;
 177        if (!r->name) {
 178                pr_debug("Forcewaked register not known for %s; skipping\n",
 179                         intel_platform_name(INTEL_INFO(gt->i915)->platform));
 180                return 0;
 181        }
 182
 183        wakeref = intel_runtime_pm_get(uncore->rpm);
 184
 185        for_each_fw_domain(domain, uncore, tmp) {
 186                smp_store_mb(domain->active, false);
 187                if (!hrtimer_cancel(&domain->timer))
 188                        continue;
 189
 190                intel_uncore_fw_release_timer(&domain->timer);
 191        }
 192
 193        for_each_engine(engine, gt, id) {
 194                i915_reg_t mmio = _MMIO(engine->mmio_base + r->offset);
 195                u32 __iomem *reg = uncore->regs + engine->mmio_base + r->offset;
 196                enum forcewake_domains fw_domains;
 197                u32 val;
 198
 199                if (!engine->default_state)
 200                        continue;
 201
 202                fw_domains = intel_uncore_forcewake_for_reg(uncore, mmio,
 203                                                            FW_REG_READ);
 204                if (!fw_domains)
 205                        continue;
 206
 207                for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 208                        if (!domain->wake_count)
 209                                continue;
 210
 211                        pr_err("fw_domain %s still active, aborting test!\n",
 212                               intel_uncore_forcewake_domain_to_str(domain->id));
 213                        err = -EINVAL;
 214                        goto out_rpm;
 215                }
 216
 217                intel_uncore_forcewake_get(uncore, fw_domains);
 218                val = readl(reg);
 219                intel_uncore_forcewake_put(uncore, fw_domains);
 220
 221                /* Flush the forcewake release (delayed onto a timer) */
 222                for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) {
 223                        smp_store_mb(domain->active, false);
 224                        if (hrtimer_cancel(&domain->timer))
 225                                intel_uncore_fw_release_timer(&domain->timer);
 226
 227                        preempt_disable();
 228                        err = wait_ack_clear(domain, FORCEWAKE_KERNEL);
 229                        preempt_enable();
 230                        if (err) {
 231                                pr_err("Failed to clear fw_domain %s\n",
 232                                       intel_uncore_forcewake_domain_to_str(domain->id));
 233                                goto out_rpm;
 234                        }
 235                }
 236
 237                if (!val) {
 238                        pr_err("%s:%s was zero while fw was held!\n",
 239                               engine->name, r->name);
 240                        err = -EINVAL;
 241                        goto out_rpm;
 242                }
 243
 244                /* We then expect the read to return 0 outside of the fw */
 245                if (wait_for(readl(reg) == 0, 100)) {
 246                        pr_err("%s:%s=%0x, fw_domains 0x%x still up after 100ms!\n",
 247                               engine->name, r->name, readl(reg), fw_domains);
 248                        err = -ETIMEDOUT;
 249                        goto out_rpm;
 250                }
 251        }
 252
 253out_rpm:
 254        intel_runtime_pm_put(uncore->rpm, wakeref);
 255        return err;
 256}
 257
 258static int live_forcewake_domains(void *arg)
 259{
 260#define FW_RANGE 0x40000
 261        struct intel_gt *gt = arg;
 262        struct intel_uncore *uncore = gt->uncore;
 263        unsigned long *valid;
 264        u32 offset;
 265        int err;
 266
 267        if (!HAS_FPGA_DBG_UNCLAIMED(gt->i915) &&
 268            !IS_VALLEYVIEW(gt->i915) &&
 269            !IS_CHERRYVIEW(gt->i915))
 270                return 0;
 271
 272        /*
 273         * This test may lockup the machine or cause GPU hangs afterwards.
 274         */
 275        if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
 276                return 0;
 277
 278        valid = bitmap_zalloc(FW_RANGE, GFP_KERNEL);
 279        if (!valid)
 280                return -ENOMEM;
 281
 282        intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 283
 284        check_for_unclaimed_mmio(uncore);
 285        for (offset = 0; offset < FW_RANGE; offset += 4) {
 286                i915_reg_t reg = { offset };
 287
 288                intel_uncore_posting_read_fw(uncore, reg);
 289                if (!check_for_unclaimed_mmio(uncore))
 290                        set_bit(offset, valid);
 291        }
 292
 293        intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 294
 295        err = 0;
 296        for_each_set_bit(offset, valid, FW_RANGE) {
 297                i915_reg_t reg = { offset };
 298
 299                iosf_mbi_punit_acquire();
 300                intel_uncore_forcewake_reset(uncore);
 301                iosf_mbi_punit_release();
 302
 303                check_for_unclaimed_mmio(uncore);
 304
 305                intel_uncore_posting_read_fw(uncore, reg);
 306                if (check_for_unclaimed_mmio(uncore)) {
 307                        pr_err("Unclaimed mmio read to register 0x%04x\n",
 308                               offset);
 309                        err = -EINVAL;
 310                }
 311        }
 312
 313        bitmap_free(valid);
 314        return err;
 315}
 316
 317static int live_fw_table(void *arg)
 318{
 319        struct intel_gt *gt = arg;
 320
 321        /* Confirm the table we load is still valid */
 322        return intel_fw_table_check(gt->uncore->fw_domains_table,
 323                                    gt->uncore->fw_domains_table_entries,
 324                                    GRAPHICS_VER(gt->i915) >= 9);
 325}
 326
 327int intel_uncore_live_selftests(struct drm_i915_private *i915)
 328{
 329        static const struct i915_subtest tests[] = {
 330                SUBTEST(live_fw_table),
 331                SUBTEST(live_forcewake_ops),
 332                SUBTEST(live_forcewake_domains),
 333        };
 334
 335        return intel_gt_live_subtests(tests, &i915->gt);
 336}
 337