linux/drivers/gpu/drm/i915/display/intel_tc.c
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   1// SPDX-License-Identifier: MIT
   2/*
   3 * Copyright © 2019 Intel Corporation
   4 */
   5
   6#include "i915_drv.h"
   7#include "intel_display.h"
   8#include "intel_display_types.h"
   9#include "intel_dp_mst.h"
  10#include "intel_tc.h"
  11
  12static const char *tc_port_mode_name(enum tc_port_mode mode)
  13{
  14        static const char * const names[] = {
  15                [TC_PORT_TBT_ALT] = "tbt-alt",
  16                [TC_PORT_DP_ALT] = "dp-alt",
  17                [TC_PORT_LEGACY] = "legacy",
  18        };
  19
  20        if (WARN_ON(mode >= ARRAY_SIZE(names)))
  21                mode = TC_PORT_TBT_ALT;
  22
  23        return names[mode];
  24}
  25
  26static enum intel_display_power_domain
  27tc_cold_get_power_domain(struct intel_digital_port *dig_port)
  28{
  29        if (intel_tc_cold_requires_aux_pw(dig_port))
  30                return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
  31        else
  32                return POWER_DOMAIN_TC_COLD_OFF;
  33}
  34
  35static intel_wakeref_t
  36tc_cold_block(struct intel_digital_port *dig_port)
  37{
  38        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  39        enum intel_display_power_domain domain;
  40
  41        if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
  42                return 0;
  43
  44        domain = tc_cold_get_power_domain(dig_port);
  45        return intel_display_power_get(i915, domain);
  46}
  47
  48static void
  49tc_cold_unblock(struct intel_digital_port *dig_port, intel_wakeref_t wakeref)
  50{
  51        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  52        enum intel_display_power_domain domain;
  53
  54        /*
  55         * wakeref == -1, means some error happened saving save_depot_stack but
  56         * power should still be put down and 0 is a invalid save_depot_stack
  57         * id so can be used to skip it for non TC legacy ports.
  58         */
  59        if (wakeref == 0)
  60                return;
  61
  62        domain = tc_cold_get_power_domain(dig_port);
  63        intel_display_power_put_async(i915, domain, wakeref);
  64}
  65
  66static void
  67assert_tc_cold_blocked(struct intel_digital_port *dig_port)
  68{
  69        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  70        bool enabled;
  71
  72        if (DISPLAY_VER(i915) == 11 && !dig_port->tc_legacy_port)
  73                return;
  74
  75        enabled = intel_display_power_is_enabled(i915,
  76                                                 tc_cold_get_power_domain(dig_port));
  77        drm_WARN_ON(&i915->drm, !enabled);
  78}
  79
  80u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
  81{
  82        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  83        struct intel_uncore *uncore = &i915->uncore;
  84        u32 lane_mask;
  85
  86        lane_mask = intel_uncore_read(uncore,
  87                                      PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
  88
  89        drm_WARN_ON(&i915->drm, lane_mask == 0xffffffff);
  90        assert_tc_cold_blocked(dig_port);
  91
  92        lane_mask &= DP_LANE_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx);
  93        return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
  94}
  95
  96u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
  97{
  98        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
  99        struct intel_uncore *uncore = &i915->uncore;
 100        u32 pin_mask;
 101
 102        pin_mask = intel_uncore_read(uncore,
 103                                     PORT_TX_DFLEXPA1(dig_port->tc_phy_fia));
 104
 105        drm_WARN_ON(&i915->drm, pin_mask == 0xffffffff);
 106        assert_tc_cold_blocked(dig_port);
 107
 108        return (pin_mask & DP_PIN_ASSIGNMENT_MASK(dig_port->tc_phy_fia_idx)) >>
 109               DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx);
 110}
 111
 112int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port)
 113{
 114        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 115        intel_wakeref_t wakeref;
 116        u32 lane_mask;
 117
 118        if (dig_port->tc_mode != TC_PORT_DP_ALT)
 119                return 4;
 120
 121        assert_tc_cold_blocked(dig_port);
 122
 123        lane_mask = 0;
 124        with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
 125                lane_mask = intel_tc_port_get_lane_mask(dig_port);
 126
 127        switch (lane_mask) {
 128        default:
 129                MISSING_CASE(lane_mask);
 130                fallthrough;
 131        case 0x1:
 132        case 0x2:
 133        case 0x4:
 134        case 0x8:
 135                return 1;
 136        case 0x3:
 137        case 0xc:
 138                return 2;
 139        case 0xf:
 140                return 4;
 141        }
 142}
 143
 144void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
 145                                      int required_lanes)
 146{
 147        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 148        bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
 149        struct intel_uncore *uncore = &i915->uncore;
 150        u32 val;
 151
 152        drm_WARN_ON(&i915->drm,
 153                    lane_reversal && dig_port->tc_mode != TC_PORT_LEGACY);
 154
 155        assert_tc_cold_blocked(dig_port);
 156
 157        val = intel_uncore_read(uncore,
 158                                PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia));
 159        val &= ~DFLEXDPMLE1_DPMLETC_MASK(dig_port->tc_phy_fia_idx);
 160
 161        switch (required_lanes) {
 162        case 1:
 163                val |= lane_reversal ?
 164                        DFLEXDPMLE1_DPMLETC_ML3(dig_port->tc_phy_fia_idx) :
 165                        DFLEXDPMLE1_DPMLETC_ML0(dig_port->tc_phy_fia_idx);
 166                break;
 167        case 2:
 168                val |= lane_reversal ?
 169                        DFLEXDPMLE1_DPMLETC_ML3_2(dig_port->tc_phy_fia_idx) :
 170                        DFLEXDPMLE1_DPMLETC_ML1_0(dig_port->tc_phy_fia_idx);
 171                break;
 172        case 4:
 173                val |= DFLEXDPMLE1_DPMLETC_ML3_0(dig_port->tc_phy_fia_idx);
 174                break;
 175        default:
 176                MISSING_CASE(required_lanes);
 177        }
 178
 179        intel_uncore_write(uncore,
 180                           PORT_TX_DFLEXDPMLE1(dig_port->tc_phy_fia), val);
 181}
 182
 183static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
 184                                      u32 live_status_mask)
 185{
 186        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 187        u32 valid_hpd_mask;
 188
 189        if (dig_port->tc_legacy_port)
 190                valid_hpd_mask = BIT(TC_PORT_LEGACY);
 191        else
 192                valid_hpd_mask = BIT(TC_PORT_DP_ALT) |
 193                                 BIT(TC_PORT_TBT_ALT);
 194
 195        if (!(live_status_mask & ~valid_hpd_mask))
 196                return;
 197
 198        /* If live status mismatches the VBT flag, trust the live status. */
 199        drm_dbg_kms(&i915->drm,
 200                    "Port %s: live status %08x mismatches the legacy port flag %08x, fixing flag\n",
 201                    dig_port->tc_port_name, live_status_mask, valid_hpd_mask);
 202
 203        dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
 204}
 205
 206static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
 207{
 208        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 209        struct intel_uncore *uncore = &i915->uncore;
 210        u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
 211        u32 mask = 0;
 212        u32 val;
 213
 214        val = intel_uncore_read(uncore,
 215                                PORT_TX_DFLEXDPSP(dig_port->tc_phy_fia));
 216
 217        if (val == 0xffffffff) {
 218                drm_dbg_kms(&i915->drm,
 219                            "Port %s: PHY in TCCOLD, nothing connected\n",
 220                            dig_port->tc_port_name);
 221                return mask;
 222        }
 223
 224        if (val & TC_LIVE_STATE_TBT(dig_port->tc_phy_fia_idx))
 225                mask |= BIT(TC_PORT_TBT_ALT);
 226        if (val & TC_LIVE_STATE_TC(dig_port->tc_phy_fia_idx))
 227                mask |= BIT(TC_PORT_DP_ALT);
 228
 229        if (intel_uncore_read(uncore, SDEISR) & isr_bit)
 230                mask |= BIT(TC_PORT_LEGACY);
 231
 232        /* The sink can be connected only in a single mode. */
 233        if (!drm_WARN_ON_ONCE(&i915->drm, hweight32(mask) > 1))
 234                tc_port_fixup_legacy_flag(dig_port, mask);
 235
 236        return mask;
 237}
 238
 239static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
 240{
 241        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 242        enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
 243        u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
 244        struct intel_uncore *uncore = &i915->uncore;
 245        u32 val, mask = 0;
 246
 247        val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
 248        if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
 249                mask |= BIT(TC_PORT_DP_ALT);
 250        if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
 251                mask |= BIT(TC_PORT_TBT_ALT);
 252
 253        if (intel_uncore_read(uncore, SDEISR) & isr_bit)
 254                mask |= BIT(TC_PORT_LEGACY);
 255
 256        /* The sink can be connected only in a single mode. */
 257        if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1))
 258                tc_port_fixup_legacy_flag(dig_port, mask);
 259
 260        return mask;
 261}
 262
 263static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
 264{
 265        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 266
 267        if (IS_ALDERLAKE_P(i915))
 268                return adl_tc_port_live_status_mask(dig_port);
 269
 270        return icl_tc_port_live_status_mask(dig_port);
 271}
 272
 273static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
 274{
 275        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 276        struct intel_uncore *uncore = &i915->uncore;
 277        u32 val;
 278
 279        val = intel_uncore_read(uncore,
 280                                PORT_TX_DFLEXDPPMS(dig_port->tc_phy_fia));
 281        if (val == 0xffffffff) {
 282                drm_dbg_kms(&i915->drm,
 283                            "Port %s: PHY in TCCOLD, assuming not complete\n",
 284                            dig_port->tc_port_name);
 285                return false;
 286        }
 287
 288        return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
 289}
 290
 291static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
 292{
 293        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 294        struct intel_uncore *uncore = &i915->uncore;
 295        u32 val;
 296
 297        val = intel_uncore_read(uncore, TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
 298        if (val == 0xffffffff) {
 299                drm_dbg_kms(&i915->drm,
 300                            "Port %s: PHY in TCCOLD, assuming not complete\n",
 301                            dig_port->tc_port_name);
 302                return false;
 303        }
 304
 305        return val & TCSS_DDI_STATUS_READY;
 306}
 307
 308static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
 309{
 310        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 311
 312        if (IS_ALDERLAKE_P(i915))
 313                return adl_tc_phy_status_complete(dig_port);
 314
 315        return icl_tc_phy_status_complete(dig_port);
 316}
 317
 318static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
 319                                      bool take)
 320{
 321        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 322        struct intel_uncore *uncore = &i915->uncore;
 323        u32 val;
 324
 325        val = intel_uncore_read(uncore,
 326                                PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
 327        if (val == 0xffffffff) {
 328                drm_dbg_kms(&i915->drm,
 329                            "Port %s: PHY in TCCOLD, can't %s ownership\n",
 330                            dig_port->tc_port_name, take ? "take" : "release");
 331
 332                return false;
 333        }
 334
 335        val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
 336        if (take)
 337                val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
 338
 339        intel_uncore_write(uncore,
 340                           PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
 341
 342        if (!take && wait_for(!tc_phy_status_complete(dig_port), 10))
 343                drm_dbg_kms(&i915->drm,
 344                            "Port %s: PHY complete clear timed out\n",
 345                            dig_port->tc_port_name);
 346
 347        return true;
 348}
 349
 350static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
 351                                      bool take)
 352{
 353        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 354        struct intel_uncore *uncore = &i915->uncore;
 355        enum port port = dig_port->base.port;
 356        u32 val;
 357
 358        val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
 359        if (take)
 360                val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 361        else
 362                val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 363        intel_uncore_write(uncore, DDI_BUF_CTL(port), val);
 364
 365        return true;
 366}
 367
 368static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take)
 369{
 370        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 371
 372        if (IS_ALDERLAKE_P(i915))
 373                return adl_tc_phy_take_ownership(dig_port, take);
 374
 375        return icl_tc_phy_take_ownership(dig_port, take);
 376}
 377
 378static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
 379{
 380        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 381        struct intel_uncore *uncore = &i915->uncore;
 382        u32 val;
 383
 384        val = intel_uncore_read(uncore,
 385                                PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
 386        if (val == 0xffffffff) {
 387                drm_dbg_kms(&i915->drm,
 388                            "Port %s: PHY in TCCOLD, assume safe mode\n",
 389                            dig_port->tc_port_name);
 390                return true;
 391        }
 392
 393        return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
 394}
 395
 396static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
 397{
 398        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 399        struct intel_uncore *uncore = &i915->uncore;
 400        enum port port = dig_port->base.port;
 401        u32 val;
 402
 403        val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
 404        return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 405}
 406
 407static bool tc_phy_is_owned(struct intel_digital_port *dig_port)
 408{
 409        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 410
 411        if (IS_ALDERLAKE_P(i915))
 412                return adl_tc_phy_is_owned(dig_port);
 413
 414        return icl_tc_phy_is_owned(dig_port);
 415}
 416
 417/*
 418 * This function implements the first part of the Connect Flow described by our
 419 * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
 420 * lanes, EDID, etc) is done as needed in the typical places.
 421 *
 422 * Unlike the other ports, type-C ports are not available to use as soon as we
 423 * get a hotplug. The type-C PHYs can be shared between multiple controllers:
 424 * display, USB, etc. As a result, handshaking through FIA is required around
 425 * connect and disconnect to cleanly transfer ownership with the controller and
 426 * set the type-C power state.
 427 */
 428static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
 429                               int required_lanes)
 430{
 431        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 432        int max_lanes;
 433
 434        if (!tc_phy_status_complete(dig_port)) {
 435                drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
 436                            dig_port->tc_port_name);
 437                goto out_set_tbt_alt_mode;
 438        }
 439
 440        if (!tc_phy_take_ownership(dig_port, true) &&
 441            !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
 442                goto out_set_tbt_alt_mode;
 443
 444        max_lanes = intel_tc_port_fia_max_lane_count(dig_port);
 445        if (dig_port->tc_legacy_port) {
 446                drm_WARN_ON(&i915->drm, max_lanes != 4);
 447                dig_port->tc_mode = TC_PORT_LEGACY;
 448
 449                return;
 450        }
 451
 452        /*
 453         * Now we have to re-check the live state, in case the port recently
 454         * became disconnected. Not necessary for legacy mode.
 455         */
 456        if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
 457                drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
 458                            dig_port->tc_port_name);
 459                goto out_release_phy;
 460        }
 461
 462        if (max_lanes < required_lanes) {
 463                drm_dbg_kms(&i915->drm,
 464                            "Port %s: PHY max lanes %d < required lanes %d\n",
 465                            dig_port->tc_port_name,
 466                            max_lanes, required_lanes);
 467                goto out_release_phy;
 468        }
 469
 470        dig_port->tc_mode = TC_PORT_DP_ALT;
 471
 472        return;
 473
 474out_release_phy:
 475        tc_phy_take_ownership(dig_port, false);
 476out_set_tbt_alt_mode:
 477        dig_port->tc_mode = TC_PORT_TBT_ALT;
 478}
 479
 480/*
 481 * See the comment at the connect function. This implements the Disconnect
 482 * Flow.
 483 */
 484static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
 485{
 486        switch (dig_port->tc_mode) {
 487        case TC_PORT_LEGACY:
 488                /* Nothing to do, we never disconnect from legacy mode */
 489                break;
 490        case TC_PORT_DP_ALT:
 491                tc_phy_take_ownership(dig_port, false);
 492                dig_port->tc_mode = TC_PORT_TBT_ALT;
 493                break;
 494        case TC_PORT_TBT_ALT:
 495                /* Nothing to do, we stay in TBT-alt mode */
 496                break;
 497        default:
 498                MISSING_CASE(dig_port->tc_mode);
 499        }
 500}
 501
 502static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
 503{
 504        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 505
 506        if (!tc_phy_status_complete(dig_port)) {
 507                drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n",
 508                            dig_port->tc_port_name);
 509                return dig_port->tc_mode == TC_PORT_TBT_ALT;
 510        }
 511
 512        if (!tc_phy_is_owned(dig_port)) {
 513                drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
 514                            dig_port->tc_port_name);
 515
 516                return false;
 517        }
 518
 519        return dig_port->tc_mode == TC_PORT_DP_ALT ||
 520               dig_port->tc_mode == TC_PORT_LEGACY;
 521}
 522
 523static enum tc_port_mode
 524intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
 525{
 526        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 527        u32 live_status_mask = tc_port_live_status_mask(dig_port);
 528        enum tc_port_mode mode;
 529
 530        if (!tc_phy_is_owned(dig_port) ||
 531            drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port)))
 532                return TC_PORT_TBT_ALT;
 533
 534        mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
 535        if (live_status_mask) {
 536                enum tc_port_mode live_mode = fls(live_status_mask) - 1;
 537
 538                if (!drm_WARN_ON(&i915->drm, live_mode == TC_PORT_TBT_ALT))
 539                        mode = live_mode;
 540        }
 541
 542        return mode;
 543}
 544
 545static enum tc_port_mode
 546intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
 547{
 548        u32 live_status_mask = tc_port_live_status_mask(dig_port);
 549
 550        if (live_status_mask)
 551                return fls(live_status_mask) - 1;
 552
 553        return tc_phy_status_complete(dig_port) &&
 554               dig_port->tc_legacy_port ? TC_PORT_LEGACY :
 555                                          TC_PORT_TBT_ALT;
 556}
 557
 558static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
 559                                     int required_lanes)
 560{
 561        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 562        enum tc_port_mode old_tc_mode = dig_port->tc_mode;
 563
 564        intel_display_power_flush_work(i915);
 565        if (!intel_tc_cold_requires_aux_pw(dig_port)) {
 566                enum intel_display_power_domain aux_domain;
 567                bool aux_powered;
 568
 569                aux_domain = intel_aux_power_domain(dig_port);
 570                aux_powered = intel_display_power_is_enabled(i915, aux_domain);
 571                drm_WARN_ON(&i915->drm, aux_powered);
 572        }
 573
 574        icl_tc_phy_disconnect(dig_port);
 575        icl_tc_phy_connect(dig_port, required_lanes);
 576
 577        drm_dbg_kms(&i915->drm, "Port %s: TC port mode reset (%s -> %s)\n",
 578                    dig_port->tc_port_name,
 579                    tc_port_mode_name(old_tc_mode),
 580                    tc_port_mode_name(dig_port->tc_mode));
 581}
 582
 583static void
 584intel_tc_port_link_init_refcount(struct intel_digital_port *dig_port,
 585                                 int refcount)
 586{
 587        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 588
 589        drm_WARN_ON(&i915->drm, dig_port->tc_link_refcount);
 590        dig_port->tc_link_refcount = refcount;
 591}
 592
 593void intel_tc_port_sanitize(struct intel_digital_port *dig_port)
 594{
 595        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 596        struct intel_encoder *encoder = &dig_port->base;
 597        intel_wakeref_t tc_cold_wref;
 598        int active_links = 0;
 599
 600        mutex_lock(&dig_port->tc_lock);
 601        tc_cold_wref = tc_cold_block(dig_port);
 602
 603        dig_port->tc_mode = intel_tc_port_get_current_mode(dig_port);
 604        if (dig_port->dp.is_mst)
 605                active_links = intel_dp_mst_encoder_active_links(dig_port);
 606        else if (encoder->base.crtc)
 607                active_links = to_intel_crtc(encoder->base.crtc)->active;
 608
 609        if (active_links) {
 610                if (!icl_tc_phy_is_connected(dig_port))
 611                        drm_dbg_kms(&i915->drm,
 612                                    "Port %s: PHY disconnected with %d active link(s)\n",
 613                                    dig_port->tc_port_name, active_links);
 614                intel_tc_port_link_init_refcount(dig_port, active_links);
 615
 616                goto out;
 617        }
 618
 619        if (dig_port->tc_legacy_port)
 620                icl_tc_phy_connect(dig_port, 1);
 621
 622out:
 623        drm_dbg_kms(&i915->drm, "Port %s: sanitize mode (%s)\n",
 624                    dig_port->tc_port_name,
 625                    tc_port_mode_name(dig_port->tc_mode));
 626
 627        tc_cold_unblock(dig_port, tc_cold_wref);
 628        mutex_unlock(&dig_port->tc_lock);
 629}
 630
 631static bool intel_tc_port_needs_reset(struct intel_digital_port *dig_port)
 632{
 633        return intel_tc_port_get_target_mode(dig_port) != dig_port->tc_mode;
 634}
 635
 636/*
 637 * The type-C ports are different because even when they are connected, they may
 638 * not be available/usable by the graphics driver: see the comment on
 639 * icl_tc_phy_connect(). So in our driver instead of adding the additional
 640 * concept of "usable" and make everything check for "connected and usable" we
 641 * define a port as "connected" when it is not only connected, but also when it
 642 * is usable by the rest of the driver. That maintains the old assumption that
 643 * connected ports are usable, and avoids exposing to the users objects they
 644 * can't really use.
 645 */
 646bool intel_tc_port_connected(struct intel_encoder *encoder)
 647{
 648        struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 649        bool is_connected;
 650        intel_wakeref_t tc_cold_wref;
 651
 652        intel_tc_port_lock(dig_port);
 653        tc_cold_wref = tc_cold_block(dig_port);
 654
 655        is_connected = tc_port_live_status_mask(dig_port) &
 656                       BIT(dig_port->tc_mode);
 657
 658        tc_cold_unblock(dig_port, tc_cold_wref);
 659        intel_tc_port_unlock(dig_port);
 660
 661        return is_connected;
 662}
 663
 664static void __intel_tc_port_lock(struct intel_digital_port *dig_port,
 665                                 int required_lanes)
 666{
 667        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 668        intel_wakeref_t wakeref;
 669
 670        wakeref = intel_display_power_get(i915, POWER_DOMAIN_DISPLAY_CORE);
 671
 672        mutex_lock(&dig_port->tc_lock);
 673
 674        if (!dig_port->tc_link_refcount) {
 675                intel_wakeref_t tc_cold_wref;
 676
 677                tc_cold_wref = tc_cold_block(dig_port);
 678
 679                if (intel_tc_port_needs_reset(dig_port))
 680                        intel_tc_port_reset_mode(dig_port, required_lanes);
 681
 682                tc_cold_unblock(dig_port, tc_cold_wref);
 683        }
 684
 685        drm_WARN_ON(&i915->drm, dig_port->tc_lock_wakeref);
 686        dig_port->tc_lock_wakeref = wakeref;
 687}
 688
 689void intel_tc_port_lock(struct intel_digital_port *dig_port)
 690{
 691        __intel_tc_port_lock(dig_port, 1);
 692}
 693
 694void intel_tc_port_unlock(struct intel_digital_port *dig_port)
 695{
 696        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 697        intel_wakeref_t wakeref = fetch_and_zero(&dig_port->tc_lock_wakeref);
 698
 699        mutex_unlock(&dig_port->tc_lock);
 700
 701        intel_display_power_put_async(i915, POWER_DOMAIN_DISPLAY_CORE,
 702                                      wakeref);
 703}
 704
 705bool intel_tc_port_ref_held(struct intel_digital_port *dig_port)
 706{
 707        return mutex_is_locked(&dig_port->tc_lock) ||
 708               dig_port->tc_link_refcount;
 709}
 710
 711void intel_tc_port_get_link(struct intel_digital_port *dig_port,
 712                            int required_lanes)
 713{
 714        __intel_tc_port_lock(dig_port, required_lanes);
 715        dig_port->tc_link_refcount++;
 716        intel_tc_port_unlock(dig_port);
 717}
 718
 719void intel_tc_port_put_link(struct intel_digital_port *dig_port)
 720{
 721        mutex_lock(&dig_port->tc_lock);
 722        dig_port->tc_link_refcount--;
 723        mutex_unlock(&dig_port->tc_lock);
 724}
 725
 726static bool
 727tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
 728{
 729        intel_wakeref_t wakeref;
 730        u32 val;
 731
 732        if (!INTEL_INFO(i915)->display.has_modular_fia)
 733                return false;
 734
 735        mutex_lock(&dig_port->tc_lock);
 736        wakeref = tc_cold_block(dig_port);
 737        val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1));
 738        tc_cold_unblock(dig_port, wakeref);
 739        mutex_unlock(&dig_port->tc_lock);
 740
 741        drm_WARN_ON(&i915->drm, val == 0xffffffff);
 742
 743        return val & MODULAR_FIA_MASK;
 744}
 745
 746static void
 747tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port)
 748{
 749        enum port port = dig_port->base.port;
 750        enum tc_port tc_port = intel_port_to_tc(i915, port);
 751
 752        /*
 753         * Each Modular FIA instance houses 2 TC ports. In SOC that has more
 754         * than two TC ports, there are multiple instances of Modular FIA.
 755         */
 756        if (tc_has_modular_fia(i915, dig_port)) {
 757                dig_port->tc_phy_fia = tc_port / 2;
 758                dig_port->tc_phy_fia_idx = tc_port % 2;
 759        } else {
 760                dig_port->tc_phy_fia = FIA1;
 761                dig_port->tc_phy_fia_idx = tc_port;
 762        }
 763}
 764
 765void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
 766{
 767        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 768        enum port port = dig_port->base.port;
 769        enum tc_port tc_port = intel_port_to_tc(i915, port);
 770
 771        if (drm_WARN_ON(&i915->drm, tc_port == TC_PORT_NONE))
 772                return;
 773
 774        snprintf(dig_port->tc_port_name, sizeof(dig_port->tc_port_name),
 775                 "%c/TC#%d", port_name(port), tc_port + 1);
 776
 777        mutex_init(&dig_port->tc_lock);
 778        dig_port->tc_legacy_port = is_legacy;
 779        dig_port->tc_link_refcount = 0;
 780        tc_port_load_fia_params(i915, dig_port);
 781}
 782
 783bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
 784{
 785        struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 786
 787        return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) ||
 788                IS_ALDERLAKE_P(i915);
 789}
 790