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27#include <linux/slab.h>
28
29#include "dm_services.h"
30#include "dc.h"
31
32#include "dcn20_init.h"
33
34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "dcn10/dcn10_hubp.h"
39#include "dcn10/dcn10_ipp.h"
40#include "dcn20_hubbub.h"
41#include "dcn20_mpc.h"
42#include "dcn20_hubp.h"
43#include "irq/dcn20/irq_service_dcn20.h"
44#include "dcn20_dpp.h"
45#include "dcn20_optc.h"
46#include "dcn20_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
48#include "dcn10/dcn10_resource.h"
49#include "dcn20_opp.h"
50
51#include "dcn20_dsc.h"
52
53#include "dcn20_link_encoder.h"
54#include "dcn20_stream_encoder.h"
55#include "dce/dce_clock_source.h"
56#include "dce/dce_audio.h"
57#include "dce/dce_hwseq.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn20_dccg.h"
62#include "dcn20_vmid.h"
63#include "dc_link_ddc.h"
64#include "dce/dce_panel_cntl.h"
65
66#include "navi10_ip_offset.h"
67
68#include "dcn/dcn_2_0_0_offset.h"
69#include "dcn/dcn_2_0_0_sh_mask.h"
70#include "dpcs/dpcs_2_0_0_offset.h"
71#include "dpcs/dpcs_2_0_0_sh_mask.h"
72
73#include "nbio/nbio_2_3_offset.h"
74
75#include "dcn20/dcn20_dwb.h"
76#include "dcn20/dcn20_mmhubbub.h"
77
78#include "mmhub/mmhub_2_0_0_offset.h"
79#include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81#include "reg_helper.h"
82#include "dce/dce_abm.h"
83#include "dce/dce_dmcu.h"
84#include "dce/dce_aux.h"
85#include "dce/dce_i2c.h"
86#include "vm_helper.h"
87
88#include "amdgpu_socbb.h"
89
90#define DC_LOGGER_INIT(logger)
91
92struct _vcs_dpi_ip_params_st dcn2_0_ip = {
93 .odm_capable = 1,
94 .gpuvm_enable = 0,
95 .hostvm_enable = 0,
96 .gpuvm_max_page_table_levels = 4,
97 .hostvm_max_page_table_levels = 4,
98 .hostvm_cached_page_table_levels = 0,
99 .pte_group_size_bytes = 2048,
100 .num_dsc = 6,
101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 84,
104 .pde_proc_buffer_size_64k_reqs = 48,
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
108 .pte_chunk_size_kbytes = 2,
109 .meta_chunk_size_kbytes = 2,
110 .writeback_chunk_size_kbytes = 2,
111 .line_buffer_size_bits = 789504,
112 .is_line_buffer_bpp_fixed = 0,
113 .line_buffer_fixed_bpp = 0,
114 .dcc_supported = true,
115 .max_line_buffer_lines = 12,
116 .writeback_luma_buffer_size_kbytes = 12,
117 .writeback_chroma_buffer_size_kbytes = 8,
118 .writeback_chroma_line_buffer_width_pixels = 4,
119 .writeback_max_hscl_ratio = 1,
120 .writeback_max_vscl_ratio = 1,
121 .writeback_min_hscl_ratio = 1,
122 .writeback_min_vscl_ratio = 1,
123 .writeback_max_hscl_taps = 12,
124 .writeback_max_vscl_taps = 12,
125 .writeback_line_buffer_luma_buffer_size = 0,
126 .writeback_line_buffer_chroma_buffer_size = 14643,
127 .cursor_buffer_size = 8,
128 .cursor_chunk_size = 2,
129 .max_num_otg = 6,
130 .max_num_dpp = 6,
131 .max_num_wb = 1,
132 .max_dchub_pscl_bw_pix_per_clk = 4,
133 .max_pscl_lb_bw_pix_per_clk = 2,
134 .max_lb_vscl_bw_pix_per_clk = 4,
135 .max_vscl_hscl_bw_pix_per_clk = 4,
136 .max_hscl_ratio = 8,
137 .max_vscl_ratio = 8,
138 .hscl_mults = 4,
139 .vscl_mults = 4,
140 .max_hscl_taps = 8,
141 .max_vscl_taps = 8,
142 .dispclk_ramp_margin_percent = 1,
143 .underscan_factor = 1.10,
144 .min_vblank_lines = 32,
145 .dppclk_delay_subtotal = 77,
146 .dppclk_delay_scl_lb_only = 16,
147 .dppclk_delay_scl = 50,
148 .dppclk_delay_cnvc_formatter = 8,
149 .dppclk_delay_cnvc_cursor = 6,
150 .dispclk_delay_subtotal = 87,
151 .dcfclk_cstate_latency = 10,
152 .max_inter_dcn_tile_repeaters = 8,
153 .xfc_supported = true,
154 .xfc_fill_bw_overhead_percent = 10.0,
155 .xfc_fill_constant_bytes = 0,
156 .number_of_cursors = 1,
157};
158
159static struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
160 .odm_capable = 1,
161 .gpuvm_enable = 0,
162 .hostvm_enable = 0,
163 .gpuvm_max_page_table_levels = 4,
164 .hostvm_max_page_table_levels = 4,
165 .hostvm_cached_page_table_levels = 0,
166 .num_dsc = 5,
167 .rob_buffer_size_kbytes = 168,
168 .det_buffer_size_kbytes = 164,
169 .dpte_buffer_size_in_pte_reqs_luma = 84,
170 .dpte_buffer_size_in_pte_reqs_chroma = 42,
171 .dpp_output_buffer_pixels = 2560,
172 .opp_output_buffer_lines = 1,
173 .pixel_chunk_size_kbytes = 8,
174 .pte_enable = 1,
175 .max_page_table_levels = 4,
176 .pte_chunk_size_kbytes = 2,
177 .meta_chunk_size_kbytes = 2,
178 .writeback_chunk_size_kbytes = 2,
179 .line_buffer_size_bits = 789504,
180 .is_line_buffer_bpp_fixed = 0,
181 .line_buffer_fixed_bpp = 0,
182 .dcc_supported = true,
183 .max_line_buffer_lines = 12,
184 .writeback_luma_buffer_size_kbytes = 12,
185 .writeback_chroma_buffer_size_kbytes = 8,
186 .writeback_chroma_line_buffer_width_pixels = 4,
187 .writeback_max_hscl_ratio = 1,
188 .writeback_max_vscl_ratio = 1,
189 .writeback_min_hscl_ratio = 1,
190 .writeback_min_vscl_ratio = 1,
191 .writeback_max_hscl_taps = 12,
192 .writeback_max_vscl_taps = 12,
193 .writeback_line_buffer_luma_buffer_size = 0,
194 .writeback_line_buffer_chroma_buffer_size = 14643,
195 .cursor_buffer_size = 8,
196 .cursor_chunk_size = 2,
197 .max_num_otg = 5,
198 .max_num_dpp = 5,
199 .max_num_wb = 1,
200 .max_dchub_pscl_bw_pix_per_clk = 4,
201 .max_pscl_lb_bw_pix_per_clk = 2,
202 .max_lb_vscl_bw_pix_per_clk = 4,
203 .max_vscl_hscl_bw_pix_per_clk = 4,
204 .max_hscl_ratio = 8,
205 .max_vscl_ratio = 8,
206 .hscl_mults = 4,
207 .vscl_mults = 4,
208 .max_hscl_taps = 8,
209 .max_vscl_taps = 8,
210 .dispclk_ramp_margin_percent = 1,
211 .underscan_factor = 1.10,
212 .min_vblank_lines = 32,
213 .dppclk_delay_subtotal = 77,
214 .dppclk_delay_scl_lb_only = 16,
215 .dppclk_delay_scl = 50,
216 .dppclk_delay_cnvc_formatter = 8,
217 .dppclk_delay_cnvc_cursor = 6,
218 .dispclk_delay_subtotal = 87,
219 .dcfclk_cstate_latency = 10,
220 .max_inter_dcn_tile_repeaters = 8,
221 .xfc_supported = true,
222 .xfc_fill_bw_overhead_percent = 10.0,
223 .xfc_fill_constant_bytes = 0,
224 .ptoi_supported = 0,
225 .number_of_cursors = 1,
226};
227
228static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
229
230 .clock_limits = {
231 {
232 .state = 0,
233 .dcfclk_mhz = 560.0,
234 .fabricclk_mhz = 560.0,
235 .dispclk_mhz = 513.0,
236 .dppclk_mhz = 513.0,
237 .phyclk_mhz = 540.0,
238 .socclk_mhz = 560.0,
239 .dscclk_mhz = 171.0,
240 .dram_speed_mts = 8960.0,
241 },
242 {
243 .state = 1,
244 .dcfclk_mhz = 694.0,
245 .fabricclk_mhz = 694.0,
246 .dispclk_mhz = 642.0,
247 .dppclk_mhz = 642.0,
248 .phyclk_mhz = 600.0,
249 .socclk_mhz = 694.0,
250 .dscclk_mhz = 214.0,
251 .dram_speed_mts = 11104.0,
252 },
253 {
254 .state = 2,
255 .dcfclk_mhz = 875.0,
256 .fabricclk_mhz = 875.0,
257 .dispclk_mhz = 734.0,
258 .dppclk_mhz = 734.0,
259 .phyclk_mhz = 810.0,
260 .socclk_mhz = 875.0,
261 .dscclk_mhz = 245.0,
262 .dram_speed_mts = 14000.0,
263 },
264 {
265 .state = 3,
266 .dcfclk_mhz = 1000.0,
267 .fabricclk_mhz = 1000.0,
268 .dispclk_mhz = 1100.0,
269 .dppclk_mhz = 1100.0,
270 .phyclk_mhz = 810.0,
271 .socclk_mhz = 1000.0,
272 .dscclk_mhz = 367.0,
273 .dram_speed_mts = 16000.0,
274 },
275 {
276 .state = 4,
277 .dcfclk_mhz = 1200.0,
278 .fabricclk_mhz = 1200.0,
279 .dispclk_mhz = 1284.0,
280 .dppclk_mhz = 1284.0,
281 .phyclk_mhz = 810.0,
282 .socclk_mhz = 1200.0,
283 .dscclk_mhz = 428.0,
284 .dram_speed_mts = 16000.0,
285 },
286
287 {
288 .state = 5,
289 .dcfclk_mhz = 1200.0,
290 .fabricclk_mhz = 1200.0,
291 .dispclk_mhz = 1284.0,
292 .dppclk_mhz = 1284.0,
293 .phyclk_mhz = 810.0,
294 .socclk_mhz = 1200.0,
295 .dscclk_mhz = 428.0,
296 .dram_speed_mts = 16000.0,
297 },
298 },
299 .num_states = 5,
300 .sr_exit_time_us = 8.6,
301 .sr_enter_plus_exit_time_us = 10.9,
302 .urgent_latency_us = 4.0,
303 .urgent_latency_pixel_data_only_us = 4.0,
304 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
305 .urgent_latency_vm_data_only_us = 4.0,
306 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
307 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
308 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
309 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
311 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
312 .max_avg_sdp_bw_use_normal_percent = 40.0,
313 .max_avg_dram_bw_use_normal_percent = 40.0,
314 .writeback_latency_us = 12.0,
315 .ideal_dram_bw_after_urgent_percent = 40.0,
316 .max_request_size_bytes = 256,
317 .dram_channel_width_bytes = 2,
318 .fabric_datapath_to_dcn_data_return_bytes = 64,
319 .dcn_downspread_percent = 0.5,
320 .downspread_percent = 0.38,
321 .dram_page_open_time_ns = 50.0,
322 .dram_rw_turnaround_time_ns = 17.5,
323 .dram_return_buffer_per_channel_bytes = 8192,
324 .round_trip_ping_latency_dcfclk_cycles = 131,
325 .urgent_out_of_order_return_per_channel_bytes = 256,
326 .channel_interleave_bytes = 256,
327 .num_banks = 8,
328 .num_chans = 16,
329 .vmm_page_size_bytes = 4096,
330 .dram_clock_change_latency_us = 404.0,
331 .dummy_pstate_latency_us = 5.0,
332 .writeback_dram_clock_change_latency_us = 23.0,
333 .return_bus_width_bytes = 64,
334 .dispclk_dppclk_vco_speed_mhz = 3850,
335 .xfc_bus_transport_time_us = 20,
336 .xfc_xbuf_latency_tolerance_us = 4,
337 .use_urgent_burst_bw = 0
338};
339
340static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
341 .clock_limits = {
342 {
343 .state = 0,
344 .dcfclk_mhz = 560.0,
345 .fabricclk_mhz = 560.0,
346 .dispclk_mhz = 513.0,
347 .dppclk_mhz = 513.0,
348 .phyclk_mhz = 540.0,
349 .socclk_mhz = 560.0,
350 .dscclk_mhz = 171.0,
351 .dram_speed_mts = 8960.0,
352 },
353 {
354 .state = 1,
355 .dcfclk_mhz = 694.0,
356 .fabricclk_mhz = 694.0,
357 .dispclk_mhz = 642.0,
358 .dppclk_mhz = 642.0,
359 .phyclk_mhz = 600.0,
360 .socclk_mhz = 694.0,
361 .dscclk_mhz = 214.0,
362 .dram_speed_mts = 11104.0,
363 },
364 {
365 .state = 2,
366 .dcfclk_mhz = 875.0,
367 .fabricclk_mhz = 875.0,
368 .dispclk_mhz = 734.0,
369 .dppclk_mhz = 734.0,
370 .phyclk_mhz = 810.0,
371 .socclk_mhz = 875.0,
372 .dscclk_mhz = 245.0,
373 .dram_speed_mts = 14000.0,
374 },
375 {
376 .state = 3,
377 .dcfclk_mhz = 1000.0,
378 .fabricclk_mhz = 1000.0,
379 .dispclk_mhz = 1100.0,
380 .dppclk_mhz = 1100.0,
381 .phyclk_mhz = 810.0,
382 .socclk_mhz = 1000.0,
383 .dscclk_mhz = 367.0,
384 .dram_speed_mts = 16000.0,
385 },
386 {
387 .state = 4,
388 .dcfclk_mhz = 1200.0,
389 .fabricclk_mhz = 1200.0,
390 .dispclk_mhz = 1284.0,
391 .dppclk_mhz = 1284.0,
392 .phyclk_mhz = 810.0,
393 .socclk_mhz = 1200.0,
394 .dscclk_mhz = 428.0,
395 .dram_speed_mts = 16000.0,
396 },
397
398 {
399 .state = 5,
400 .dcfclk_mhz = 1200.0,
401 .fabricclk_mhz = 1200.0,
402 .dispclk_mhz = 1284.0,
403 .dppclk_mhz = 1284.0,
404 .phyclk_mhz = 810.0,
405 .socclk_mhz = 1200.0,
406 .dscclk_mhz = 428.0,
407 .dram_speed_mts = 16000.0,
408 },
409 },
410 .num_states = 5,
411 .sr_exit_time_us = 11.6,
412 .sr_enter_plus_exit_time_us = 13.9,
413 .urgent_latency_us = 4.0,
414 .urgent_latency_pixel_data_only_us = 4.0,
415 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
416 .urgent_latency_vm_data_only_us = 4.0,
417 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
418 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
419 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
420 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
421 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
422 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
423 .max_avg_sdp_bw_use_normal_percent = 40.0,
424 .max_avg_dram_bw_use_normal_percent = 40.0,
425 .writeback_latency_us = 12.0,
426 .ideal_dram_bw_after_urgent_percent = 40.0,
427 .max_request_size_bytes = 256,
428 .dram_channel_width_bytes = 2,
429 .fabric_datapath_to_dcn_data_return_bytes = 64,
430 .dcn_downspread_percent = 0.5,
431 .downspread_percent = 0.38,
432 .dram_page_open_time_ns = 50.0,
433 .dram_rw_turnaround_time_ns = 17.5,
434 .dram_return_buffer_per_channel_bytes = 8192,
435 .round_trip_ping_latency_dcfclk_cycles = 131,
436 .urgent_out_of_order_return_per_channel_bytes = 256,
437 .channel_interleave_bytes = 256,
438 .num_banks = 8,
439 .num_chans = 8,
440 .vmm_page_size_bytes = 4096,
441 .dram_clock_change_latency_us = 404.0,
442 .dummy_pstate_latency_us = 5.0,
443 .writeback_dram_clock_change_latency_us = 23.0,
444 .return_bus_width_bytes = 64,
445 .dispclk_dppclk_vco_speed_mhz = 3850,
446 .xfc_bus_transport_time_us = 20,
447 .xfc_xbuf_latency_tolerance_us = 4,
448 .use_urgent_burst_bw = 0
449};
450
451static struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
452
453#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
454 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
455 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
456 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
457 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
458 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
459 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
460 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
461 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
462 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
463 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
464 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
465 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
466 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
467 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
468#endif
469
470
471enum dcn20_clk_src_array_id {
472 DCN20_CLK_SRC_PLL0,
473 DCN20_CLK_SRC_PLL1,
474 DCN20_CLK_SRC_PLL2,
475 DCN20_CLK_SRC_PLL3,
476 DCN20_CLK_SRC_PLL4,
477 DCN20_CLK_SRC_PLL5,
478 DCN20_CLK_SRC_TOTAL
479};
480
481
482
483
484
485
486#undef BASE_INNER
487#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
488
489#define BASE(seg) BASE_INNER(seg)
490
491#define SR(reg_name)\
492 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
493 mm ## reg_name
494
495#define SRI(reg_name, block, id)\
496 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
497 mm ## block ## id ## _ ## reg_name
498
499#define SRIR(var_name, reg_name, block, id)\
500 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 mm ## block ## id ## _ ## reg_name
502
503#define SRII(reg_name, block, id)\
504 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 mm ## block ## id ## _ ## reg_name
506
507#define DCCG_SRII(reg_name, block, id)\
508 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 mm ## block ## id ## _ ## reg_name
510
511#define VUPDATE_SRII(reg_name, block, id)\
512 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
513 mm ## reg_name ## _ ## block ## id
514
515
516#define NBIO_BASE_INNER(seg) \
517 NBIO_BASE__INST0_SEG ## seg
518
519#define NBIO_BASE(seg) \
520 NBIO_BASE_INNER(seg)
521
522#define NBIO_SR(reg_name)\
523 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
524 mm ## reg_name
525
526
527#define MMHUB_BASE_INNER(seg) \
528 MMHUB_BASE__INST0_SEG ## seg
529
530#define MMHUB_BASE(seg) \
531 MMHUB_BASE_INNER(seg)
532
533#define MMHUB_SR(reg_name)\
534 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
535 mmMM ## reg_name
536
537static const struct bios_registers bios_regs = {
538 NBIO_SR(BIOS_SCRATCH_3),
539 NBIO_SR(BIOS_SCRATCH_6)
540};
541
542#define clk_src_regs(index, pllid)\
543[index] = {\
544 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
545}
546
547static const struct dce110_clk_src_regs clk_src_regs[] = {
548 clk_src_regs(0, A),
549 clk_src_regs(1, B),
550 clk_src_regs(2, C),
551 clk_src_regs(3, D),
552 clk_src_regs(4, E),
553 clk_src_regs(5, F)
554};
555
556static const struct dce110_clk_src_shift cs_shift = {
557 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
558};
559
560static const struct dce110_clk_src_mask cs_mask = {
561 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
562};
563
564static const struct dce_dmcu_registers dmcu_regs = {
565 DMCU_DCN10_REG_LIST()
566};
567
568static const struct dce_dmcu_shift dmcu_shift = {
569 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
570};
571
572static const struct dce_dmcu_mask dmcu_mask = {
573 DMCU_MASK_SH_LIST_DCN10(_MASK)
574};
575
576static const struct dce_abm_registers abm_regs = {
577 ABM_DCN20_REG_LIST()
578};
579
580static const struct dce_abm_shift abm_shift = {
581 ABM_MASK_SH_LIST_DCN20(__SHIFT)
582};
583
584static const struct dce_abm_mask abm_mask = {
585 ABM_MASK_SH_LIST_DCN20(_MASK)
586};
587
588#define audio_regs(id)\
589[id] = {\
590 AUD_COMMON_REG_LIST(id)\
591}
592
593static const struct dce_audio_registers audio_regs[] = {
594 audio_regs(0),
595 audio_regs(1),
596 audio_regs(2),
597 audio_regs(3),
598 audio_regs(4),
599 audio_regs(5),
600 audio_regs(6),
601};
602
603#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
604 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
605 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
606 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
607
608static const struct dce_audio_shift audio_shift = {
609 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
610};
611
612static const struct dce_audio_mask audio_mask = {
613 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
614};
615
616#define stream_enc_regs(id)\
617[id] = {\
618 SE_DCN2_REG_LIST(id)\
619}
620
621static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
622 stream_enc_regs(0),
623 stream_enc_regs(1),
624 stream_enc_regs(2),
625 stream_enc_regs(3),
626 stream_enc_regs(4),
627 stream_enc_regs(5),
628};
629
630static const struct dcn10_stream_encoder_shift se_shift = {
631 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
632};
633
634static const struct dcn10_stream_encoder_mask se_mask = {
635 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
636};
637
638
639#define aux_regs(id)\
640[id] = {\
641 DCN2_AUX_REG_LIST(id)\
642}
643
644static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
645 aux_regs(0),
646 aux_regs(1),
647 aux_regs(2),
648 aux_regs(3),
649 aux_regs(4),
650 aux_regs(5)
651};
652
653#define hpd_regs(id)\
654[id] = {\
655 HPD_REG_LIST(id)\
656}
657
658static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
659 hpd_regs(0),
660 hpd_regs(1),
661 hpd_regs(2),
662 hpd_regs(3),
663 hpd_regs(4),
664 hpd_regs(5)
665};
666
667#define link_regs(id, phyid)\
668[id] = {\
669 LE_DCN10_REG_LIST(id), \
670 UNIPHY_DCN2_REG_LIST(phyid), \
671 DPCS_DCN2_REG_LIST(id), \
672 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
673}
674
675static const struct dcn10_link_enc_registers link_enc_regs[] = {
676 link_regs(0, A),
677 link_regs(1, B),
678 link_regs(2, C),
679 link_regs(3, D),
680 link_regs(4, E),
681 link_regs(5, F)
682};
683
684static const struct dcn10_link_enc_shift le_shift = {
685 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
686 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
687};
688
689static const struct dcn10_link_enc_mask le_mask = {
690 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
691 DPCS_DCN2_MASK_SH_LIST(_MASK)
692};
693
694static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
695 { DCN_PANEL_CNTL_REG_LIST() }
696};
697
698static const struct dce_panel_cntl_shift panel_cntl_shift = {
699 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
700};
701
702static const struct dce_panel_cntl_mask panel_cntl_mask = {
703 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
704};
705
706#define ipp_regs(id)\
707[id] = {\
708 IPP_REG_LIST_DCN20(id),\
709}
710
711static const struct dcn10_ipp_registers ipp_regs[] = {
712 ipp_regs(0),
713 ipp_regs(1),
714 ipp_regs(2),
715 ipp_regs(3),
716 ipp_regs(4),
717 ipp_regs(5),
718};
719
720static const struct dcn10_ipp_shift ipp_shift = {
721 IPP_MASK_SH_LIST_DCN20(__SHIFT)
722};
723
724static const struct dcn10_ipp_mask ipp_mask = {
725 IPP_MASK_SH_LIST_DCN20(_MASK),
726};
727
728#define opp_regs(id)\
729[id] = {\
730 OPP_REG_LIST_DCN20(id),\
731}
732
733static const struct dcn20_opp_registers opp_regs[] = {
734 opp_regs(0),
735 opp_regs(1),
736 opp_regs(2),
737 opp_regs(3),
738 opp_regs(4),
739 opp_regs(5),
740};
741
742static const struct dcn20_opp_shift opp_shift = {
743 OPP_MASK_SH_LIST_DCN20(__SHIFT)
744};
745
746static const struct dcn20_opp_mask opp_mask = {
747 OPP_MASK_SH_LIST_DCN20(_MASK)
748};
749
750#define aux_engine_regs(id)\
751[id] = {\
752 AUX_COMMON_REG_LIST0(id), \
753 .AUXN_IMPCAL = 0, \
754 .AUXP_IMPCAL = 0, \
755 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
756}
757
758static const struct dce110_aux_registers aux_engine_regs[] = {
759 aux_engine_regs(0),
760 aux_engine_regs(1),
761 aux_engine_regs(2),
762 aux_engine_regs(3),
763 aux_engine_regs(4),
764 aux_engine_regs(5)
765};
766
767#define tf_regs(id)\
768[id] = {\
769 TF_REG_LIST_DCN20(id),\
770 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
771}
772
773static const struct dcn2_dpp_registers tf_regs[] = {
774 tf_regs(0),
775 tf_regs(1),
776 tf_regs(2),
777 tf_regs(3),
778 tf_regs(4),
779 tf_regs(5),
780};
781
782static const struct dcn2_dpp_shift tf_shift = {
783 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
784 TF_DEBUG_REG_LIST_SH_DCN20
785};
786
787static const struct dcn2_dpp_mask tf_mask = {
788 TF_REG_LIST_SH_MASK_DCN20(_MASK),
789 TF_DEBUG_REG_LIST_MASK_DCN20
790};
791
792#define dwbc_regs_dcn2(id)\
793[id] = {\
794 DWBC_COMMON_REG_LIST_DCN2_0(id),\
795 }
796
797static const struct dcn20_dwbc_registers dwbc20_regs[] = {
798 dwbc_regs_dcn2(0),
799};
800
801static const struct dcn20_dwbc_shift dwbc20_shift = {
802 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
803};
804
805static const struct dcn20_dwbc_mask dwbc20_mask = {
806 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
807};
808
809#define mcif_wb_regs_dcn2(id)\
810[id] = {\
811 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
812 }
813
814static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
815 mcif_wb_regs_dcn2(0),
816};
817
818static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
819 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
820};
821
822static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
823 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
824};
825
826static const struct dcn20_mpc_registers mpc_regs = {
827 MPC_REG_LIST_DCN2_0(0),
828 MPC_REG_LIST_DCN2_0(1),
829 MPC_REG_LIST_DCN2_0(2),
830 MPC_REG_LIST_DCN2_0(3),
831 MPC_REG_LIST_DCN2_0(4),
832 MPC_REG_LIST_DCN2_0(5),
833 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
834 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
835 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
836 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
837 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
838 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
839 MPC_DBG_REG_LIST_DCN2_0()
840};
841
842static const struct dcn20_mpc_shift mpc_shift = {
843 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
844 MPC_DEBUG_REG_LIST_SH_DCN20
845};
846
847static const struct dcn20_mpc_mask mpc_mask = {
848 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
849 MPC_DEBUG_REG_LIST_MASK_DCN20
850};
851
852#define tg_regs(id)\
853[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
854
855
856static const struct dcn_optc_registers tg_regs[] = {
857 tg_regs(0),
858 tg_regs(1),
859 tg_regs(2),
860 tg_regs(3),
861 tg_regs(4),
862 tg_regs(5)
863};
864
865static const struct dcn_optc_shift tg_shift = {
866 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
867};
868
869static const struct dcn_optc_mask tg_mask = {
870 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
871};
872
873#define hubp_regs(id)\
874[id] = {\
875 HUBP_REG_LIST_DCN20(id)\
876}
877
878static const struct dcn_hubp2_registers hubp_regs[] = {
879 hubp_regs(0),
880 hubp_regs(1),
881 hubp_regs(2),
882 hubp_regs(3),
883 hubp_regs(4),
884 hubp_regs(5)
885};
886
887static const struct dcn_hubp2_shift hubp_shift = {
888 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
889};
890
891static const struct dcn_hubp2_mask hubp_mask = {
892 HUBP_MASK_SH_LIST_DCN20(_MASK)
893};
894
895static const struct dcn_hubbub_registers hubbub_reg = {
896 HUBBUB_REG_LIST_DCN20(0)
897};
898
899static const struct dcn_hubbub_shift hubbub_shift = {
900 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
901};
902
903static const struct dcn_hubbub_mask hubbub_mask = {
904 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
905};
906
907#define vmid_regs(id)\
908[id] = {\
909 DCN20_VMID_REG_LIST(id)\
910}
911
912static const struct dcn_vmid_registers vmid_regs[] = {
913 vmid_regs(0),
914 vmid_regs(1),
915 vmid_regs(2),
916 vmid_regs(3),
917 vmid_regs(4),
918 vmid_regs(5),
919 vmid_regs(6),
920 vmid_regs(7),
921 vmid_regs(8),
922 vmid_regs(9),
923 vmid_regs(10),
924 vmid_regs(11),
925 vmid_regs(12),
926 vmid_regs(13),
927 vmid_regs(14),
928 vmid_regs(15)
929};
930
931static const struct dcn20_vmid_shift vmid_shifts = {
932 DCN20_VMID_MASK_SH_LIST(__SHIFT)
933};
934
935static const struct dcn20_vmid_mask vmid_masks = {
936 DCN20_VMID_MASK_SH_LIST(_MASK)
937};
938
939static const struct dce110_aux_registers_shift aux_shift = {
940 DCN_AUX_MASK_SH_LIST(__SHIFT)
941};
942
943static const struct dce110_aux_registers_mask aux_mask = {
944 DCN_AUX_MASK_SH_LIST(_MASK)
945};
946
947static int map_transmitter_id_to_phy_instance(
948 enum transmitter transmitter)
949{
950 switch (transmitter) {
951 case TRANSMITTER_UNIPHY_A:
952 return 0;
953 break;
954 case TRANSMITTER_UNIPHY_B:
955 return 1;
956 break;
957 case TRANSMITTER_UNIPHY_C:
958 return 2;
959 break;
960 case TRANSMITTER_UNIPHY_D:
961 return 3;
962 break;
963 case TRANSMITTER_UNIPHY_E:
964 return 4;
965 break;
966 case TRANSMITTER_UNIPHY_F:
967 return 5;
968 break;
969 default:
970 ASSERT(0);
971 return 0;
972 }
973}
974
975#define dsc_regsDCN20(id)\
976[id] = {\
977 DSC_REG_LIST_DCN20(id)\
978}
979
980static const struct dcn20_dsc_registers dsc_regs[] = {
981 dsc_regsDCN20(0),
982 dsc_regsDCN20(1),
983 dsc_regsDCN20(2),
984 dsc_regsDCN20(3),
985 dsc_regsDCN20(4),
986 dsc_regsDCN20(5)
987};
988
989static const struct dcn20_dsc_shift dsc_shift = {
990 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
991};
992
993static const struct dcn20_dsc_mask dsc_mask = {
994 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
995};
996
997static const struct dccg_registers dccg_regs = {
998 DCCG_REG_LIST_DCN2()
999};
1000
1001static const struct dccg_shift dccg_shift = {
1002 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
1003};
1004
1005static const struct dccg_mask dccg_mask = {
1006 DCCG_MASK_SH_LIST_DCN2(_MASK)
1007};
1008
1009static const struct resource_caps res_cap_nv10 = {
1010 .num_timing_generator = 6,
1011 .num_opp = 6,
1012 .num_video_plane = 6,
1013 .num_audio = 7,
1014 .num_stream_encoder = 6,
1015 .num_pll = 6,
1016 .num_dwb = 1,
1017 .num_ddc = 6,
1018 .num_vmid = 16,
1019 .num_dsc = 6,
1020};
1021
1022static const struct dc_plane_cap plane_cap = {
1023 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1024 .blends_with_above = true,
1025 .blends_with_below = true,
1026 .per_pixel_alpha = true,
1027
1028 .pixel_format_support = {
1029 .argb8888 = true,
1030 .nv12 = true,
1031 .fp16 = true,
1032 .p010 = true
1033 },
1034
1035 .max_upscale_factor = {
1036 .argb8888 = 16000,
1037 .nv12 = 16000,
1038 .fp16 = 1
1039 },
1040
1041 .max_downscale_factor = {
1042 .argb8888 = 250,
1043 .nv12 = 250,
1044 .fp16 = 1
1045 },
1046 16,
1047 16
1048};
1049static const struct resource_caps res_cap_nv14 = {
1050 .num_timing_generator = 5,
1051 .num_opp = 5,
1052 .num_video_plane = 5,
1053 .num_audio = 6,
1054 .num_stream_encoder = 5,
1055 .num_pll = 5,
1056 .num_dwb = 1,
1057 .num_ddc = 5,
1058 .num_vmid = 16,
1059 .num_dsc = 5,
1060};
1061
1062static const struct dc_debug_options debug_defaults_drv = {
1063 .disable_dmcu = false,
1064 .force_abm_enable = false,
1065 .timing_trace = false,
1066 .clock_trace = true,
1067 .disable_pplib_clock_request = true,
1068 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
1069 .force_single_disp_pipe_split = false,
1070 .disable_dcc = DCC_ENABLE,
1071 .vsr_support = true,
1072 .performance_trace = false,
1073 .max_downscale_src_width = 5120,
1074 .disable_pplib_wm_range = false,
1075 .scl_reset_length10 = true,
1076 .sanity_checks = false,
1077 .underflow_assert_delay_us = 0xFFFFFFFF,
1078};
1079
1080static const struct dc_debug_options debug_defaults_diags = {
1081 .disable_dmcu = false,
1082 .force_abm_enable = false,
1083 .timing_trace = true,
1084 .clock_trace = true,
1085 .disable_dpp_power_gate = true,
1086 .disable_hubp_power_gate = true,
1087 .disable_clock_gate = true,
1088 .disable_pplib_clock_request = true,
1089 .disable_pplib_wm_range = true,
1090 .disable_stutter = true,
1091 .scl_reset_length10 = true,
1092 .underflow_assert_delay_us = 0xFFFFFFFF,
1093 .enable_tri_buf = true,
1094};
1095
1096void dcn20_dpp_destroy(struct dpp **dpp)
1097{
1098 kfree(TO_DCN20_DPP(*dpp));
1099 *dpp = NULL;
1100}
1101
1102struct dpp *dcn20_dpp_create(
1103 struct dc_context *ctx,
1104 uint32_t inst)
1105{
1106 struct dcn20_dpp *dpp =
1107 kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
1108
1109 if (!dpp)
1110 return NULL;
1111
1112 if (dpp2_construct(dpp, ctx, inst,
1113 &tf_regs[inst], &tf_shift, &tf_mask))
1114 return &dpp->base;
1115
1116 BREAK_TO_DEBUGGER();
1117 kfree(dpp);
1118 return NULL;
1119}
1120
1121struct input_pixel_processor *dcn20_ipp_create(
1122 struct dc_context *ctx, uint32_t inst)
1123{
1124 struct dcn10_ipp *ipp =
1125 kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
1126
1127 if (!ipp) {
1128 BREAK_TO_DEBUGGER();
1129 return NULL;
1130 }
1131
1132 dcn20_ipp_construct(ipp, ctx, inst,
1133 &ipp_regs[inst], &ipp_shift, &ipp_mask);
1134 return &ipp->base;
1135}
1136
1137
1138struct output_pixel_processor *dcn20_opp_create(
1139 struct dc_context *ctx, uint32_t inst)
1140{
1141 struct dcn20_opp *opp =
1142 kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
1143
1144 if (!opp) {
1145 BREAK_TO_DEBUGGER();
1146 return NULL;
1147 }
1148
1149 dcn20_opp_construct(opp, ctx, inst,
1150 &opp_regs[inst], &opp_shift, &opp_mask);
1151 return &opp->base;
1152}
1153
1154struct dce_aux *dcn20_aux_engine_create(
1155 struct dc_context *ctx,
1156 uint32_t inst)
1157{
1158 struct aux_engine_dce110 *aux_engine =
1159 kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
1160
1161 if (!aux_engine)
1162 return NULL;
1163
1164 dce110_aux_engine_construct(aux_engine, ctx, inst,
1165 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1166 &aux_engine_regs[inst],
1167 &aux_mask,
1168 &aux_shift,
1169 ctx->dc->caps.extended_aux_timeout_support);
1170
1171 return &aux_engine->base;
1172}
1173#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1174
1175static const struct dce_i2c_registers i2c_hw_regs[] = {
1176 i2c_inst_regs(1),
1177 i2c_inst_regs(2),
1178 i2c_inst_regs(3),
1179 i2c_inst_regs(4),
1180 i2c_inst_regs(5),
1181 i2c_inst_regs(6),
1182};
1183
1184static const struct dce_i2c_shift i2c_shifts = {
1185 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1186};
1187
1188static const struct dce_i2c_mask i2c_masks = {
1189 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1190};
1191
1192struct dce_i2c_hw *dcn20_i2c_hw_create(
1193 struct dc_context *ctx,
1194 uint32_t inst)
1195{
1196 struct dce_i2c_hw *dce_i2c_hw =
1197 kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
1198
1199 if (!dce_i2c_hw)
1200 return NULL;
1201
1202 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1203 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1204
1205 return dce_i2c_hw;
1206}
1207struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1208{
1209 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1210 GFP_ATOMIC);
1211
1212 if (!mpc20)
1213 return NULL;
1214
1215 dcn20_mpc_construct(mpc20, ctx,
1216 &mpc_regs,
1217 &mpc_shift,
1218 &mpc_mask,
1219 6);
1220
1221 return &mpc20->base;
1222}
1223
1224struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1225{
1226 int i;
1227 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1228 GFP_ATOMIC);
1229
1230 if (!hubbub)
1231 return NULL;
1232
1233 hubbub2_construct(hubbub, ctx,
1234 &hubbub_reg,
1235 &hubbub_shift,
1236 &hubbub_mask);
1237
1238 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1239 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1240
1241 vmid->ctx = ctx;
1242
1243 vmid->regs = &vmid_regs[i];
1244 vmid->shifts = &vmid_shifts;
1245 vmid->masks = &vmid_masks;
1246 }
1247
1248 return &hubbub->base;
1249}
1250
1251struct timing_generator *dcn20_timing_generator_create(
1252 struct dc_context *ctx,
1253 uint32_t instance)
1254{
1255 struct optc *tgn10 =
1256 kzalloc(sizeof(struct optc), GFP_ATOMIC);
1257
1258 if (!tgn10)
1259 return NULL;
1260
1261 tgn10->base.inst = instance;
1262 tgn10->base.ctx = ctx;
1263
1264 tgn10->tg_regs = &tg_regs[instance];
1265 tgn10->tg_shift = &tg_shift;
1266 tgn10->tg_mask = &tg_mask;
1267
1268 dcn20_timing_generator_init(tgn10);
1269
1270 return &tgn10->base;
1271}
1272
1273static const struct encoder_feature_support link_enc_feature = {
1274 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1275 .max_hdmi_pixel_clock = 600000,
1276 .hdmi_ycbcr420_supported = true,
1277 .dp_ycbcr420_supported = true,
1278 .fec_supported = true,
1279 .flags.bits.IS_HBR2_CAPABLE = true,
1280 .flags.bits.IS_HBR3_CAPABLE = true,
1281 .flags.bits.IS_TPS3_CAPABLE = true,
1282 .flags.bits.IS_TPS4_CAPABLE = true
1283};
1284
1285struct link_encoder *dcn20_link_encoder_create(
1286 const struct encoder_init_data *enc_init_data)
1287{
1288 struct dcn20_link_encoder *enc20 =
1289 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1290 int link_regs_id;
1291
1292 if (!enc20)
1293 return NULL;
1294
1295 link_regs_id =
1296 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1297
1298 dcn20_link_encoder_construct(enc20,
1299 enc_init_data,
1300 &link_enc_feature,
1301 &link_enc_regs[link_regs_id],
1302 &link_enc_aux_regs[enc_init_data->channel - 1],
1303 &link_enc_hpd_regs[enc_init_data->hpd_source],
1304 &le_shift,
1305 &le_mask);
1306
1307 return &enc20->enc10.base;
1308}
1309
1310static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1311{
1312 struct dce_panel_cntl *panel_cntl =
1313 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1314
1315 if (!panel_cntl)
1316 return NULL;
1317
1318 dce_panel_cntl_construct(panel_cntl,
1319 init_data,
1320 &panel_cntl_regs[init_data->inst],
1321 &panel_cntl_shift,
1322 &panel_cntl_mask);
1323
1324 return &panel_cntl->base;
1325}
1326
1327static struct clock_source *dcn20_clock_source_create(
1328 struct dc_context *ctx,
1329 struct dc_bios *bios,
1330 enum clock_source_id id,
1331 const struct dce110_clk_src_regs *regs,
1332 bool dp_clk_src)
1333{
1334 struct dce110_clk_src *clk_src =
1335 kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
1336
1337 if (!clk_src)
1338 return NULL;
1339
1340 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1341 regs, &cs_shift, &cs_mask)) {
1342 clk_src->base.dp_clk_src = dp_clk_src;
1343 return &clk_src->base;
1344 }
1345
1346 kfree(clk_src);
1347 BREAK_TO_DEBUGGER();
1348 return NULL;
1349}
1350
1351static void read_dce_straps(
1352 struct dc_context *ctx,
1353 struct resource_straps *straps)
1354{
1355 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1356 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1357}
1358
1359static struct audio *dcn20_create_audio(
1360 struct dc_context *ctx, unsigned int inst)
1361{
1362 return dce_audio_create(ctx, inst,
1363 &audio_regs[inst], &audio_shift, &audio_mask);
1364}
1365
1366struct stream_encoder *dcn20_stream_encoder_create(
1367 enum engine_id eng_id,
1368 struct dc_context *ctx)
1369{
1370 struct dcn10_stream_encoder *enc1 =
1371 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1372
1373 if (!enc1)
1374 return NULL;
1375
1376 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1377 if (eng_id >= ENGINE_ID_DIGD)
1378 eng_id++;
1379 }
1380
1381 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1382 &stream_enc_regs[eng_id],
1383 &se_shift, &se_mask);
1384
1385 return &enc1->base;
1386}
1387
1388static const struct dce_hwseq_registers hwseq_reg = {
1389 HWSEQ_DCN2_REG_LIST()
1390};
1391
1392static const struct dce_hwseq_shift hwseq_shift = {
1393 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1394};
1395
1396static const struct dce_hwseq_mask hwseq_mask = {
1397 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1398};
1399
1400struct dce_hwseq *dcn20_hwseq_create(
1401 struct dc_context *ctx)
1402{
1403 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1404
1405 if (hws) {
1406 hws->ctx = ctx;
1407 hws->regs = &hwseq_reg;
1408 hws->shifts = &hwseq_shift;
1409 hws->masks = &hwseq_mask;
1410 }
1411 return hws;
1412}
1413
1414static const struct resource_create_funcs res_create_funcs = {
1415 .read_dce_straps = read_dce_straps,
1416 .create_audio = dcn20_create_audio,
1417 .create_stream_encoder = dcn20_stream_encoder_create,
1418 .create_hwseq = dcn20_hwseq_create,
1419};
1420
1421static const struct resource_create_funcs res_create_maximus_funcs = {
1422 .read_dce_straps = NULL,
1423 .create_audio = NULL,
1424 .create_stream_encoder = NULL,
1425 .create_hwseq = dcn20_hwseq_create,
1426};
1427
1428static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1429
1430void dcn20_clock_source_destroy(struct clock_source **clk_src)
1431{
1432 kfree(TO_DCE110_CLK_SRC(*clk_src));
1433 *clk_src = NULL;
1434}
1435
1436
1437struct display_stream_compressor *dcn20_dsc_create(
1438 struct dc_context *ctx, uint32_t inst)
1439{
1440 struct dcn20_dsc *dsc =
1441 kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
1442
1443 if (!dsc) {
1444 BREAK_TO_DEBUGGER();
1445 return NULL;
1446 }
1447
1448 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1449 return &dsc->base;
1450}
1451
1452void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1453{
1454 kfree(container_of(*dsc, struct dcn20_dsc, base));
1455 *dsc = NULL;
1456}
1457
1458
1459static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1460{
1461 unsigned int i;
1462
1463 for (i = 0; i < pool->base.stream_enc_count; i++) {
1464 if (pool->base.stream_enc[i] != NULL) {
1465 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1466 pool->base.stream_enc[i] = NULL;
1467 }
1468 }
1469
1470 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1471 if (pool->base.dscs[i] != NULL)
1472 dcn20_dsc_destroy(&pool->base.dscs[i]);
1473 }
1474
1475 if (pool->base.mpc != NULL) {
1476 kfree(TO_DCN20_MPC(pool->base.mpc));
1477 pool->base.mpc = NULL;
1478 }
1479 if (pool->base.hubbub != NULL) {
1480 kfree(pool->base.hubbub);
1481 pool->base.hubbub = NULL;
1482 }
1483 for (i = 0; i < pool->base.pipe_count; i++) {
1484 if (pool->base.dpps[i] != NULL)
1485 dcn20_dpp_destroy(&pool->base.dpps[i]);
1486
1487 if (pool->base.ipps[i] != NULL)
1488 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1489
1490 if (pool->base.hubps[i] != NULL) {
1491 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1492 pool->base.hubps[i] = NULL;
1493 }
1494
1495 if (pool->base.irqs != NULL) {
1496 dal_irq_service_destroy(&pool->base.irqs);
1497 }
1498 }
1499
1500 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1501 if (pool->base.engines[i] != NULL)
1502 dce110_engine_destroy(&pool->base.engines[i]);
1503 if (pool->base.hw_i2cs[i] != NULL) {
1504 kfree(pool->base.hw_i2cs[i]);
1505 pool->base.hw_i2cs[i] = NULL;
1506 }
1507 if (pool->base.sw_i2cs[i] != NULL) {
1508 kfree(pool->base.sw_i2cs[i]);
1509 pool->base.sw_i2cs[i] = NULL;
1510 }
1511 }
1512
1513 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1514 if (pool->base.opps[i] != NULL)
1515 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1516 }
1517
1518 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1519 if (pool->base.timing_generators[i] != NULL) {
1520 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1521 pool->base.timing_generators[i] = NULL;
1522 }
1523 }
1524
1525 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1526 if (pool->base.dwbc[i] != NULL) {
1527 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1528 pool->base.dwbc[i] = NULL;
1529 }
1530 if (pool->base.mcif_wb[i] != NULL) {
1531 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1532 pool->base.mcif_wb[i] = NULL;
1533 }
1534 }
1535
1536 for (i = 0; i < pool->base.audio_count; i++) {
1537 if (pool->base.audios[i])
1538 dce_aud_destroy(&pool->base.audios[i]);
1539 }
1540
1541 for (i = 0; i < pool->base.clk_src_count; i++) {
1542 if (pool->base.clock_sources[i] != NULL) {
1543 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1544 pool->base.clock_sources[i] = NULL;
1545 }
1546 }
1547
1548 if (pool->base.dp_clock_source != NULL) {
1549 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1550 pool->base.dp_clock_source = NULL;
1551 }
1552
1553
1554 if (pool->base.abm != NULL)
1555 dce_abm_destroy(&pool->base.abm);
1556
1557 if (pool->base.dmcu != NULL)
1558 dce_dmcu_destroy(&pool->base.dmcu);
1559
1560 if (pool->base.dccg != NULL)
1561 dcn_dccg_destroy(&pool->base.dccg);
1562
1563 if (pool->base.pp_smu != NULL)
1564 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1565
1566 if (pool->base.oem_device != NULL)
1567 dal_ddc_service_destroy(&pool->base.oem_device);
1568}
1569
1570struct hubp *dcn20_hubp_create(
1571 struct dc_context *ctx,
1572 uint32_t inst)
1573{
1574 struct dcn20_hubp *hubp2 =
1575 kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
1576
1577 if (!hubp2)
1578 return NULL;
1579
1580 if (hubp2_construct(hubp2, ctx, inst,
1581 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1582 return &hubp2->base;
1583
1584 BREAK_TO_DEBUGGER();
1585 kfree(hubp2);
1586 return NULL;
1587}
1588
1589static void get_pixel_clock_parameters(
1590 struct pipe_ctx *pipe_ctx,
1591 struct pixel_clk_params *pixel_clk_params)
1592{
1593 const struct dc_stream_state *stream = pipe_ctx->stream;
1594 struct pipe_ctx *odm_pipe;
1595 int opp_cnt = 1;
1596
1597 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1598 opp_cnt++;
1599
1600 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1601 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1602 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1603 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1604
1605 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1606 LINK_RATE_REF_FREQ_IN_KHZ;
1607 pixel_clk_params->flags.ENABLE_SS = 0;
1608 pixel_clk_params->color_depth =
1609 stream->timing.display_color_depth;
1610 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1611 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1612
1613 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1614 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1615
1616 if (opp_cnt == 4)
1617 pixel_clk_params->requested_pix_clk_100hz /= 4;
1618 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1619 pixel_clk_params->requested_pix_clk_100hz /= 2;
1620
1621 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1622 pixel_clk_params->requested_pix_clk_100hz *= 2;
1623
1624}
1625
1626static void build_clamping_params(struct dc_stream_state *stream)
1627{
1628 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1629 stream->clamping.c_depth = stream->timing.display_color_depth;
1630 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1631}
1632
1633static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1634{
1635
1636 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1637
1638 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1639 pipe_ctx->clock_source,
1640 &pipe_ctx->stream_res.pix_clk_params,
1641 &pipe_ctx->pll_settings);
1642
1643 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1644
1645 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1646 &pipe_ctx->stream->bit_depth_params);
1647 build_clamping_params(pipe_ctx->stream);
1648
1649 return DC_OK;
1650}
1651
1652enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1653{
1654 enum dc_status status = DC_OK;
1655 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1656
1657 if (!pipe_ctx)
1658 return DC_ERROR_UNEXPECTED;
1659
1660
1661 status = build_pipe_hw_param(pipe_ctx);
1662
1663 return status;
1664}
1665
1666
1667void dcn20_acquire_dsc(const struct dc *dc,
1668 struct resource_context *res_ctx,
1669 struct display_stream_compressor **dsc,
1670 int pipe_idx)
1671{
1672 int i;
1673 const struct resource_pool *pool = dc->res_pool;
1674 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1675
1676 ASSERT(*dsc == NULL);
1677 *dsc = NULL;
1678
1679
1680 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1681 *dsc = pool->dscs[pipe_idx];
1682 res_ctx->is_dsc_acquired[pipe_idx] = true;
1683 return;
1684 }
1685
1686
1687 if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1688 *dsc = dsc_old;
1689 res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1690 return ;
1691 }
1692
1693
1694 for (i = 0; i < pool->res_cap->num_dsc; i++)
1695 if (!res_ctx->is_dsc_acquired[i]) {
1696 *dsc = pool->dscs[i];
1697 res_ctx->is_dsc_acquired[i] = true;
1698 break;
1699 }
1700}
1701
1702void dcn20_release_dsc(struct resource_context *res_ctx,
1703 const struct resource_pool *pool,
1704 struct display_stream_compressor **dsc)
1705{
1706 int i;
1707
1708 for (i = 0; i < pool->res_cap->num_dsc; i++)
1709 if (pool->dscs[i] == *dsc) {
1710 res_ctx->is_dsc_acquired[i] = false;
1711 *dsc = NULL;
1712 break;
1713 }
1714}
1715
1716
1717
1718enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1719 struct dc_state *dc_ctx,
1720 struct dc_stream_state *dc_stream)
1721{
1722 enum dc_status result = DC_OK;
1723 int i;
1724
1725
1726 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1727 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1728
1729 if (pipe_ctx->stream != dc_stream)
1730 continue;
1731
1732 if (pipe_ctx->stream_res.dsc)
1733 continue;
1734
1735 dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1736
1737
1738 if (!pipe_ctx->stream_res.dsc) {
1739 result = DC_NO_DSC_RESOURCE;
1740 }
1741
1742 break;
1743 }
1744
1745 return result;
1746}
1747
1748
1749static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1750 struct dc_state *new_ctx,
1751 struct dc_stream_state *dc_stream)
1752{
1753 struct pipe_ctx *pipe_ctx = NULL;
1754 int i;
1755
1756 for (i = 0; i < MAX_PIPES; i++) {
1757 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1758 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1759
1760 if (pipe_ctx->stream_res.dsc)
1761 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1762 }
1763 }
1764
1765 if (!pipe_ctx)
1766 return DC_ERROR_UNEXPECTED;
1767 else
1768 return DC_OK;
1769}
1770
1771
1772enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1773{
1774 enum dc_status result = DC_ERROR_UNEXPECTED;
1775
1776 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1777
1778 if (result == DC_OK)
1779 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1780
1781
1782 if (result == DC_OK && dc_stream->timing.flags.DSC)
1783 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1784
1785 if (result == DC_OK)
1786 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1787
1788 return result;
1789}
1790
1791
1792enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1793{
1794 enum dc_status result = DC_OK;
1795
1796 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1797
1798 return result;
1799}
1800
1801
1802static void swizzle_to_dml_params(
1803 enum swizzle_mode_values swizzle,
1804 unsigned int *sw_mode)
1805{
1806 switch (swizzle) {
1807 case DC_SW_LINEAR:
1808 *sw_mode = dm_sw_linear;
1809 break;
1810 case DC_SW_4KB_S:
1811 *sw_mode = dm_sw_4kb_s;
1812 break;
1813 case DC_SW_4KB_S_X:
1814 *sw_mode = dm_sw_4kb_s_x;
1815 break;
1816 case DC_SW_4KB_D:
1817 *sw_mode = dm_sw_4kb_d;
1818 break;
1819 case DC_SW_4KB_D_X:
1820 *sw_mode = dm_sw_4kb_d_x;
1821 break;
1822 case DC_SW_64KB_S:
1823 *sw_mode = dm_sw_64kb_s;
1824 break;
1825 case DC_SW_64KB_S_X:
1826 *sw_mode = dm_sw_64kb_s_x;
1827 break;
1828 case DC_SW_64KB_S_T:
1829 *sw_mode = dm_sw_64kb_s_t;
1830 break;
1831 case DC_SW_64KB_D:
1832 *sw_mode = dm_sw_64kb_d;
1833 break;
1834 case DC_SW_64KB_D_X:
1835 *sw_mode = dm_sw_64kb_d_x;
1836 break;
1837 case DC_SW_64KB_D_T:
1838 *sw_mode = dm_sw_64kb_d_t;
1839 break;
1840 case DC_SW_64KB_R_X:
1841 *sw_mode = dm_sw_64kb_r_x;
1842 break;
1843 case DC_SW_VAR_S:
1844 *sw_mode = dm_sw_var_s;
1845 break;
1846 case DC_SW_VAR_S_X:
1847 *sw_mode = dm_sw_var_s_x;
1848 break;
1849 case DC_SW_VAR_D:
1850 *sw_mode = dm_sw_var_d;
1851 break;
1852 case DC_SW_VAR_D_X:
1853 *sw_mode = dm_sw_var_d_x;
1854 break;
1855
1856 default:
1857 ASSERT(0);
1858 break;
1859 }
1860}
1861
1862bool dcn20_split_stream_for_odm(
1863 const struct dc *dc,
1864 struct resource_context *res_ctx,
1865 struct pipe_ctx *prev_odm_pipe,
1866 struct pipe_ctx *next_odm_pipe)
1867{
1868 int pipe_idx = next_odm_pipe->pipe_idx;
1869 const struct resource_pool *pool = dc->res_pool;
1870
1871 *next_odm_pipe = *prev_odm_pipe;
1872
1873 next_odm_pipe->pipe_idx = pipe_idx;
1874 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1875 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1876 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1877 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1878 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1879 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1880 next_odm_pipe->stream_res.dsc = NULL;
1881 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1882 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1883 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1884 }
1885 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1886 prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1887 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1888 }
1889 if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1890 prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1891 next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1892 }
1893 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1894 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1895
1896 if (prev_odm_pipe->plane_state) {
1897 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1898 int new_width;
1899
1900
1901 sd->h_active /= 2;
1902
1903
1904 if (sd->recout.x + 16 >= sd->h_active)
1905 return false;
1906 new_width = sd->h_active - sd->recout.x;
1907 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1908 sd->ratios.horz, sd->recout.width - new_width));
1909 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1910 sd->ratios.horz_c, sd->recout.width - new_width));
1911 sd->recout.width = new_width;
1912
1913
1914 sd = &next_odm_pipe->plane_res.scl_data;
1915
1916 sd->h_active /= 2;
1917
1918 if (new_width <= 16)
1919 return false;
1920 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1921 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1922 sd->ratios.horz, sd->recout.width - new_width));
1923 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1924 sd->ratios.horz_c, sd->recout.width - new_width));
1925 sd->recout.width = new_width;
1926 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1927 sd->ratios.horz, sd->h_active - sd->recout.x));
1928 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1929 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1930 sd->recout.x = 0;
1931 }
1932 if (!next_odm_pipe->top_pipe)
1933 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1934 else
1935 next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
1936 if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
1937 dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1938 ASSERT(next_odm_pipe->stream_res.dsc);
1939 if (next_odm_pipe->stream_res.dsc == NULL)
1940 return false;
1941 }
1942
1943 return true;
1944}
1945
1946void dcn20_split_stream_for_mpc(
1947 struct resource_context *res_ctx,
1948 const struct resource_pool *pool,
1949 struct pipe_ctx *primary_pipe,
1950 struct pipe_ctx *secondary_pipe)
1951{
1952 int pipe_idx = secondary_pipe->pipe_idx;
1953 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1954
1955 *secondary_pipe = *primary_pipe;
1956 secondary_pipe->bottom_pipe = sec_bot_pipe;
1957
1958 secondary_pipe->pipe_idx = pipe_idx;
1959 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1960 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1961 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1962 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1963 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1964 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1965 secondary_pipe->stream_res.dsc = NULL;
1966 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1967 ASSERT(!secondary_pipe->bottom_pipe);
1968 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1969 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1970 }
1971 primary_pipe->bottom_pipe = secondary_pipe;
1972 secondary_pipe->top_pipe = primary_pipe;
1973
1974 ASSERT(primary_pipe->plane_state);
1975}
1976
1977void dcn20_populate_dml_writeback_from_context(
1978 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1979{
1980 int pipe_cnt, i;
1981
1982 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1983 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1984
1985 if (!res_ctx->pipe_ctx[i].stream)
1986 continue;
1987
1988
1989 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1990 pipes[pipe_cnt].dout.num_active_wb++;
1991 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1992 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1993 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1994 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1995 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1996 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1997 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1998 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1999 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
2000 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
2001 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
2002 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2003 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
2004 else
2005 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
2006 } else
2007 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
2008
2009 pipe_cnt++;
2010 }
2011
2012}
2013
2014int dcn20_populate_dml_pipes_from_context(
2015 struct dc *dc,
2016 struct dc_state *context,
2017 display_e2e_pipe_params_st *pipes,
2018 bool fast_validate)
2019{
2020 int pipe_cnt, i;
2021 bool synchronized_vblank = true;
2022 struct resource_context *res_ctx = &context->res_ctx;
2023
2024 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2025 if (!res_ctx->pipe_ctx[i].stream)
2026 continue;
2027
2028 if (pipe_cnt < 0) {
2029 pipe_cnt = i;
2030 continue;
2031 }
2032
2033 if (res_ctx->pipe_ctx[pipe_cnt].stream == res_ctx->pipe_ctx[i].stream)
2034 continue;
2035
2036 if (dc->debug.disable_timing_sync ||
2037 (!resource_are_streams_timing_synchronizable(
2038 res_ctx->pipe_ctx[pipe_cnt].stream,
2039 res_ctx->pipe_ctx[i].stream) &&
2040 !resource_are_vblanks_synchronizable(
2041 res_ctx->pipe_ctx[pipe_cnt].stream,
2042 res_ctx->pipe_ctx[i].stream))) {
2043 synchronized_vblank = false;
2044 break;
2045 }
2046 }
2047
2048 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2049 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2050 unsigned int v_total;
2051 unsigned int front_porch;
2052 int output_bpc;
2053 struct audio_check aud_check = {0};
2054
2055 if (!res_ctx->pipe_ctx[i].stream)
2056 continue;
2057
2058 v_total = timing->v_total;
2059 front_porch = timing->v_front_porch;
2060
2061
2062
2063
2064
2065
2066 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2067
2068 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2069
2070 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2071 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2072 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2073
2074 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2075 (v_total - timing->v_addressable
2076 - timing->v_border_top - timing->v_border_bottom) / 2;
2077
2078 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2079 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2080 }
2081 pipes[pipe_cnt].pipe.src.dcc = false;
2082 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2083 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2084 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2085 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2086 - timing->h_addressable
2087 - timing->h_border_left
2088 - timing->h_border_right;
2089 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
2090 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2091 - timing->v_addressable
2092 - timing->v_border_top
2093 - timing->v_border_bottom;
2094 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2095 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
2096 pipes[pipe_cnt].pipe.dest.hactive =
2097 timing->h_addressable + timing->h_border_left + timing->h_border_right;
2098 pipes[pipe_cnt].pipe.dest.vactive =
2099 timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
2100 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2101 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2102 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2103 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2104 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
2105 pipes[pipe_cnt].dout.dp_lanes = 4;
2106 pipes[pipe_cnt].dout.is_virtual = 0;
2107 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2108 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
2109 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2110 case 1:
2111 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2112 break;
2113 case 3:
2114 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
2115 break;
2116 default:
2117 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2118 }
2119 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2120 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
2121 == res_ctx->pipe_ctx[i].plane_state) {
2122 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
2123 int split_idx = 0;
2124
2125 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
2126 == res_ctx->pipe_ctx[i].plane_state) {
2127 first_pipe = first_pipe->top_pipe;
2128 split_idx++;
2129 }
2130
2131 if (split_idx == 0)
2132 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2133 else if (split_idx == 1)
2134 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2135 else if (split_idx == 2)
2136 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx;
2137 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
2138 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2139
2140 while (first_pipe->prev_odm_pipe)
2141 first_pipe = first_pipe->prev_odm_pipe;
2142 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2143 }
2144
2145 switch (res_ctx->pipe_ctx[i].stream->signal) {
2146 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2147 case SIGNAL_TYPE_DISPLAY_PORT:
2148 pipes[pipe_cnt].dout.output_type = dm_dp;
2149 break;
2150 case SIGNAL_TYPE_EDP:
2151 pipes[pipe_cnt].dout.output_type = dm_edp;
2152 break;
2153 case SIGNAL_TYPE_HDMI_TYPE_A:
2154 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2155 case SIGNAL_TYPE_DVI_DUAL_LINK:
2156 pipes[pipe_cnt].dout.output_type = dm_hdmi;
2157 break;
2158 default:
2159
2160 pipes[pipe_cnt].dout.is_virtual = 1;
2161 pipes[pipe_cnt].dout.output_type = dm_dp;
2162 pipes[pipe_cnt].dout.dp_lanes = 4;
2163 }
2164
2165 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2166 case COLOR_DEPTH_666:
2167 output_bpc = 6;
2168 break;
2169 case COLOR_DEPTH_888:
2170 output_bpc = 8;
2171 break;
2172 case COLOR_DEPTH_101010:
2173 output_bpc = 10;
2174 break;
2175 case COLOR_DEPTH_121212:
2176 output_bpc = 12;
2177 break;
2178 case COLOR_DEPTH_141414:
2179 output_bpc = 14;
2180 break;
2181 case COLOR_DEPTH_161616:
2182 output_bpc = 16;
2183 break;
2184 case COLOR_DEPTH_999:
2185 output_bpc = 9;
2186 break;
2187 case COLOR_DEPTH_111111:
2188 output_bpc = 11;
2189 break;
2190 default:
2191 output_bpc = 8;
2192 break;
2193 }
2194
2195 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2196 case PIXEL_ENCODING_RGB:
2197 case PIXEL_ENCODING_YCBCR444:
2198 pipes[pipe_cnt].dout.output_format = dm_444;
2199 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2200 break;
2201 case PIXEL_ENCODING_YCBCR420:
2202 pipes[pipe_cnt].dout.output_format = dm_420;
2203 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2204 break;
2205 case PIXEL_ENCODING_YCBCR422:
2206 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC &&
2207 !res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.ycbcr422_simple)
2208 pipes[pipe_cnt].dout.output_format = dm_n422;
2209 else
2210 pipes[pipe_cnt].dout.output_format = dm_s422;
2211 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2212 break;
2213 default:
2214 pipes[pipe_cnt].dout.output_format = dm_444;
2215 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2216 }
2217
2218 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2219 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2220
2221
2222 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
2223
2224 get_audio_check(&res_ctx->pipe_ctx[i].stream->audio_info, &aud_check);
2225 pipes[pipe_cnt].dout.max_audio_sample_rate = aud_check.max_audiosample_rate / 1000;
2226
2227
2228
2229
2230 if (res_ctx->pipe_ctx[i].plane_state &&
2231 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2232 pipes[pipe_cnt].pipe.src.num_cursors = 0;
2233 else
2234 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2235
2236 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2237 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2238
2239 if (!res_ctx->pipe_ctx[i].plane_state) {
2240 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2241 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2242 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_4kb_s;
2243 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2244 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2245 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2246 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2247 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2248 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2249 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2250 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2251 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2252 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2253 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2254 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 255) / 256) * 256;
2255 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2256 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width;
2257 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height;
2258 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;
2259 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height;
2260 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2261 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2262 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2263 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0;
2264 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2265 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2266 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2267 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2268
2269 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2270 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2271 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
2272 } else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
2273 pipes[pipe_cnt].pipe.src.viewport_width /= 4;
2274 pipes[pipe_cnt].pipe.dest.recout_width /= 4;
2275 }
2276 } else {
2277 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2278 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2279
2280 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2281 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2282 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2283 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2284
2285
2286 if (pln->stereo_format == PLANE_STEREO_FORMAT_SIDE_BY_SIDE ||
2287 pln->stereo_format == PLANE_STEREO_FORMAT_TOP_AND_BOTTOM) {
2288 pipes[pipe_cnt].pipe.src.is_hsplit = false;
2289 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2290 }
2291
2292 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2293 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2294 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2295 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2296 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2297 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2298 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2299 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
2300 pipes[pipe_cnt].pipe.src.viewport_width_max = pln->src_rect.width;
2301 pipes[pipe_cnt].pipe.src.viewport_height_max = pln->src_rect.height;
2302 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
2303 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2304 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2305 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
2306 if (pln->format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA
2307 || pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2308 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2309 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2310 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2311 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2312 } else {
2313 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2314 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2315 }
2316 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2317 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2318 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2319 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2320 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2321 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2322 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
2323 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
2324 pipes[pipe_cnt].pipe.dest.full_recout_width *= 4;
2325 else {
2326 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2327
2328 while (split_pipe && split_pipe->plane_state == pln) {
2329 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2330 split_pipe = split_pipe->bottom_pipe;
2331 }
2332 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2333 while (split_pipe && split_pipe->plane_state == pln) {
2334 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2335 split_pipe = split_pipe->top_pipe;
2336 }
2337 }
2338
2339 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2340 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2341 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2342 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2343 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2344 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2345 scl->ratios.vert.value != dc_fixpt_one.value
2346 || scl->ratios.horz.value != dc_fixpt_one.value
2347 || scl->ratios.vert_c.value != dc_fixpt_one.value
2348 || scl->ratios.horz_c.value != dc_fixpt_one.value
2349 || dc->debug.always_scale;
2350 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2351 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2352 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2353 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2354
2355 pipes[pipe_cnt].pipe.src.macro_tile_size =
2356 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2357 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2358 &pipes[pipe_cnt].pipe.src.sw_mode);
2359
2360 switch (pln->format) {
2361 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2362 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2363 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2364 break;
2365 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2366 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2367 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2368 break;
2369 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2370 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
2371 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2372 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2373 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2374 break;
2375 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2376 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2377 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2378 break;
2379 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2380 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2381 break;
2382 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
2383 pipes[pipe_cnt].pipe.src.source_format = dm_rgbe_alpha;
2384 break;
2385 default:
2386 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2387 break;
2388 }
2389 }
2390
2391 pipe_cnt++;
2392 }
2393
2394
2395 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2396
2397 return pipe_cnt;
2398}
2399
2400unsigned int dcn20_calc_max_scaled_time(
2401 unsigned int time_per_pixel,
2402 enum mmhubbub_wbif_mode mode,
2403 unsigned int urgent_watermark)
2404{
2405 unsigned int time_per_byte = 0;
2406 unsigned int total_y_free_entry = 0x200;
2407 unsigned int total_c_free_entry = 0x140;
2408 unsigned int small_free_entry, max_free_entry;
2409 unsigned int buf_lh_capability;
2410 unsigned int max_scaled_time;
2411
2412 if (mode == PACKED_444)
2413 time_per_byte = time_per_pixel/4;
2414 else if (mode == PLANAR_420_8BPC)
2415 time_per_byte = time_per_pixel;
2416 else if (mode == PLANAR_420_10BPC)
2417 time_per_byte = time_per_pixel * 819/1024;
2418
2419 if (time_per_byte == 0)
2420 time_per_byte = 1;
2421
2422 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2423 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2424 buf_lh_capability = max_free_entry*time_per_byte*32/16;
2425 max_scaled_time = buf_lh_capability - urgent_watermark;
2426 return max_scaled_time;
2427}
2428
2429void dcn20_set_mcif_arb_params(
2430 struct dc *dc,
2431 struct dc_state *context,
2432 display_e2e_pipe_params_st *pipes,
2433 int pipe_cnt)
2434{
2435 enum mmhubbub_wbif_mode wbif_mode;
2436 struct mcif_arb_params *wb_arb_params;
2437 int i, j, k, dwb_pipe;
2438
2439
2440 dwb_pipe = 0;
2441 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2442
2443 if (!context->res_ctx.pipe_ctx[i].stream)
2444 continue;
2445
2446 for (j = 0; j < MAX_DWB_PIPES; j++) {
2447 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2448 continue;
2449
2450
2451 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2452
2453 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2454 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2455 wbif_mode = PLANAR_420_8BPC;
2456 else
2457 wbif_mode = PLANAR_420_10BPC;
2458 } else
2459 wbif_mode = PACKED_444;
2460
2461 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2462 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2463 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2464 }
2465 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk;
2466 wb_arb_params->slice_lines = 32;
2467 wb_arb_params->arbitration_slice = 2;
2468 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2469 wbif_mode,
2470 wb_arb_params->cli_watermark[0]);
2471
2472 dwb_pipe++;
2473
2474 if (dwb_pipe >= MAX_DWB_PIPES)
2475 return;
2476 }
2477 if (dwb_pipe >= MAX_DWB_PIPES)
2478 return;
2479 }
2480}
2481
2482bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2483{
2484 int i;
2485
2486
2487 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2488 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2489 struct dc_stream_state *stream = pipe_ctx->stream;
2490 struct dsc_config dsc_cfg;
2491 struct pipe_ctx *odm_pipe;
2492 int opp_cnt = 1;
2493
2494 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2495 opp_cnt++;
2496
2497
2498 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2499 continue;
2500
2501 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2502 + stream->timing.h_border_right) / opp_cnt;
2503 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2504 + stream->timing.v_border_bottom;
2505 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2506 dsc_cfg.color_depth = stream->timing.display_color_depth;
2507 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
2508 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2509 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2510
2511 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2512 return false;
2513 }
2514 return true;
2515}
2516
2517struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2518 struct resource_context *res_ctx,
2519 const struct resource_pool *pool,
2520 const struct pipe_ctx *primary_pipe)
2521{
2522 struct pipe_ctx *secondary_pipe = NULL;
2523
2524 if (dc && primary_pipe) {
2525 int j;
2526 int preferred_pipe_idx = 0;
2527
2528
2529
2530
2531
2532
2533
2534 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2535 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2536 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2537 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2538 secondary_pipe->pipe_idx = preferred_pipe_idx;
2539 }
2540 }
2541 if (secondary_pipe == NULL &&
2542 dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2543 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2544 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2545 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2546 secondary_pipe->pipe_idx = preferred_pipe_idx;
2547 }
2548 }
2549
2550
2551
2552
2553
2554
2555
2556 if (secondary_pipe == NULL) {
2557 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2558 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2559 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
2560 preferred_pipe_idx = j;
2561
2562 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2563 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2564 secondary_pipe->pipe_idx = preferred_pipe_idx;
2565 break;
2566 }
2567 }
2568 }
2569 }
2570
2571
2572
2573
2574 ASSERT(secondary_pipe);
2575
2576
2577
2578
2579 if (secondary_pipe == NULL) {
2580 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2581 preferred_pipe_idx = j;
2582
2583 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2584 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2585 secondary_pipe->pipe_idx = preferred_pipe_idx;
2586 break;
2587 }
2588 }
2589 }
2590 }
2591
2592 return secondary_pipe;
2593}
2594
2595void dcn20_merge_pipes_for_validate(
2596 struct dc *dc,
2597 struct dc_state *context)
2598{
2599 int i;
2600
2601
2602 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2603 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2604 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2605
2606 if (pipe->prev_odm_pipe)
2607 continue;
2608
2609 pipe->next_odm_pipe = NULL;
2610 while (odm_pipe) {
2611 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2612
2613 odm_pipe->plane_state = NULL;
2614 odm_pipe->stream = NULL;
2615 odm_pipe->top_pipe = NULL;
2616 odm_pipe->bottom_pipe = NULL;
2617 odm_pipe->prev_odm_pipe = NULL;
2618 odm_pipe->next_odm_pipe = NULL;
2619 if (odm_pipe->stream_res.dsc)
2620 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2621
2622 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2623 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2624 odm_pipe = next_odm_pipe;
2625 }
2626 if (pipe->plane_state)
2627 resource_build_scaling_params(pipe);
2628 }
2629
2630
2631 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2632 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2633 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2634
2635 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2636 continue;
2637
2638 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2639 if (hsplit_pipe->bottom_pipe)
2640 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2641 hsplit_pipe->plane_state = NULL;
2642 hsplit_pipe->stream = NULL;
2643 hsplit_pipe->top_pipe = NULL;
2644 hsplit_pipe->bottom_pipe = NULL;
2645
2646
2647 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2648 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2649 if (pipe->plane_state)
2650 resource_build_scaling_params(pipe);
2651 }
2652}
2653
2654int dcn20_validate_apply_pipe_split_flags(
2655 struct dc *dc,
2656 struct dc_state *context,
2657 int vlevel,
2658 int *split,
2659 bool *merge)
2660{
2661 int i, pipe_idx, vlevel_split;
2662 int plane_count = 0;
2663 bool force_split = false;
2664 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
2665 struct vba_vars_st *v = &context->bw_ctx.dml.vba;
2666 int max_mpc_comb = v->maxMpcComb;
2667
2668 if (context->stream_count > 1) {
2669 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2670 avoid_split = true;
2671 } else if (dc->debug.force_single_disp_pipe_split)
2672 force_split = true;
2673
2674 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2675 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2676
2677
2678
2679
2680
2681
2682 if (pipe->plane_state &&
2683 (pipe->plane_state->dst_rect.width <= 16 ||
2684 pipe->plane_state->dst_rect.height <= 16 ||
2685 pipe->plane_state->src_rect.width <= 16 ||
2686 pipe->plane_state->src_rect.height <= 16))
2687 avoid_split = true;
2688
2689
2690 if (pipe->stream && !pipe->prev_odm_pipe &&
2691 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2692 ++plane_count;
2693 }
2694 if (plane_count > dc->res_pool->pipe_count / 2)
2695 avoid_split = true;
2696
2697
2698 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2699 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2700 struct dc_crtc_timing timing;
2701
2702 if (!pipe->stream)
2703 continue;
2704 else {
2705 timing = pipe->stream->timing;
2706 if (timing.h_border_left + timing.h_border_right
2707 + timing.v_border_top + timing.v_border_bottom > 0) {
2708 avoid_split = true;
2709 break;
2710 }
2711 }
2712 }
2713
2714
2715 if (avoid_split) {
2716 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2717 if (!context->res_ctx.pipe_ctx[i].stream)
2718 continue;
2719
2720 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2721 if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
2722 v->ModeSupport[vlevel][0])
2723 break;
2724
2725 if (vlevel > context->bw_ctx.dml.soc.num_states)
2726 vlevel = vlevel_split;
2727 else
2728 max_mpc_comb = 0;
2729 pipe_idx++;
2730 }
2731 v->maxMpcComb = max_mpc_comb;
2732 }
2733
2734
2735 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2736 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2737 int pipe_plane = v->pipe_plane[pipe_idx];
2738 bool split4mpc = context->stream_count == 1 && plane_count == 1
2739 && dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
2740
2741 if (!context->res_ctx.pipe_ctx[i].stream)
2742 continue;
2743
2744 if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
2745 split[i] = 4;
2746 else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
2747 split[i] = 2;
2748
2749 if ((pipe->stream->view_format ==
2750 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2751 pipe->stream->view_format ==
2752 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2753 (pipe->stream->timing.timing_3d_format ==
2754 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2755 pipe->stream->timing.timing_3d_format ==
2756 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2757 split[i] = 2;
2758 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2759 split[i] = 2;
2760 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
2761 }
2762 if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
2763 split[i] = 4;
2764 v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
2765 }
2766
2767 if (pipe->stream->timing.h_addressable > 7680 &&
2768 pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
2769 split[i] = 4;
2770 }
2771 v->ODMCombineEnabled[pipe_plane] =
2772 v->ODMCombineEnablePerState[vlevel][pipe_plane];
2773
2774 if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2775 if (get_num_mpc_splits(pipe) == 1) {
2776
2777 if (split[i] == 4)
2778 split[i] = 2;
2779 else if (split[i] == 2)
2780 split[i] = 0;
2781 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
2782 merge[i] = true;
2783 } else if (get_num_mpc_splits(pipe) == 3) {
2784
2785 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
2786 || !pipe->bottom_pipe)) {
2787 merge[i] = true;
2788 } else if (split[i] == 0 && pipe->top_pipe &&
2789 pipe->top_pipe->plane_state == pipe->plane_state)
2790 merge[i] = true;
2791 split[i] = 0;
2792 } else if (get_num_odm_splits(pipe)) {
2793
2794 if (pipe->prev_odm_pipe) {
2795 split[i] = 0;
2796 merge[i] = true;
2797 }
2798 }
2799 } else {
2800 if (get_num_odm_splits(pipe) == 1) {
2801
2802 if (split[i] == 4)
2803 split[i] = 2;
2804 else if (split[i] == 2)
2805 split[i] = 0;
2806 else if (pipe->prev_odm_pipe) {
2807 ASSERT(0);
2808 merge[i] = true;
2809 }
2810 } else if (get_num_odm_splits(pipe) == 3) {
2811
2812 if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
2813 || !pipe->next_odm_pipe)) {
2814 ASSERT(0);
2815 merge[i] = true;
2816 } else if (split[i] == 0 && pipe->prev_odm_pipe) {
2817 ASSERT(0);
2818 merge[i] = true;
2819 }
2820 split[i] = 0;
2821 } else if (get_num_mpc_splits(pipe)) {
2822
2823 ASSERT(0);
2824 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2825 split[i] = 0;
2826 merge[i] = true;
2827 }
2828 }
2829 }
2830
2831
2832 if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1)
2833 v->RequiredDPPCLK[vlevel][max_mpc_comb][pipe_idx] /= 2;
2834 pipe_idx++;
2835 }
2836
2837 return vlevel;
2838}
2839
2840bool dcn20_fast_validate_bw(
2841 struct dc *dc,
2842 struct dc_state *context,
2843 display_e2e_pipe_params_st *pipes,
2844 int *pipe_cnt_out,
2845 int *pipe_split_from,
2846 int *vlevel_out,
2847 bool fast_validate)
2848{
2849 bool out = false;
2850 int split[MAX_PIPES] = { 0 };
2851 int pipe_cnt, i, pipe_idx, vlevel;
2852
2853 ASSERT(pipes);
2854 if (!pipes)
2855 return false;
2856
2857 dcn20_merge_pipes_for_validate(dc, context);
2858
2859 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2860
2861 *pipe_cnt_out = pipe_cnt;
2862
2863 if (!pipe_cnt) {
2864 out = true;
2865 goto validate_out;
2866 }
2867
2868 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2869
2870 if (vlevel > context->bw_ctx.dml.soc.num_states)
2871 goto validate_fail;
2872
2873 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2874
2875
2876 for (i = 0; i < MAX_PIPES; i++)
2877 pipe_split_from[i] = -1;
2878
2879 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2880 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2881 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2882
2883 if (!pipe->stream || pipe_split_from[i] >= 0)
2884 continue;
2885
2886 pipe_idx++;
2887
2888 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2889 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2890 ASSERT(hsplit_pipe);
2891 if (!dcn20_split_stream_for_odm(
2892 dc, &context->res_ctx,
2893 pipe, hsplit_pipe))
2894 goto validate_fail;
2895 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2896 dcn20_build_mapped_resource(dc, context, pipe->stream);
2897 }
2898
2899 if (!pipe->plane_state)
2900 continue;
2901
2902 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2903 continue;
2904
2905
2906 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2907 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2908 goto validate_fail;
2909
2910 if (split[i] == 2) {
2911 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2912
2913 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2914 ASSERT(hsplit_pipe);
2915 if (!hsplit_pipe) {
2916 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2917 continue;
2918 }
2919 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2920 if (!dcn20_split_stream_for_odm(
2921 dc, &context->res_ctx,
2922 pipe, hsplit_pipe))
2923 goto validate_fail;
2924 dcn20_build_mapped_resource(dc, context, pipe->stream);
2925 } else {
2926 dcn20_split_stream_for_mpc(
2927 &context->res_ctx, dc->res_pool,
2928 pipe, hsplit_pipe);
2929 resource_build_scaling_params(pipe);
2930 resource_build_scaling_params(hsplit_pipe);
2931 }
2932 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2933 }
2934 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2935
2936 ASSERT(0);
2937 }
2938 }
2939
2940 if (!dcn20_validate_dsc(dc, context)) {
2941 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2942 DML_FAIL_DSC_VALIDATION_FAILURE;
2943 goto validate_fail;
2944 }
2945
2946 *vlevel_out = vlevel;
2947
2948 out = true;
2949 goto validate_out;
2950
2951validate_fail:
2952 out = false;
2953
2954validate_out:
2955 return out;
2956}
2957
2958static void dcn20_calculate_wm(
2959 struct dc *dc, struct dc_state *context,
2960 display_e2e_pipe_params_st *pipes,
2961 int *out_pipe_cnt,
2962 int *pipe_split_from,
2963 int vlevel,
2964 bool fast_validate)
2965{
2966 int pipe_cnt, i, pipe_idx;
2967
2968 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2969 if (!context->res_ctx.pipe_ctx[i].stream)
2970 continue;
2971
2972 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2973 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2974
2975 if (pipe_split_from[i] < 0) {
2976 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2977 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2978 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2979 pipes[pipe_cnt].pipe.dest.odm_combine =
2980 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
2981 else
2982 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2983 pipe_idx++;
2984 } else {
2985 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2986 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2987 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2988 pipes[pipe_cnt].pipe.dest.odm_combine =
2989 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
2990 else
2991 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2992 }
2993
2994 if (dc->config.forced_clocks) {
2995 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2996 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2997 }
2998 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2999 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
3000 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
3001 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
3002
3003 pipe_cnt++;
3004 }
3005
3006 if (pipe_cnt != pipe_idx) {
3007 if (dc->res_pool->funcs->populate_dml_pipes)
3008 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
3009 context, pipes, fast_validate);
3010 else
3011 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
3012 context, pipes, fast_validate);
3013 }
3014
3015 *out_pipe_cnt = pipe_cnt;
3016
3017 pipes[0].clks_cfg.voltage = vlevel;
3018 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3019 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3020
3021
3022 if (vlevel < 1) {
3023 pipes[0].clks_cfg.voltage = 1;
3024 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
3025 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
3026 }
3027 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3028 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3029 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3030 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3031 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3032 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3033 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3034 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3035
3036 if (vlevel < 2) {
3037 pipes[0].clks_cfg.voltage = 2;
3038 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3039 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3040 }
3041 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3042 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3043 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3044 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3045 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3046 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3047 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3048
3049 if (vlevel < 3) {
3050 pipes[0].clks_cfg.voltage = 3;
3051 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
3052 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
3053 }
3054 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3055 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3056 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3057 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3058 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3059 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3060 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3061
3062 pipes[0].clks_cfg.voltage = vlevel;
3063 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
3064 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
3065 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3066 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3067 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3068 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3069 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3070 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3071 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
3072}
3073
3074static bool is_dtbclk_required(struct dc *dc, struct dc_state *context)
3075{
3076 int i;
3077 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3078 if (!context->res_ctx.pipe_ctx[i].stream)
3079 continue;
3080 }
3081 return false;
3082}
3083
3084static enum dcn_zstate_support_state decide_zstate_support(struct dc *dc, struct dc_state *context)
3085{
3086 int plane_count;
3087 int i;
3088
3089 plane_count = 0;
3090 for (i = 0; i < dc->res_pool->pipe_count; i++) {
3091 if (context->res_ctx.pipe_ctx[i].plane_state)
3092 plane_count++;
3093 }
3094
3095
3096
3097
3098
3099
3100
3101 if (plane_count == 0)
3102 return DCN_ZSTATE_SUPPORT_ALLOW;
3103 else if (context->stream_count == 1 && context->streams[0]->signal == SIGNAL_TYPE_EDP) {
3104 struct dc_link *link = context->streams[0]->sink->link;
3105
3106 if ((link->link_index == 0 && link->psr_settings.psr_feature_enabled)
3107 || context->bw_ctx.dml.vba.StutterPeriod > 5000.0)
3108 return DCN_ZSTATE_SUPPORT_ALLOW;
3109 else
3110 return DCN_ZSTATE_SUPPORT_DISALLOW;
3111 } else
3112 return DCN_ZSTATE_SUPPORT_DISALLOW;
3113}
3114
3115void dcn20_calculate_dlg_params(
3116 struct dc *dc, struct dc_state *context,
3117 display_e2e_pipe_params_st *pipes,
3118 int pipe_cnt,
3119 int vlevel)
3120{
3121 int i, pipe_idx;
3122
3123
3124 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
3125
3126 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
3127 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
3128 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
3129 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
3130 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
3131 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
3132 context->bw_ctx.bw.dcn.clk.p_state_change_support =
3133 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
3134 != dm_dram_clock_change_unsupported;
3135 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
3136
3137 context->bw_ctx.bw.dcn.clk.zstate_support = decide_zstate_support(dc, context);
3138
3139 context->bw_ctx.bw.dcn.clk.dtbclk_en = is_dtbclk_required(dc, context);
3140
3141 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
3142 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
3143
3144 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3145 if (!context->res_ctx.pipe_ctx[i].stream)
3146 continue;
3147 pipes[pipe_idx].pipe.dest.vstartup_start = get_vstartup(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3148 pipes[pipe_idx].pipe.dest.vupdate_offset = get_vupdate_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3149 pipes[pipe_idx].pipe.dest.vupdate_width = get_vupdate_width(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3150 pipes[pipe_idx].pipe.dest.vready_offset = get_vready_offset(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
3151 context->res_ctx.pipe_ctx[i].det_buffer_size_kb = context->bw_ctx.dml.ip.det_buffer_size_kbytes;
3152 context->res_ctx.pipe_ctx[i].unbounded_req = pipes[pipe_idx].pipe.src.unbounded_req_mode;
3153
3154 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3155 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3156 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
3157 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3158 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3159 pipe_idx++;
3160 }
3161
3162 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3163 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
3164 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
3165 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
3166
3167 context->bw_ctx.bw.dcn.compbuf_size_kb = context->bw_ctx.dml.ip.config_return_buffer_size_in_kbytes
3168 - context->bw_ctx.dml.ip.det_buffer_size_kbytes * pipe_idx;
3169
3170 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3171 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
3172
3173 if (!context->res_ctx.pipe_ctx[i].stream)
3174 continue;
3175
3176 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3177 &context->res_ctx.pipe_ctx[i].dlg_regs,
3178 &context->res_ctx.pipe_ctx[i].ttu_regs,
3179 pipes,
3180 pipe_cnt,
3181 pipe_idx,
3182 cstate_en,
3183 context->bw_ctx.bw.dcn.clk.p_state_change_support,
3184 false, false, true);
3185
3186 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3187 &context->res_ctx.pipe_ctx[i].rq_regs,
3188 pipes[pipe_idx].pipe);
3189 pipe_idx++;
3190 }
3191}
3192
3193static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
3194 bool fast_validate)
3195{
3196 bool out = false;
3197
3198 BW_VAL_TRACE_SETUP();
3199
3200 int vlevel = 0;
3201 int pipe_split_from[MAX_PIPES];
3202 int pipe_cnt = 0;
3203 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
3204 DC_LOGGER_INIT(dc->ctx->logger);
3205
3206 BW_VAL_TRACE_COUNT();
3207
3208 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
3209
3210 if (pipe_cnt == 0)
3211 goto validate_out;
3212
3213 if (!out)
3214 goto validate_fail;
3215
3216 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3217
3218 if (fast_validate) {
3219 BW_VAL_TRACE_SKIP(fast);
3220 goto validate_out;
3221 }
3222
3223 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
3224 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3225
3226 BW_VAL_TRACE_END_WATERMARKS();
3227
3228 goto validate_out;
3229
3230validate_fail:
3231 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3232 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3233
3234 BW_VAL_TRACE_SKIP(fail);
3235 out = false;
3236
3237validate_out:
3238 kfree(pipes);
3239
3240 BW_VAL_TRACE_FINISH();
3241
3242 return out;
3243}
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3258 struct dc_state *context, bool fast_validate)
3259{
3260 bool voltage_supported = false;
3261 bool full_pstate_supported = false;
3262 bool dummy_pstate_supported = false;
3263 double p_state_latency_us;
3264
3265