/* Copyright 2015 Advanced Micro Devices, Inc. */
#include "dm_services.h"
#include "dc.h"
#include "dc_link_dp.h"
#include "dm_helpers.h"
#include "opp.h"
#include "dsc.h"
#include "resource.h"

#include "inc/core_types.h"
#include "link_hwss.h"
#include "dc_link_ddc.h"
#include "core_status.h"
#include "dpcd_defs.h"
#include "dc_dmub_srv.h"
#include "dce/dmub_hw_lock_mgr.h"
#include "inc/link_enc_cfg.h"

/*Travis*/
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT";
/*Nutmeg*/
static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA";

#define DC_LOGGER \
        link->ctx->logger
#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */

#include "link_dpcd.h"

        /* maximum pre emphasis level allowed for each voltage swing level*/
        static const enum dc_pre_emphasis
        voltage_swing_to_pre_emphasis[] = { PRE_EMPHASIS_LEVEL3,
                                            PRE_EMPHASIS_LEVEL2,
                                            PRE_EMPHASIS_LEVEL1,
                                            PRE_EMPHASIS_DISABLED };

enum {
        POST_LT_ADJ_REQ_LIMIT = 6,
        POST_LT_ADJ_REQ_TIMEOUT = 200
};

static bool decide_fallback_link_setting(
                struct dc_link_settings initial_link_settings,
                struct dc_link_settings *current_link_setting,
                enum link_training_result training_result);
static struct dc_link_settings get_common_supported_link_settings(
                struct dc_link_settings link_setting_a,
                struct dc_link_settings link_setting_b);

static uint32_t get_cr_training_aux_rd_interval(struct dc_link *link,
                const struct dc_link_settings *link_settings)
{
        union training_aux_rd_interval training_rd_interval;
        uint32_t wait_in_micro_secs = 100;

        memset(&training_rd_interval, 0, sizeof(training_rd_interval));
        core_link_read_dpcd(
                        link,
                        DP_TRAINING_AUX_RD_INTERVAL,
                        (uint8_t *)&training_rd_interval,
                        sizeof(training_rd_interval));
        if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
                wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
        return wait_in_micro_secs;
}

static uint32_t get_eq_training_aux_rd_interval(
        struct dc_link *link,
        const struct dc_link_settings *link_settings)
{
        union training_aux_rd_interval training_rd_interval;
        uint32_t wait_in_micro_secs = 400;

        memset(&training_rd_interval, 0, sizeof(training_rd_interval));
        /* overwrite the delay if rev > 1.1*/
        if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_12) {
                /* DP 1.2 or later - retrieve delay through
                 * "DPCD_ADDR_TRAINING_AUX_RD_INTERVAL" register */
                core_link_read_dpcd(
                        link,
                        DP_TRAINING_AUX_RD_INTERVAL,
                        (uint8_t *)&training_rd_interval,
                        sizeof(training_rd_interval));

                if (training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL)
                        wait_in_micro_secs = training_rd_interval.bits.TRAINIG_AUX_RD_INTERVAL * 4000;
        }

        return wait_in_micro_secs;
}

void dp_wait_for_training_aux_rd_interval(
        struct dc_link *link,
        uint32_t wait_in_micro_secs)
{
        udelay(wait_in_micro_secs);

        DC_LOG_HW_LINK_TRAINING("%s:\n wait = %d\n",
                __func__,
                wait_in_micro_secs);
}

enum dpcd_training_patterns
        dc_dp_training_pattern_to_dpcd_training_pattern(
        struct dc_link *link,
        enum dc_dp_training_pattern pattern)
{
        enum dpcd_training_patterns dpcd_tr_pattern =
        DPCD_TRAINING_PATTERN_VIDEOIDLE;

        switch (pattern) {
        case DP_TRAINING_PATTERN_SEQUENCE_1:
                dpcd_tr_pattern = DPCD_TRAINING_PATTERN_1;
                break;
        case DP_TRAINING_PATTERN_SEQUENCE_2:
                dpcd_tr_pattern = DPCD_TRAINING_PATTERN_2;
                break;
        case DP_TRAINING_PATTERN_SEQUENCE_3:
                dpcd_tr_pattern = DPCD_TRAINING_PATTERN_3;
                break;
        case DP_TRAINING_PATTERN_SEQUENCE_4:
                dpcd_tr_pattern = DPCD_TRAINING_PATTERN_4;
                break;
        case DP_TRAINING_PATTERN_VIDEOIDLE:
                dpcd_tr_pattern = DPCD_TRAINING_PATTERN_VIDEOIDLE;
                break;
        default:
                ASSERT(0);
                DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
                        __func__, pattern);
                break;
        }

        return dpcd_tr_pattern;
}

static void dpcd_set_training_pattern(
        struct dc_link *link,
        enum dc_dp_training_pattern training_pattern)
{
        union dpcd_training_pattern dpcd_pattern = { {0} };

        dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
                        dc_dp_training_pattern_to_dpcd_training_pattern(
                                        link, training_pattern);

        core_link_write_dpcd(
                link,
                DP_TRAINING_PATTERN_SET,
                &dpcd_pattern.raw,
                1);

        DC_LOG_HW_LINK_TRAINING("%s\n %x pattern = %x\n",
                __func__,
                DP_TRAINING_PATTERN_SET,
                dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
}

static enum dc_dp_training_pattern decide_cr_training_pattern(
                const struct dc_link_settings *link_settings)
{
        return DP_TRAINING_PATTERN_SEQUENCE_1;
}

static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,
                const struct dc_link_settings *link_settings)
{
        struct link_encoder *link_enc;
        enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;
        struct encoder_feature_support *features;
        struct dpcd_caps *dpcd_caps = &link->dpcd_caps;

        /* Access link encoder capability based on whether it is statically
         * or dynamically assigned to a link.
         */
        if (link->is_dig_mapping_flexible &&
                        link->dc->res_pool->funcs->link_encs_assign)
                link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
        else
                link_enc = link->link_enc;
        ASSERT(link_enc);
        features = &link_enc->features;

        if (features->flags.bits.IS_TPS3_CAPABLE)
                highest_tp = DP_TRAINING_PATTERN_SEQUENCE_3;

        if (features->flags.bits.IS_TPS4_CAPABLE)
                highest_tp = DP_TRAINING_PATTERN_SEQUENCE_4;

        if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
                highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_4)
                return DP_TRAINING_PATTERN_SEQUENCE_4;

        if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
                highest_tp >= DP_TRAINING_PATTERN_SEQUENCE_3)
                return DP_TRAINING_PATTERN_SEQUENCE_3;

        return DP_TRAINING_PATTERN_SEQUENCE_2;
}

enum dc_status dpcd_set_link_settings(
        struct dc_link *link,
        const struct link_training_settings *lt_settings)
{
        uint8_t rate;
        enum dc_status status;

        union down_spread_ctrl downspread = { {0} };
        union lane_count_set lane_count_set = { {0} };

        downspread.raw = (uint8_t)
        (lt_settings->link_settings.link_spread);

        lane_count_set.bits.LANE_COUNT_SET =
        lt_settings->link_settings.lane_count;

        lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
        lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;


        if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
                        lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {
                lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
                                link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
        }

        status = core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
                &downspread.raw, sizeof(downspread));

        status = core_link_write_dpcd(link, DP_LANE_COUNT_SET,
                &lane_count_set.raw, 1);

        if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
                        lt_settings->link_settings.use_link_rate_set == true) {
                rate = 0;
                /* WA for some MUX chips that will power down with eDP and lose supported
                 * link rate set for eDP 1.4. Source reads DPCD 0x010 again to ensure
                 * MUX chip gets link rate set back before link training.
                 */
                if (link->connector_signal == SIGNAL_TYPE_EDP) {
                        uint8_t supported_link_rates[16];

                        core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
                                        supported_link_rates, sizeof(supported_link_rates));
                }
                status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
                status = core_link_write_dpcd(link, DP_LINK_RATE_SET,
                                &lt_settings->link_settings.link_rate_set, 1);
        } else {
                rate = (uint8_t) (lt_settings->link_settings.link_rate);
                status = core_link_write_dpcd(link, DP_LINK_BW_SET, &rate, 1);
        }

        if (rate) {
                DC_LOG_HW_LINK_TRAINING("%s\n %x rate = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
                        __func__,
                        DP_LINK_BW_SET,
                        lt_settings->link_settings.link_rate,
                        DP_LANE_COUNT_SET,
                        lt_settings->link_settings.lane_count,
                        lt_settings->enhanced_framing,
                        DP_DOWNSPREAD_CTRL,
                        lt_settings->link_settings.link_spread);
        } else {
                DC_LOG_HW_LINK_TRAINING("%s\n %x rate set = %x\n %x lane = %x framing = %x\n %x spread = %x\n",
                        __func__,
                        DP_LINK_RATE_SET,
                        lt_settings->link_settings.link_rate_set,
                        DP_LANE_COUNT_SET,
                        lt_settings->link_settings.lane_count,
                        lt_settings->enhanced_framing,
                        DP_DOWNSPREAD_CTRL,
                        lt_settings->link_settings.link_spread);
        }

        return status;
}

uint8_t dc_dp_initialize_scrambling_data_symbols(
        struct dc_link *link,
        enum dc_dp_training_pattern pattern)
{
        uint8_t disable_scrabled_data_symbols = 0;

        switch (pattern) {
        case DP_TRAINING_PATTERN_SEQUENCE_1:
        case DP_TRAINING_PATTERN_SEQUENCE_2:
        case DP_TRAINING_PATTERN_SEQUENCE_3:
                disable_scrabled_data_symbols = 1;
                break;
        case DP_TRAINING_PATTERN_SEQUENCE_4:
                disable_scrabled_data_symbols = 0;
                break;
        default:
                ASSERT(0);
                DC_LOG_HW_LINK_TRAINING("%s: Invalid HW Training pattern: %d\n",
                        __func__, pattern);
                break;
        }
        return disable_scrabled_data_symbols;
}

static inline bool is_repeater(struct dc_link *link, uint32_t offset)
{
        return (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && (offset != 0);
}

static void dpcd_set_lt_pattern_and_lane_settings(
        struct dc_link *link,
        const struct link_training_settings *lt_settings,
        enum dc_dp_training_pattern pattern,
        uint32_t offset)
{
        union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = { { {0} } };

        uint32_t dpcd_base_lt_offset;

        uint8_t dpcd_lt_buffer[5] = {0};
        union dpcd_training_pattern dpcd_pattern = { {0} };
        uint32_t lane;
        uint32_t size_in_bytes;
        bool edp_workaround = false; /* TODO link_prop.INTERNAL */
        dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET;

        if (is_repeater(link, offset))
                dpcd_base_lt_offset = DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
                        ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));

        /*****************************************************************
        * DpcdAddress_TrainingPatternSet
        *****************************************************************/
        dpcd_pattern.v1_4.TRAINING_PATTERN_SET =
                dc_dp_training_pattern_to_dpcd_training_pattern(link, pattern);

        dpcd_pattern.v1_4.SCRAMBLING_DISABLE =
                dc_dp_initialize_scrambling_data_symbols(link, pattern);

        dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET]
                = dpcd_pattern.raw;

        if (is_repeater(link, offset)) {
                DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n",
                        __func__,
                        offset,
                        dpcd_base_lt_offset,
                        dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
        } else {
                DC_LOG_HW_LINK_TRAINING("%s\n 0x%X pattern = %x\n",
                        __func__,
                        dpcd_base_lt_offset,
                        dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
        }
        /*****************************************************************
        * DpcdAddress_Lane0Set -> DpcdAddress_Lane3Set
        *****************************************************************/
        for (lane = 0; lane <
                (uint32_t)(lt_settings->link_settings.lane_count); lane++) {

                dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
                (uint8_t)(lt_settings->lane_settings[lane].VOLTAGE_SWING);
                dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
                (uint8_t)(lt_settings->lane_settings[lane].PRE_EMPHASIS);

                dpcd_lane[lane].bits.MAX_SWING_REACHED =
                (lt_settings->lane_settings[lane].VOLTAGE_SWING ==
                VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
                dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
                (lt_settings->lane_settings[lane].PRE_EMPHASIS ==
                PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
        }

        /* concatenate everything into one buffer*/

        size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]);

         // 0x00103 - 0x00102
        memmove(
                &dpcd_lt_buffer[DP_TRAINING_LANE0_SET - DP_TRAINING_PATTERN_SET],
                dpcd_lane,
                size_in_bytes);

        if (is_repeater(link, offset)) {
                DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
                                " 0x%X VS set = %x PE set = %x max VS Reached = %x  max PE Reached = %x\n",
                        __func__,
                        offset,
                        dpcd_base_lt_offset,
                        dpcd_lane[0].bits.VOLTAGE_SWING_SET,
                        dpcd_lane[0].bits.PRE_EMPHASIS_SET,
                        dpcd_lane[0].bits.MAX_SWING_REACHED,
                        dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
        } else {
                DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
                        __func__,
                        dpcd_base_lt_offset,
                        dpcd_lane[0].bits.VOLTAGE_SWING_SET,
                        dpcd_lane[0].bits.PRE_EMPHASIS_SET,
                        dpcd_lane[0].bits.MAX_SWING_REACHED,
                        dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
        }
        if (edp_workaround) {
                /* for eDP write in 2 parts because the 5-byte burst is
                * causing issues on some eDP panels (EPR#366724)
                */
                core_link_write_dpcd(
                        link,
                        DP_TRAINING_PATTERN_SET,
                        &dpcd_pattern.raw,
                        sizeof(dpcd_pattern.raw));

                core_link_write_dpcd(
                        link,
                        DP_TRAINING_LANE0_SET,
                        (uint8_t *)(dpcd_lane),
                        size_in_bytes);

                } else
                /* write it all in (1 + number-of-lanes)-byte burst*/
                        core_link_write_dpcd(
                                link,
                                dpcd_base_lt_offset,
                                dpcd_lt_buffer,
                                size_in_bytes + sizeof(dpcd_pattern.raw));

        link->cur_lane_setting = lt_settings->lane_settings[0];
}

bool dp_is_cr_done(enum dc_lane_count ln_count,
        union lane_status *dpcd_lane_status)
{
        uint32_t lane;
        /*LANEx_CR_DONE bits All 1's?*/
        for (lane = 0; lane < (uint32_t)(ln_count); lane++) {
                if (!dpcd_lane_status[lane].bits.CR_DONE_0)
                        return false;
        }
        return true;
}

bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
                union lane_status *dpcd_lane_status)
{
        bool done = true;
        uint32_t lane;
        for (lane = 0; lane < (uint32_t)(ln_count); lane++)
                if (!dpcd_lane_status[lane].bits.CHANNEL_EQ_DONE_0)
                        done = false;
        return done;
}

bool dp_is_symbol_locked(enum dc_lane_count ln_count,
                union lane_status *dpcd_lane_status)
{
        bool locked = true;
        uint32_t lane;
        for (lane = 0; lane < (uint32_t)(ln_count); lane++)
                if (!dpcd_lane_status[lane].bits.SYMBOL_LOCKED_0)
                        locked = false;
        return locked;
}

bool dp_is_interlane_aligned(union lane_align_status_updated align_status)
{
        return align_status.bits.INTERLANE_ALIGN_DONE == 1;
}

void dp_update_drive_settings(
                struct link_training_settings *dest,
                struct link_training_settings src)
{
        uint32_t lane;
        for (lane = 0; lane < src.link_settings.lane_count; lane++) {
                if (dest->voltage_swing == NULL)
                        dest->lane_settings[lane].VOLTAGE_SWING = src.lane_settings[lane].VOLTAGE_SWING;
                else
                        dest->lane_settings[lane].VOLTAGE_SWING = *dest->voltage_swing;

                if (dest->pre_emphasis == NULL)
                        dest->lane_settings[lane].PRE_EMPHASIS = src.lane_settings[lane].PRE_EMPHASIS;
                else
                        dest->lane_settings[lane].PRE_EMPHASIS = *dest->pre_emphasis;

                if (dest->post_cursor2 == NULL)
                        dest->lane_settings[lane].POST_CURSOR2 = src.lane_settings[lane].POST_CURSOR2;
                else
                        dest->lane_settings[lane].POST_CURSOR2 = *dest->post_cursor2;
        }
}

static uint8_t get_nibble_at_index(const uint8_t *buf,
        uint32_t index)
{
        uint8_t nibble;
        nibble = buf[index / 2];

        if (index % 2)
                nibble >>= 4;
        else
                nibble &= 0x0F;

        return nibble;
}

static enum dc_pre_emphasis get_max_pre_emphasis_for_voltage_swing(
        enum dc_voltage_swing voltage)
{
        enum dc_pre_emphasis pre_emphasis;
        pre_emphasis = PRE_EMPHASIS_MAX_LEVEL;

        if (voltage <= VOLTAGE_SWING_MAX_LEVEL)
                pre_emphasis = voltage_swing_to_pre_emphasis[voltage];

        return pre_emphasis;

}

static void find_max_drive_settings(
        const struct link_training_settings *link_training_setting,
        struct link_training_settings *max_lt_setting)
{
        uint32_t lane;
        struct dc_lane_settings max_requested;

        max_requested.VOLTAGE_SWING =
                link_training_setting->
                lane_settings[0].VOLTAGE_SWING;
        max_requested.PRE_EMPHASIS =
                link_training_setting->
                lane_settings[0].PRE_EMPHASIS;
        /*max_requested.postCursor2 =
         * link_training_setting->laneSettings[0].postCursor2;*/

        /* Determine what the maximum of the requested settings are*/
        for (lane = 1; lane < link_training_setting->link_settings.lane_count;
                        lane++) {
                if (link_training_setting->lane_settings[lane].VOLTAGE_SWING >
                        max_requested.VOLTAGE_SWING)

                        max_requested.VOLTAGE_SWING =
                        link_training_setting->
                        lane_settings[lane].VOLTAGE_SWING;

                if (link_training_setting->lane_settings[lane].PRE_EMPHASIS >
                                max_requested.PRE_EMPHASIS)
                        max_requested.PRE_EMPHASIS =
                        link_training_setting->
                        lane_settings[lane].PRE_EMPHASIS;

                /*
                if (link_training_setting->laneSettings[lane].postCursor2 >
                 max_requested.postCursor2)
                {
                max_requested.postCursor2 =
                link_training_setting->laneSettings[lane].postCursor2;
                }
                */
        }

        /* make sure the requested settings are
         * not higher than maximum settings*/
        if (max_requested.VOLTAGE_SWING > VOLTAGE_SWING_MAX_LEVEL)
                max_requested.VOLTAGE_SWING = VOLTAGE_SWING_MAX_LEVEL;

        if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
                max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
        /*
        if (max_requested.postCursor2 > PostCursor2_MaxLevel)
        max_requested.postCursor2 = PostCursor2_MaxLevel;
        */

        /* make sure the pre-emphasis matches the voltage swing*/
        if (max_requested.PRE_EMPHASIS >
                get_max_pre_emphasis_for_voltage_swing(
                        max_requested.VOLTAGE_SWING))
                max_requested.PRE_EMPHASIS =
                get_max_pre_emphasis_for_voltage_swing(
                        max_requested.VOLTAGE_SWING);

        /*
         * Post Cursor2 levels are completely independent from
         * pre-emphasis (Post Cursor1) levels. But Post Cursor2 levels
         * can only be applied to each allowable combination of voltage
         * swing and pre-emphasis levels */
         /* if ( max_requested.postCursor2 >
          *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing))
          *  max_requested.postCursor2 =
          *  getMaxPostCursor2ForVoltageSwing(max_requested.voltageSwing);
          */

        max_lt_setting->link_settings.link_rate =
                link_training_setting->link_settings.link_rate;
        max_lt_setting->link_settings.lane_count =
        link_training_setting->link_settings.lane_count;
        max_lt_setting->link_settings.link_spread =
                link_training_setting->link_settings.link_spread;

        for (lane = 0; lane <
                link_training_setting->link_settings.lane_count;
                lane++) {
                max_lt_setting->lane_settings[lane].VOLTAGE_SWING =
                        max_requested.VOLTAGE_SWING;
                max_lt_setting->lane_settings[lane].PRE_EMPHASIS =
                        max_requested.PRE_EMPHASIS;
                /*max_lt_setting->laneSettings[lane].postCursor2 =
                 * max_requested.postCursor2;
                 */
        }

}

enum dc_status dp_get_lane_status_and_drive_settings(
        struct dc_link *link,
        const struct link_training_settings *link_training_setting,
        union lane_status *ln_status,
        union lane_align_status_updated *ln_status_updated,
        struct link_training_settings *req_settings,
        uint32_t offset)
{
        unsigned int lane01_status_address = DP_LANE0_1_STATUS;
        uint8_t lane_adjust_offset = 4;
        unsigned int lane01_adjust_address;
        uint8_t dpcd_buf[6] = {0};
        union lane_adjust dpcd_lane_adjust[LANE_COUNT_DP_MAX] = { { {0} } };
        struct link_training_settings request_settings = { {0} };
        uint32_t lane;
        enum dc_status status;

        memset(req_settings, '\0', sizeof(struct link_training_settings));

        if (is_repeater(link, offset)) {
                lane01_status_address =
                                DP_LANE0_1_STATUS_PHY_REPEATER1 +
                                ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
                lane_adjust_offset = 3;
        }

        status = core_link_read_dpcd(
                link,
                lane01_status_address,
                (uint8_t *)(dpcd_buf),
                sizeof(dpcd_buf));

        for (lane = 0; lane <
                (uint32_t)(link_training_setting->link_settings.lane_count);
                lane++) {

                ln_status[lane].raw =
                        get_nibble_at_index(&dpcd_buf[0], lane);
                dpcd_lane_adjust[lane].raw =
                        get_nibble_at_index(&dpcd_buf[lane_adjust_offset], lane);
        }

        ln_status_updated->raw = dpcd_buf[2];

        if (is_repeater(link, offset)) {
                DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
                                " 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
                        __func__,
                        offset,
                        lane01_status_address, dpcd_buf[0],
                        lane01_status_address + 1, dpcd_buf[1]);
        } else {
                DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01Status = %x\n 0x%X Lane23Status = %x\n ",
                        __func__,
                        lane01_status_address, dpcd_buf[0],
                        lane01_status_address + 1, dpcd_buf[1]);
        }
        lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;

        if (is_repeater(link, offset))
                lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 +
                                ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));

        if (is_repeater(link, offset)) {
                DC_LOG_HW_LINK_TRAINING("%s:\n LTTPR Repeater ID: %d\n"
                                " 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
                                        __func__,
                                        offset,
                                        lane01_adjust_address,
                                        dpcd_buf[lane_adjust_offset],
                                        lane01_adjust_address + 1,
                                        dpcd_buf[lane_adjust_offset + 1]);
        } else {
                DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X Lane01AdjustRequest = %x\n 0x%X Lane23AdjustRequest = %x\n",
                        __func__,
                        lane01_adjust_address,
                        dpcd_buf[lane_adjust_offset],
                        lane01_adjust_address + 1,
                        dpcd_buf[lane_adjust_offset + 1]);
        }

        /*copy to req_settings*/
        request_settings.link_settings.lane_count =
                link_training_setting->link_settings.lane_count;
        request_settings.link_settings.link_rate =
                link_training_setting->link_settings.link_rate;
        request_settings.link_settings.link_spread =
                link_training_setting->link_settings.link_spread;

        for (lane = 0; lane <
                (uint32_t)(link_training_setting->link_settings.lane_count);
                lane++) {

                request_settings.lane_settings[lane].VOLTAGE_SWING =
                        (enum dc_voltage_swing)(dpcd_lane_adjust[lane].bits.
                                VOLTAGE_SWING_LANE);
                request_settings.lane_settings[lane].PRE_EMPHASIS =
                        (enum dc_pre_emphasis)(dpcd_lane_adjust[lane].bits.
                                PRE_EMPHASIS_LANE);
        }

        /*Note: for postcursor2, read adjusted
         * postcursor2 settings from*/
        /*DpcdAddress_AdjustRequestPostCursor2 =
         *0x020C (not implemented yet)*/

        /* we find the maximum of the requested settings across all lanes*/
        /* and set this maximum for all lanes*/
        find_max_drive_settings(&request_settings, req_settings);

        /* if post cursor 2 is needed in the future,
         * read DpcdAddress_AdjustRequestPostCursor2 = 0x020C
         */

        return status;
}

enum dc_status dpcd_set_lane_settings(
        struct dc_link *link,
        const struct link_training_settings *link_training_setting,
        uint32_t offset)
{
        union dpcd_training_lane dpcd_lane[LANE_COUNT_DP_MAX] = {{{0}}};
        uint32_t lane;
        unsigned int lane0_set_address;
        enum dc_status status;

        lane0_set_address = DP_TRAINING_LANE0_SET;

        if (is_repeater(link, offset))
                lane0_set_address = DP_TRAINING_LANE0_SET_PHY_REPEATER1 +
                ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));

        for (lane = 0; lane <
                (uint32_t)(link_training_setting->
                link_settings.lane_count);
                lane++) {
                dpcd_lane[lane].bits.VOLTAGE_SWING_SET =
                        (uint8_t)(link_training_setting->
                        lane_settings[lane].VOLTAGE_SWING);
                dpcd_lane[lane].bits.PRE_EMPHASIS_SET =
                        (uint8_t)(link_training_setting->
                        lane_settings[lane].PRE_EMPHASIS);
                dpcd_lane[lane].bits.MAX_SWING_REACHED =
                        (link_training_setting->
                        lane_settings[lane].VOLTAGE_SWING ==
                        VOLTAGE_SWING_MAX_LEVEL ? 1 : 0);
                dpcd_lane[lane].bits.MAX_PRE_EMPHASIS_REACHED =
                        (link_training_setting->
                        lane_settings[lane].PRE_EMPHASIS ==
                        PRE_EMPHASIS_MAX_LEVEL ? 1 : 0);
        }

        status = core_link_write_dpcd(link,
                lane0_set_address,
                (uint8_t *)(dpcd_lane),
                link_training_setting->link_settings.lane_count);

        /*
        if (LTSettings.link.rate == LinkRate_High2)
        {
                DpcdTrainingLaneSet2 dpcd_lane2[lane_count_DPMax] = {0};
                for ( uint32_t lane = 0;
                lane < lane_count_DPMax; lane++)
                {
                        dpcd_lane2[lane].bits.post_cursor2_set =
                        static_cast<unsigned char>(
                        LTSettings.laneSettings[lane].postCursor2);
                        dpcd_lane2[lane].bits.max_post_cursor2_reached = 0;
                }
                m_pDpcdAccessSrv->WriteDpcdData(
                DpcdAddress_Lane0Set2,
                reinterpret_cast<unsigned char*>(dpcd_lane2),
                LTSettings.link.lanes);
        }
        */

        if (is_repeater(link, offset)) {
                DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n"
                                " 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
                        __func__,
                        offset,
                        lane0_set_address,
                        dpcd_lane[0].bits.VOLTAGE_SWING_SET,
                        dpcd_lane[0].bits.PRE_EMPHASIS_SET,
                        dpcd_lane[0].bits.MAX_SWING_REACHED,
                        dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);

        } else {
                DC_LOG_HW_LINK_TRAINING("%s\n 0x%X VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
                        __func__,
                        lane0_set_address,
                        dpcd_lane[0].bits.VOLTAGE_SWING_SET,
                        dpcd_lane[0].bits.PRE_EMPHASIS_SET,
                        dpcd_lane[0].bits.MAX_SWING_REACHED,
                        dpcd_lane[0].bits.MAX_PRE_EMPHASIS_REACHED);
        }
        link->cur_lane_setting = link_training_setting->lane_settings[0];

        return status;
}

bool dp_is_max_vs_reached(
        const struct link_training_settings *lt_settings)
{
        uint32_t lane;
        for (lane = 0; lane <
                (uint32_t)(lt_settings->link_settings.lane_count);
                lane++) {
                if (lt_settings->lane_settings[lane].VOLTAGE_SWING
                        == VOLTAGE_SWING_MAX_LEVEL)
                        return true;
        }
        return false;

}

static bool perform_post_lt_adj_req_sequence(
        struct dc_link *link,
        struct link_training_settings *lt_settings)
{
        enum dc_lane_count lane_count =
        lt_settings->link_settings.lane_count;

        uint32_t adj_req_count;
        uint32_t adj_req_timer;
        bool req_drv_setting_changed;
        uint32_t lane;

        req_drv_setting_changed = false;
        for (adj_req_count = 0; adj_req_count < POST_LT_ADJ_REQ_LIMIT;
        adj_req_count++) {

                req_drv_setting_changed = false;

                for (adj_req_timer = 0;
                        adj_req_timer < POST_LT_ADJ_REQ_TIMEOUT;
                        adj_req_timer++) {

                        struct link_training_settings req_settings;
                        union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
                        union lane_align_status_updated
                                dpcd_lane_status_updated;

                        dp_get_lane_status_and_drive_settings(
                                link,
                                lt_settings,
                                dpcd_lane_status,
                                &dpcd_lane_status_updated,
                                &req_settings,
                                DPRX);

                        if (dpcd_lane_status_updated.bits.
                                        POST_LT_ADJ_REQ_IN_PROGRESS == 0)
                                return true;

                        if (!dp_is_cr_done(lane_count, dpcd_lane_status))
                                return false;

                        if (!dp_is_ch_eq_done(lane_count, dpcd_lane_status) ||
                                        !dp_is_symbol_locked(lane_count, dpcd_lane_status) ||
                                        !dp_is_interlane_aligned(dpcd_lane_status_updated))
                                return false;

                        for (lane = 0; lane < (uint32_t)(lane_count); lane++) {

                                if (lt_settings->
                                lane_settings[lane].VOLTAGE_SWING !=
                                req_settings.lane_settings[lane].
                                VOLTAGE_SWING ||
                                lt_settings->lane_settings[lane].PRE_EMPHASIS !=
                                req_settings.lane_settings[lane].PRE_EMPHASIS) {

                                        req_drv_setting_changed = true;
                                        break;
                                }
                        }

                        if (req_drv_setting_changed) {
                                dp_update_drive_settings(
                                        lt_settings, req_settings);

                                dc_link_dp_set_drive_settings(link,
                                                lt_settings);
                                break;
                        }

                        msleep(1);
                }

                if (!req_drv_setting_changed) {
                        DC_LOG_WARNING("%s: Post Link Training Adjust Request Timed out\n",
                                __func__);

                        ASSERT(0);
                        return true;
                }
        }
        DC_LOG_WARNING("%s: Post Link Training Adjust Request limit reached\n",
                __func__);

        ASSERT(0);
        return true;

}

/* Only used for channel equalization */
uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval)
{
        unsigned int aux_rd_interval_us = 400;

        switch (dpcd_aux_read_interval) {
        case 0x01:
                aux_rd_interval_us = 4000;
                break;
        case 0x02:
                aux_rd_interval_us = 8000;
                break;
        case 0x03:
                aux_rd_interval_us = 12000;
                break;
        case 0x04:
                aux_rd_interval_us = 16000;
                break;
        default:
                break;
        }

        return aux_rd_interval_us;
}

enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
                                        union lane_status *dpcd_lane_status)
{
        enum link_training_result result = LINK_TRAINING_SUCCESS;

        if (ln_count >= LANE_COUNT_ONE && !dpcd_lane_status[0].bits.CR_DONE_0)
                result = LINK_TRAINING_CR_FAIL_LANE0;
        else if (ln_count >= LANE_COUNT_TWO && !dpcd_lane_status[1].bits.CR_DONE_0)
                result = LINK_TRAINING_CR_FAIL_LANE1;
        else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[2].bits.CR_DONE_0)
                result = LINK_TRAINING_CR_FAIL_LANE23;
        else if (ln_count >= LANE_COUNT_FOUR && !dpcd_lane_status[3].bits.CR_DONE_0)
                result = LINK_TRAINING_CR_FAIL_LANE23;
        return result;
}

static enum link_training_result perform_channel_equalization_sequence(
        struct dc_link *link,
        struct link_training_settings *lt_settings,
        uint32_t offset)
{
        struct link_training_settings req_settings;
        enum dc_dp_training_pattern tr_pattern;
        uint32_t retries_ch_eq;
        uint32_t wait_time_microsec;
        enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
        union lane_align_status_updated dpcd_lane_status_updated = { {0} };
        union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX] = { { {0} } };

        /* Note: also check that TPS4 is a supported feature*/

        tr_pattern = lt_settings->pattern_for_eq;

        if (is_repeater(link, offset))
                tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_4;

        dp_set_hw_training_pattern(link, tr_pattern, offset);

        for (retries_ch_eq = 0; retries_ch_eq <= LINK_TRAINING_MAX_RETRY_COUNT;
                retries_ch_eq++) {

                dp_set_hw_lane_settings(link, lt_settings, offset);

                /* 2. update DPCD*/
                if (!retries_ch_eq)
                        /* EPR #361076 - write as a 5-byte burst,
                         * but only for the 1-st iteration
                         */

                        dpcd_set_lt_pattern_and_lane_settings(
                                link,
                                lt_settings,
                                tr_pattern, offset);
                else
                        dpcd_set_lane_settings(link, lt_settings, offset);

                /* 3. wait for receiver to lock-on*/
                wait_time_microsec = lt_settings->eq_pattern_time;

                if (is_repeater(link, offset))
                        wait_time_microsec =
                                        dp_translate_training_aux_read_interval(
                                                link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]);

                dp_wait_for_training_aux_rd_interval(
                                link,
                                wait_time_microsec);

                /* 4. Read lane status and requested
                 * drive settings as set by the sink*/

                dp_get_lane_status_and_drive_settings(
                        link,
                        lt_settings,
                        dpcd_lane_status,
                        &dpcd_lane_status_updated,
                        &req_settings,
                        offset);

                /* 5. check CR done*/
                if (!dp_is_cr_done(lane_count, dpcd_lane_status))
                        return LINK_TRAINING_EQ_FAIL_CR;

                /* 6. check CHEQ done*/
                if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
                                dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
                                dp_is_interlane_aligned(dpcd_lane_status_updated))
                        return LINK_TRAINING_SUCCESS;

                /* 7. update VS/PE/PC2 in lt_settings*/
                dp_update_drive_settings(lt_settings, req_settings);
        }

        return LINK_TRAINING_EQ_FAIL_EQ;

}

static void start_clock_recovery_pattern_early(struct dc_link *link,
                struct link_training_settings *lt_settings,
                uint32_t offset)
{
        DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",
                        __func__);
        dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);
        dp_set_hw_lane_settings(link, lt_settings, offset);
        udelay(400);
}

static enum link_training_result perform_clock_recovery_sequence(
        struct dc_link *link,
        struct link_training_settings *lt_settings,
        uint32_t offset)
{
        uint32_t retries_cr;
        uint32_t retry_count;
        uint32_t wait_time_microsec;
        struct link_training_settings req_settings;
        enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;
        union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];
        union lane_align_status_updated dpcd_lane_status_updated;

        retries_cr = 0;
        retry_count = 0;

        if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
                dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);

        /* najeeb - The synaptics MST hub can put the LT in
        * infinite loop by switching the VS
        */
        /* between level 0 and level 1 continuously, here
        * we try for CR lock for LinkTrainingMaxCRRetry count*/
        while ((retries_cr < LINK_TRAINING_MAX_RETRY_COUNT) &&
                (retry_count < LINK_TRAINING_MAX_CR_RETRY)) {

                memset(&dpcd_lane_status, '\0', sizeof(dpcd_lane_status));
                memset(&dpcd_lane_status_updated, '\0',
                sizeof(dpcd_lane_status_updated));

                /* 1. call HWSS to set lane settings*/
                dp_set_hw_lane_settings(
                                link,
                                lt_settings,
                                offset);

                /* 2. update DPCD of the receiver*/
                if (!retry_count)
                        /* EPR #361076 - write as a 5-byte burst,
                         * but only for the 1-st iteration.*/
                        dpcd_set_lt_pattern_and_lane_settings(
                                        link,
                                        lt_settings,
                                        lt_settings->pattern_for_cr,
                                        offset);
                else
                        dpcd_set_lane_settings(
                                        link,
                                        lt_settings,
                                        offset);

                /* 3. wait receiver to lock-on*/
                wait_time_microsec = lt_settings->cr_pattern_time;

                if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
                        wait_time_microsec = TRAINING_AUX_RD_INTERVAL;

                dp_wait_for_training_aux_rd_interval(
                                link,
                                wait_time_microsec);

                /* 4. Read lane status and requested drive
                * settings as set by the sink
                */
                dp_get_lane_status_and_drive_settings(
                                link,
                                lt_settings,
                                dpcd_lane_status,
                                &dpcd_lane_status_updated,
                                &req_settings,
                                offset);

                /* 5. check CR done*/
                if (dp_is_cr_done(lane_count, dpcd_lane_status))
                        return LINK_TRAINING_SUCCESS;

                /* 6. max VS reached*/
                if (dp_is_max_vs_reached(lt_settings))
                        break;

                /* 7. same lane settings*/
                /* Note: settings are the same for all lanes,
                 * so comparing first lane is sufficient*/
                if ((lt_settings->lane_settings[0].VOLTAGE_SWING ==
                        req_settings.lane_settings[0].VOLTAGE_SWING)
                        && (lt_settings->lane_settings[0].PRE_EMPHASIS ==
                                req_settings.lane_settings[0].PRE_EMPHASIS))
                        retries_cr++;
                else
                        retries_cr = 0;

                /* 8. update VS/PE/PC2 in lt_settings*/
                dp_update_drive_settings(lt_settings, req_settings);

                retry_count++;
        }

        if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
                ASSERT(0);
                DC_LOG_ERROR("%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",
                        __func__,
                        LINK_TRAINING_MAX_CR_RETRY);

        }

        return dp_get_cr_failure(lane_count, dpcd_lane_status);
}

static inline enum link_training_result dp_transition_to_video_idle(
        struct dc_link *link,
        struct link_training_settings *lt_settings,
        enum link_training_result status)
{
        union lane_count_set lane_count_set = { {0} };

        /* 4. mainlink output idle pattern*/
        dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);

        /*
         * 5. post training adjust if required
         * If the upstream DPTX and downstream DPRX both support TPS4,
         * TPS4 must be used instead of POST_LT_ADJ_REQ.
         */
        if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||
                        lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4) {
                /* delay 5ms after Main Link output idle pattern and then check
                 * DPCD 0202h.
                 */
                if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) {
                        msleep(5);
                        status = dp_check_link_loss_status(link, lt_settings);
                }
                return status;
        }

        if (status == LINK_TRAINING_SUCCESS &&
                perform_post_lt_adj_req_sequence(link, lt_settings) == false)
                status = LINK_TRAINING_LQA_FAIL;

        lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
        lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;
        lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;

        core_link_write_dpcd(
                link,
                DP_LANE_COUNT_SET,
                &lane_count_set.raw,
                sizeof(lane_count_set));

        return status;
}

enum link_training_result dp_check_link_loss_status(
        struct dc_link *link,
        const struct link_training_settings *link_training_setting)
{
        enum link_training_result status = LINK_TRAINING_SUCCESS;
        union lane_status lane_status;
        uint8_t dpcd_buf[6] = {0};
        uint32_t lane;

        core_link_read_dpcd(
                        link,
                        DP_SINK_COUNT,
                        (uint8_t *)(dpcd_buf),
                        sizeof(dpcd_buf));

        /*parse lane status*/
        for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
                /*
                 * check lanes status
                 */
                lane_status.raw = get_nibble_at_index(&dpcd_buf[2], lane);

                if (!lane_status.bits.CHANNEL_EQ_DONE_0 ||
                        !lane_status.bits.CR_DONE_0 ||
                        !lane_status.bits.SYMBOL_LOCKED_0) {
                        /* if one of the channel equalization, clock
                         * recovery or symbol lock is dropped
                         * consider it as (link has been
                         * dropped) dp sink status has changed
                         */
                        status = LINK_TRAINING_LINK_LOSS;
                        break;
                }
        }

        return status;
}

static inline void decide_8b_10b_training_settings(
         struct dc_link *link,
        const struct dc_link_settings *link_setting,
        const struct dc_link_training_overrides *overrides,
        struct link_training_settings *lt_settings)
{
        uint32_t lane;

        memset(lt_settings, '\0', sizeof(struct link_training_settings));

        /* Initialize link settings */
        lt_settings->link_settings.use_link_rate_set = link_setting->use_link_rate_set;
        lt_settings->link_settings.link_rate_set = link_setting->link_rate_set;

        if (link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
                lt_settings->link_settings.link_rate = link->preferred_link_setting.link_rate;
        else
                lt_settings->link_settings.link_rate = link_setting->link_rate;

        if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN)
                lt_settings->link_settings.lane_count = link->preferred_link_setting.lane_count;
        else
                lt_settings->link_settings.lane_count = link_setting->lane_count;

        /*@todo[vdevulap] move SS to LS, should not be handled by displaypath*/

        /* TODO hard coded to SS for now
         * lt_settings.link_settings.link_spread =
         * dal_display_path_is_ss_supported(
         * path_mode->display_path) ?
         * LINK_SPREAD_05_DOWNSPREAD_30KHZ :
         * LINK_SPREAD_DISABLED;
         */
        /* Initialize link spread */
        if (link->dp_ss_off)
                lt_settings->link_settings.link_spread = LINK_SPREAD_DISABLED;
        else if (overrides->downspread != NULL)
                lt_settings->link_settings.link_spread
                        = *overrides->downspread
                        ? LINK_SPREAD_05_DOWNSPREAD_30KHZ
                        : LINK_SPREAD_DISABLED;
        else
                lt_settings->link_settings.link_spread = LINK_SPREAD_05_DOWNSPREAD_30KHZ;

        lt_settings->lttpr_mode = link->lttpr_mode;

        /* Initialize lane settings overrides */
        if (overrides->voltage_swing != NULL)
                lt_settings->voltage_swing = overrides->voltage_swing;

        if (overrides->pre_emphasis != NULL)
                lt_settings->pre_emphasis = overrides->pre_emphasis;

        if (overrides->post_cursor2 != NULL)
                lt_settings->post_cursor2 = overrides->post_cursor2;

        /* Initialize lane settings (VS/PE/PC2) */
        for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) {
                lt_settings->lane_settings[lane].VOLTAGE_SWING =
                        lt_settings->voltage_swing != NULL ?
                        *lt_settings->voltage_swing :
                        VOLTAGE_SWING_LEVEL0;
                lt_settings->lane_settings[lane].PRE_EMPHASIS =
                        lt_settings->pre_emphasis != NULL ?
                        *lt_settings->pre_emphasis
                        : PRE_EMPHASIS_DISABLED;
                lt_settings->lane_settings[lane].POST_CURSOR2 =
                        lt_settings->post_cursor2 != NULL ?
                        *lt_settings->post_cursor2
                        : POST_CURSOR2_DISABLED;
        }

        /* Initialize training timings */
        if (overrides->cr_pattern_time != NULL)
                lt_settings->cr_pattern_time = *overrides->cr_pattern_time;
        else
                lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting);

        if (overrides->eq_pattern_time != NULL)
                lt_settings->eq_pattern_time = *overrides->eq_pattern_time;
        else
                lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);

        if (overrides->pattern_for_cr != NULL)
                lt_settings->pattern_for_cr = *overrides->pattern_for_cr;
        else
                lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
        if (overrides->pattern_for_eq != NULL)
                lt_settings->pattern_for_eq = *overrides->pattern_for_eq;
        else
                lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);

        if (overrides->enhanced_framing != NULL)
                lt_settings->enhanced_framing = *overrides->enhanced_framing;
        else
                lt_settings->enhanced_framing = 1;

        if (link->preferred_training_settings.fec_enable != NULL)
                lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable;
        else
                lt_settings->should_set_fec_ready = true;
}

void dp_decide_training_settings(
                struct dc_link *link,
                const struct dc_link_settings *link_settings,
                const struct dc_link_training_overrides *overrides,
                struct link_training_settings *lt_settings)
{
        if (dp_get_link_encoding_format(link_settings) == DP_8b_10b_ENCODING)
                decide_8b_10b_training_settings(link, link_settings, overrides, lt_settings);
}


uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count)
{
        switch (lttpr_repeater_count) {
        case 0x80: // 1 lttpr repeater
                return 1;
        case 0x40: // 2 lttpr repeaters
                return 2;
        case 0x20: // 3 lttpr repeaters
                return 3;
        case 0x10: // 4 lttpr repeaters
                return 4;
        case 0x08: // 5 lttpr repeaters
                return 5;
        case 0x04: // 6 lttpr repeaters
                return 6;
        case 0x02: // 7 lttpr repeaters
                return 7;
        case 0x01: // 8 lttpr repeaters
                return 8;
        default:
                break;
        }
        return 0; // invalid value
}

enum dc_status configure_lttpr_mode_transparent(struct dc_link *link)
{
        uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;

        DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
        return core_link_write_dpcd(link,
                        DP_PHY_REPEATER_MODE,
                        (uint8_t *)&repeater_mode,
                        sizeof(repeater_mode));
}

enum dc_status configure_lttpr_mode_non_transparent(
                struct dc_link *link,
                const struct link_training_settings *lt_settings)
{
        /* aux timeout is already set to extended */
        /* RESET/SET lttpr mode to enable non transparent mode */
        uint8_t repeater_cnt;
        uint32_t aux_interval_address;
        uint8_t repeater_id;
        enum dc_status result = DC_ERROR_UNEXPECTED;
        uint8_t repeater_mode = DP_PHY_REPEATER_MODE_TRANSPARENT;

        enum dp_link_encoding encoding = dp_get_link_encoding_format(&lt_settings->link_settings);

        if (encoding == DP_8b_10b_ENCODING) {
                DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Transparent Mode\n", __func__);
                result = core_link_write_dpcd(link,
                                DP_PHY_REPEATER_MODE,
                                (uint8_t *)&repeater_mode,
                                sizeof(repeater_mode));

        }

        if (result == DC_OK) {
                link->dpcd_caps.lttpr_caps.mode = repeater_mode;
        }

        if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {

                DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent Mode\n", __func__);

                repeater_mode = DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
                result = core_link_write_dpcd(link,
                                DP_PHY_REPEATER_MODE,
                                (uint8_t *)&repeater_mode,
                                sizeof(repeater_mode));

                if (result == DC_OK) {
                        link->dpcd_caps.lttpr_caps.mode = repeater_mode;
                }

                if (encoding == DP_8b_10b_ENCODING) {
                        repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);
                        for (repeater_id = repeater_cnt; repeater_id > 0; repeater_id--) {
                                aux_interval_address = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 +
                                                        ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (repeater_id - 1));
                                core_link_read_dpcd(
                                        link,
                                        aux_interval_address,
                                        (uint8_t *)&link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1],
                                        sizeof(link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1]));
                                link->dpcd_caps.lttpr_caps.aux_rd_interval[repeater_id - 1] &= 0x7F;
                        }
                }
        }

        return result;
}

static void repeater_training_done(struct dc_link *link, uint32_t offset)
{
        union dpcd_training_pattern dpcd_pattern = { {0} };

        const uint32_t dpcd_base_lt_offset =
                        DP_TRAINING_PATTERN_SET_PHY_REPEATER1 +
                                ((DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE) * (offset - 1));
        /* Set training not in progress*/
        dpcd_pattern.v1_4.TRAINING_PATTERN_SET = DPCD_TRAINING_PATTERN_VIDEOIDLE;

        core_link_write_dpcd(
                link,
                dpcd_base_lt_offset,
                &dpcd_pattern.raw,
                1);

        DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Id: %d 0x%X pattern = %x\n",
                __func__,
                offset,
                dpcd_base_lt_offset,
                dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
}

static void print_status_message(
        struct dc_link *link,
        const struct link_training_settings *lt_settings,
        enum link_training_result status)
{
        char *link_rate = "Unknown";
        char *lt_result = "Unknown";
        char *lt_spread = "Disabled";

        switch (lt_settings->link_settings.link_rate) {
        case LINK_RATE_LOW:
                link_rate = "RBR";
                break;
        case LINK_RATE_RATE_2:
                link_rate = "R2";
                break;
        case LINK_RATE_RATE_3:
                link_rate = "R3";
                break;
        case LINK_RATE_HIGH:
                link_rate = "HBR";
                break;
        case LINK_RATE_RBR2:
                link_rate = "RBR2";
                break;
        case LINK_RATE_RATE_6:
                link_rate = "R6";
                break;
        case LINK_RATE_HIGH2:
                link_rate = "HBR2";
                break;
        case LINK_RATE_HIGH3:
                link_rate = "HBR3";
                break;
        default:
                break;
        }

        switch (status) {
        case LINK_TRAINING_SUCCESS:
                lt_result = "pass";
                break;
        case LINK_TRAINING_CR_FAIL_LANE0:
                lt_result = "CR failed lane0";
                break;
        case LINK_TRAINING_CR_FAIL_LANE1:
                lt_result = "CR failed lane1";
                break;
        case LINK_TRAINING_CR_FAIL_LANE23:
                lt_result = "CR failed lane23";
                break;
        case LINK_TRAINING_EQ_FAIL_CR:
                lt_result = "CR failed in EQ";
                break;
        case LINK_TRAINING_EQ_FAIL_EQ:
                lt_result = "EQ failed";
                break;
        case LINK_TRAINING_LQA_FAIL:
                lt_result = "LQA failed";
                break;
        case LINK_TRAINING_LINK_LOSS:
                lt_result = "Link loss";
                break;
        default:
                break;
        }

        switch (lt_settings->link_settings.link_spread) {
        case LINK_SPREAD_DISABLED:
                lt_spread = "Disabled";
                break;
        case LINK_SPREAD_05_DOWNSPREAD_30KHZ:
                lt_spread = "0.5% 30KHz";
                break;
        case LINK_SPREAD_05_DOWNSPREAD_33KHZ:
                lt_spread = "0.5% 33KHz";
                break;
        default:
                break;
        }

        /* Connectivity log: link training */
        CONN_MSG_LT(link, "%sx%d %s VS=%d, PE=%d, DS=%s",
                                link_rate,
                                lt_settings->link_settings.lane_count,
                                lt_result,
                                lt_settings->lane_settings[0].VOLTAGE_SWING,
                                lt_settings->lane_settings[0].PRE_EMPHASIS,
                                lt_spread);
}

void dc_link_dp_set_drive_settings(
        struct dc_link *link,
        struct link_training_settings *lt_settings)
{
        /* program ASIC PHY settings*/
        dp_set_hw_lane_settings(link, lt_settings, DPRX);

        /* Notify DP sink the PHY settings from source */
        dpcd_set_lane_settings(link, lt_settings, DPRX);
}

bool dc_link_dp_perform_link_training_skip_aux(
        struct dc_link *link,
        const struct dc_link_settings *link_setting)
{
        struct link_training_settings lt_settings;

        dp_decide_training_settings(
                        link,
                        link_setting,
                        &link->preferred_training_settings,
                        &lt_settings);

        /* 1. Perform_clock_recovery_sequence. */

        /* transmit training pattern for clock recovery */
        dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);

        /* call HWSS to set lane settings*/
        dp_set_hw_lane_settings(link, &lt_settings, DPRX);

        /* wait receiver to lock-on*/
        dp_wait_for_training_aux_rd_interval(link, lt_settings.cr_pattern_time);

        /* 2. Perform_channel_equalization_sequence. */

        /* transmit training pattern for channel equalization. */
        dp_set_hw_training_pattern(link, lt_settings.pattern_for_eq, DPRX);

        /* call HWSS to set lane settings*/
        dp_set_hw_lane_settings(link, &lt_settings, DPRX);

        /* wait receiver to lock-on. */
        dp_wait_for_training_aux_rd_interval(link, lt_settings.eq_pattern_time);

        /* 3. Perform_link_training_int. */

        /* Mainlink output idle pattern. */
        dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);

        print_status_message(link, &lt_settings, LINK_TRAINING_SUCCESS);

        return true;
}

enum dc_status dpcd_configure_lttpr_mode(struct dc_link *link, struct link_training_settings *lt_settings)
{
        enum dc_status status = DC_OK;

        if (lt_settings->lttpr_mode == LTTPR_MODE_TRANSPARENT)
                status = configure_lttpr_mode_transparent(link);

        else if (lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT)
                status = configure_lttpr_mode_non_transparent(link, lt_settings);

        return status;
}

static void dpcd_exit_training_mode(struct dc_link *link)
{

        /* clear training pattern set */
        dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE);
}

enum dc_status dpcd_configure_channel_coding(struct dc_link *link,
                struct link_training_settings *lt_settings)
{
        enum dp_link_encoding encoding =
                        dp_get_link_encoding_format(
                                        &lt_settings->link_settings);
        enum dc_status status;

        status = core_link_write_dpcd(
                        link,
                        DP_MAIN_LINK_CHANNEL_CODING_SET,
                        (uint8_t *) &encoding,
                        1);
        DC_LOG_HW_LINK_TRAINING("%s:\n 0x%X MAIN_LINK_CHANNEL_CODING_SET = %x\n",
                                        __func__,
                                        DP_MAIN_LINK_CHANNEL_CODING_SET,
                                        encoding);

        return status;
}

static enum link_training_result dp_perform_8b_10b_link_training(
                struct dc_link *link,
                struct link_training_settings *lt_settings)
{
        enum link_training_result status = LINK_TRAINING_SUCCESS;

        uint8_t repeater_cnt;
        uint8_t repeater_id;
        uint8_t lane = 0;

        if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
                start_clock_recovery_pattern_early(link, lt_settings, DPRX);

        /* 1. set link rate, lane count and spread. */
        dpcd_set_link_settings(link, lt_settings);

        if (link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) {

                /* 2. perform link training (set link training done
                 *  to false is done as well)
                 */
                repeater_cnt = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt);

                for (repeater_id = repeater_cnt; (repeater_id > 0 && status == LINK_TRAINING_SUCCESS);
                                repeater_id--) {
                        status = perform_clock_recovery_sequence(link, lt_settings, repeater_id);

                        if (status != LINK_TRAINING_SUCCESS)
                                break;

                        status = perform_channel_equalization_sequence(link,
                                        lt_settings,
                                        repeater_id);

                        if (status != LINK_TRAINING_SUCCESS)
                                break;

                        repeater_training_done(link, repeater_id);
                }

                for (lane = 0; lane < (uint8_t)lt_settings->link_settings.lane_count; lane++)
                        lt_settings->lane_settings[lane].VOLTAGE_SWING = VOLTAGE_SWING_LEVEL0;
        }

        if (status == LINK_TRAINING_SUCCESS) {
                status = perform_clock_recovery_sequence(link, lt_settings, DPRX);
        if (status == LINK_TRAINING_SUCCESS) {
                status = perform_channel_equalization_sequence(link,
                                        lt_settings,
                                        DPRX);
                }
        }

        return status;
}

enum link_training_result dc_link_dp_perform_link_training(
        struct dc_link *link,
        const struct dc_link_settings *link_settings,
        bool skip_video_pattern)
{
        enum link_training_result status = LINK_TRAINING_SUCCESS;
        struct link_training_settings lt_settings;
        enum dp_link_encoding encoding =
                        dp_get_link_encoding_format(link_settings);

        /* decide training settings */
        dp_decide_training_settings(
                        link,
                        link_settings,
                        &link->preferred_training_settings,
                        &lt_settings);

        /* reset previous training states */
        dpcd_exit_training_mode(link);

        /* configure link prior to entering training mode */
        dpcd_configure_lttpr_mode(link, &lt_settings);
        dp_set_fec_ready(link, lt_settings.should_set_fec_ready);
        dpcd_configure_channel_coding(link, &lt_settings);

        /* enter training mode:
         * Per DP specs starting from here, DPTX device shall not issue
         * Non-LT AUX transactions inside training mode.
         */
        if (encoding == DP_8b_10b_ENCODING)
                status = dp_perform_8b_10b_link_training(link, &lt_settings);
        else
                ASSERT(0);

        /* exit training mode and switch to video idle */
        dpcd_exit_training_mode(link);
        if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern)
                status = dp_transition_to_video_idle(link,
                                &lt_settings,
                                status);

        /* dump debug data */
        print_status_message(link, &lt_settings, status);
        if (status != LINK_TRAINING_SUCCESS)
                link->ctx->dc->debug_data.ltFailCount++;
        return status;
}

bool perform_link_training_with_retries(
        const struct dc_link_settings *link_setting,
        bool skip_video_pattern,
        int attempts,
        struct pipe_ctx *pipe_ctx,
        enum signal_type signal,
        bool do_fallback)
{
        int j;
        uint8_t delay_between_attempts = LINK_TRAINING_RETRY_DELAY;
        struct dc_stream_state *stream = pipe_ctx->stream;
        struct dc_link *link = stream->link;
        enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
        struct link_encoder *link_enc;
        enum link_training_result status = LINK_TRAINING_CR_FAIL_LANE0;
        struct dc_link_settings current_setting = *link_setting;

        /* Dynamically assigned link encoders associated with stream rather than
         * link.
         */
        if (link->dc->res_pool->funcs->link_encs_assign)
                link_enc = stream->link_enc;
        else
                link_enc = link->link_enc;

        /* We need to do this before the link training to ensure the idle pattern in SST
         * mode will be sent right after the link training
         */
        link_enc->funcs->connect_dig_be_to_fe(link_enc,
                                                        pipe_ctx->stream_res.stream_enc->id, true);

        for (j = 0; j < attempts; ++j) {

                DC_LOG_HW_LINK_TRAINING("%s: Beginning link training attempt %u of %d\n",
                        __func__, (unsigned int)j + 1, attempts);

                dp_enable_link_phy(
                        link,
                        signal,
                        pipe_ctx->clock_source->id,
                        &current_setting);

                if (stream->sink_patches.dppowerup_delay > 0) {
                        int delay_dp_power_up_in_ms = stream->sink_patches.dppowerup_delay;

                        msleep(delay_dp_power_up_in_ms);
                }

#ifdef CONFIG_DRM_AMD_DC_HDCP
                if (panel_mode == DP_PANEL_MODE_EDP) {
                        struct cp_psp *cp_psp = &stream->ctx->cp_psp;

                        if (cp_psp && cp_psp->funcs.enable_assr) {
                                if (!cp_psp->funcs.enable_assr(cp_psp->handle, link)) {
                                        /* since eDP implies ASSR on, change panel
                                         * mode to disable ASSR
                                         */
                                        panel_mode = DP_PANEL_MODE_DEFAULT;
                                }
                        }
                }
#endif

                dp_set_panel_mode(link, panel_mode);

                if (link->aux_access_disabled) {
                        dc_link_dp_perform_link_training_skip_aux(link, &current_setting);
                        return true;
                } else {
                                status = dc_link_dp_perform_link_training(
                                                                                link,
                                                                                &current_setting,
                                                                                skip_video_pattern);
                        if (status == LINK_TRAINING_SUCCESS)
                                return true;
                }

                /* latest link training still fail, skip delay and keep PHY on
                 */
                if (j == (attempts - 1) && link->ep_type == DISPLAY_ENDPOINT_PHY)
                        break;

                DC_LOG_WARNING("%s: Link training attempt %u of %d failed\n",
                        __func__, (unsigned int)j + 1, attempts);

                dp_disable_link_phy(link, signal);

                /* Abort link training if failure due to sink being unplugged. */
                if (status == LINK_TRAINING_ABORT)
                        break;
                else if (do_fallback) {
                        decide_fallback_link_setting(*link_setting, &current_setting, status);
                        /* Fail link training if reduced link bandwidth no longer meets
                         * stream requirements.
                         */
                        if (dc_bandwidth_in_kbps_from_timing(&stream->timing) <
                                        dc_link_bandwidth_kbps(link, &current_setting))
                                break;
                }

                msleep(delay_between_attempts);

                delay_between_attempts += LINK_TRAINING_RETRY_DELAY;
        }

        return false;
}

static enum clock_source_id get_clock_source_id(struct dc_link *link)
{
        enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_UNDEFINED;
        struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source;

        if (dp_cs != NULL) {
                dp_cs_id = dp_cs->id;
        } else {
                /*
                 * dp clock source is not initialized for some reason.
                 * Should not happen, CLOCK_SOURCE_ID_EXTERNAL will be used
                 */
                ASSERT(dp_cs);
        }

        return dp_cs_id;
}

static void set_dp_mst_mode(struct dc_link *link, bool mst_enable)
{
        if (mst_enable == false &&
                link->type == dc_connection_mst_branch) {
                /* Disable MST on link. Use only local sink. */
                dp_disable_link_phy_mst(link, link->connector_signal);

                link->type = dc_connection_single;
                link->local_sink = link->remote_sinks[0];
                link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT;
                dc_sink_retain(link->local_sink);
                dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
        } else if (mst_enable == true &&
                        link->type == dc_connection_single &&
                        link->remote_sinks[0] != NULL) {
                /* Re-enable MST on link. */
                dp_disable_link_phy(link, link->connector_signal);
                dp_enable_mst_on_sink(link, true);

                link->type = dc_connection_mst_branch;
                link->local_sink->sink_signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
        }
}

bool dc_link_dp_sync_lt_begin(struct dc_link *link)
{
        /* Begin Sync LT. During this time,
         * DPCD:600h must not be powered down.
         */
        link->sync_lt_in_progress = true;

        /*Clear any existing preferred settings.*/
        memset(&link->preferred_training_settings, 0,
                sizeof(struct dc_link_training_overrides));
        memset(&link->preferred_link_setting, 0,
                sizeof(struct dc_link_settings));

        return true;
}

enum link_training_result dc_link_dp_sync_lt_attempt(
    struct dc_link *link,
    struct dc_link_settings *link_settings,
    struct dc_link_training_overrides *lt_overrides)
{
        struct link_training_settings lt_settings;
        enum link_training_result lt_status = LINK_TRAINING_SUCCESS;
        enum dp_panel_mode panel_mode = DP_PANEL_MODE_DEFAULT;
        enum clock_source_id dp_cs_id = CLOCK_SOURCE_ID_EXTERNAL;
        bool fec_enable = false;

        dp_decide_training_settings(
                link,
                link_settings,
                lt_overrides,
                &lt_settings);

        /* Setup MST Mode */
        if (lt_overrides->mst_enable)
                set_dp_mst_mode(link, *lt_overrides->mst_enable);

        /* Disable link */
        dp_disable_link_phy(link, link->connector_signal);

        /* Enable link */
        dp_cs_id = get_clock_source_id(link);
        dp_enable_link_phy(link, link->connector_signal,
                dp_cs_id, link_settings);

        /* Set FEC enable */
        fec_enable = lt_overrides->fec_enable && *lt_overrides->fec_enable;
        dp_set_fec_ready(link, fec_enable);

        if (lt_overrides->alternate_scrambler_reset) {
                if (*lt_overrides->alternate_scrambler_reset)
                        panel_mode = DP_PANEL_MODE_EDP;
                else
                        panel_mode = DP_PANEL_MODE_DEFAULT;
        } else
                panel_mode = dp_get_panel_mode(link);

        dp_set_panel_mode(link, panel_mode);

        /* Attempt to train with given link training settings */
        if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
                start_clock_recovery_pattern_early(link, &lt_settings, DPRX);

        /* Set link rate, lane count and spread. */
        dpcd_set_link_settings(link, &lt_settings);

        /* 2. perform link training (set link training done
         *  to false is done as well)
         */
        lt_status = perform_clock_recovery_sequence(link, &lt_settings, DPRX);
        if (lt_status == LINK_TRAINING_SUCCESS) {
                lt_status = perform_channel_equalization_sequence(link,
                                                &lt_settings,
                                                DPRX);
        }

        /* 3. Sync LT must skip TRAINING_PATTERN_SET:0 (video pattern)*/
        /* 4. print status message*/
        print_status_message(link, &lt_settings, lt_status);

        return lt_status;
}

bool dc_link_dp_sync_lt_end(struct dc_link *link, bool link_down)
{
        /* If input parameter is set, shut down phy.
         * Still shouldn't turn off dp_receiver (DPCD:600h)