linux/drivers/gpu/drm/amd/display/dc/core/dc_link.c
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   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include <linux/slab.h>
  27
  28#include "dm_services.h"
  29#include "atomfirmware.h"
  30#include "dm_helpers.h"
  31#include "dc.h"
  32#include "grph_object_id.h"
  33#include "gpio_service_interface.h"
  34#include "core_status.h"
  35#include "dc_link_dp.h"
  36#include "dc_link_ddc.h"
  37#include "link_hwss.h"
  38#include "opp.h"
  39
  40#include "link_encoder.h"
  41#include "hw_sequencer.h"
  42#include "resource.h"
  43#include "abm.h"
  44#include "fixed31_32.h"
  45#include "dpcd_defs.h"
  46#include "dmcu.h"
  47#include "hw/clk_mgr.h"
  48#include "dce/dmub_psr.h"
  49#include "dmub/dmub_srv.h"
  50#include "inc/hw/panel_cntl.h"
  51#include "inc/link_enc_cfg.h"
  52#include "inc/link_dpcd.h"
  53
  54#define DC_LOGGER_INIT(logger)
  55
  56#define LINK_INFO(...) \
  57        DC_LOG_HW_HOTPLUG(  \
  58                __VA_ARGS__)
  59
  60#define RETIMER_REDRIVER_INFO(...) \
  61        DC_LOG_RETIMER_REDRIVER(  \
  62                __VA_ARGS__)
  63
  64/*******************************************************************************
  65 * Private functions
  66 ******************************************************************************/
  67static void dc_link_destruct(struct dc_link *link)
  68{
  69        int i;
  70
  71        if (link->hpd_gpio) {
  72                dal_gpio_destroy_irq(&link->hpd_gpio);
  73                link->hpd_gpio = NULL;
  74        }
  75
  76        if (link->ddc)
  77                dal_ddc_service_destroy(&link->ddc);
  78
  79        if (link->panel_cntl)
  80                link->panel_cntl->funcs->destroy(&link->panel_cntl);
  81
  82        if (link->link_enc) {
  83                /* Update link encoder resource tracking variables. These are used for
  84                 * the dynamic assignment of link encoders to streams. Virtual links
  85                 * are not assigned encoder resources on creation.
  86                 */
  87                if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
  88                        link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
  89                        link->dc->res_pool->dig_link_enc_count--;
  90                }
  91                link->link_enc->funcs->destroy(&link->link_enc);
  92        }
  93
  94        if (link->local_sink)
  95                dc_sink_release(link->local_sink);
  96
  97        for (i = 0; i < link->sink_count; ++i)
  98                dc_sink_release(link->remote_sinks[i]);
  99}
 100
 101struct gpio *get_hpd_gpio(struct dc_bios *dcb,
 102                          struct graphics_object_id link_id,
 103                          struct gpio_service *gpio_service)
 104{
 105        enum bp_result bp_result;
 106        struct graphics_object_hpd_info hpd_info;
 107        struct gpio_pin_info pin_info;
 108
 109        if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
 110                return NULL;
 111
 112        bp_result = dcb->funcs->get_gpio_pin_info(dcb,
 113                hpd_info.hpd_int_gpio_uid, &pin_info);
 114
 115        if (bp_result != BP_RESULT_OK) {
 116                ASSERT(bp_result == BP_RESULT_NORECORD);
 117                return NULL;
 118        }
 119
 120        return dal_gpio_service_create_irq(gpio_service,
 121                                           pin_info.offset,
 122                                           pin_info.mask);
 123}
 124
 125/*
 126 *  Function: program_hpd_filter
 127 *
 128 *  @brief
 129 *     Programs HPD filter on associated HPD line
 130 *
 131 *  @param [in] delay_on_connect_in_ms: Connect filter timeout
 132 *  @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout
 133 *
 134 *  @return
 135 *     true on success, false otherwise
 136 */
 137static bool program_hpd_filter(const struct dc_link *link)
 138{
 139        bool result = false;
 140        struct gpio *hpd;
 141        int delay_on_connect_in_ms = 0;
 142        int delay_on_disconnect_in_ms = 0;
 143
 144        if (link->is_hpd_filter_disabled)
 145                return false;
 146        /* Verify feature is supported */
 147        switch (link->connector_signal) {
 148        case SIGNAL_TYPE_DVI_SINGLE_LINK:
 149        case SIGNAL_TYPE_DVI_DUAL_LINK:
 150        case SIGNAL_TYPE_HDMI_TYPE_A:
 151                /* Program hpd filter */
 152                delay_on_connect_in_ms = 500;
 153                delay_on_disconnect_in_ms = 100;
 154                break;
 155        case SIGNAL_TYPE_DISPLAY_PORT:
 156        case SIGNAL_TYPE_DISPLAY_PORT_MST:
 157                /* Program hpd filter to allow DP signal to settle */
 158                /* 500: not able to detect MST <-> SST switch as HPD is low for
 159                 * only 100ms on DELL U2413
 160                 * 0: some passive dongle still show aux mode instead of i2c
 161                 * 20-50: not enough to hide bouncing HPD with passive dongle.
 162                 * also see intermittent i2c read issues.
 163                 */
 164                delay_on_connect_in_ms = 80;
 165                delay_on_disconnect_in_ms = 0;
 166                break;
 167        case SIGNAL_TYPE_LVDS:
 168        case SIGNAL_TYPE_EDP:
 169        default:
 170                /* Don't program hpd filter */
 171                return false;
 172        }
 173
 174        /* Obtain HPD handle */
 175        hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 176                           link->ctx->gpio_service);
 177
 178        if (!hpd)
 179                return result;
 180
 181        /* Setup HPD filtering */
 182        if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
 183                struct gpio_hpd_config config;
 184
 185                config.delay_on_connect = delay_on_connect_in_ms;
 186                config.delay_on_disconnect = delay_on_disconnect_in_ms;
 187
 188                dal_irq_setup_hpd_filter(hpd, &config);
 189
 190                dal_gpio_close(hpd);
 191
 192                result = true;
 193        } else {
 194                ASSERT_CRITICAL(false);
 195        }
 196
 197        /* Release HPD handle */
 198        dal_gpio_destroy_irq(&hpd);
 199
 200        return result;
 201}
 202
 203bool dc_link_wait_for_t12(struct dc_link *link)
 204{
 205        if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
 206                link->dc->hwss.edp_wait_for_T12(link);
 207
 208                return true;
 209        }
 210
 211        return false;
 212}
 213
 214/**
 215 * dc_link_detect_sink() - Determine if there is a sink connected
 216 *
 217 * @link: pointer to the dc link
 218 * @type: Returned connection type
 219 * Does not detect downstream devices, such as MST sinks
 220 * or display connected through active dongles
 221 */
 222bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 223{
 224        uint32_t is_hpd_high = 0;
 225        struct gpio *hpd_pin;
 226
 227        if (link->connector_signal == SIGNAL_TYPE_LVDS) {
 228                *type = dc_connection_single;
 229                return true;
 230        }
 231
 232        if (link->connector_signal == SIGNAL_TYPE_EDP) {
 233                /*in case it is not on*/
 234                link->dc->hwss.edp_power_control(link, true);
 235                link->dc->hwss.edp_wait_for_hpd_ready(link, true);
 236        }
 237
 238        /* Link may not have physical HPD pin. */
 239        if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
 240                if (link->hpd_status)
 241                        *type = dc_connection_single;
 242                else
 243                        *type = dc_connection_none;
 244
 245                return true;
 246        }
 247
 248        /* todo: may need to lock gpio access */
 249        hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
 250                               link->ctx->gpio_service);
 251        if (!hpd_pin)
 252                goto hpd_gpio_failure;
 253
 254        dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
 255        dal_gpio_get_value(hpd_pin, &is_hpd_high);
 256        dal_gpio_close(hpd_pin);
 257        dal_gpio_destroy_irq(&hpd_pin);
 258
 259        if (is_hpd_high) {
 260                *type = dc_connection_single;
 261                /* TODO: need to do the actual detection */
 262        } else {
 263                *type = dc_connection_none;
 264        }
 265
 266        return true;
 267
 268hpd_gpio_failure:
 269        return false;
 270}
 271
 272static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
 273{
 274        enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
 275
 276        switch (sink_signal) {
 277        case SIGNAL_TYPE_DVI_SINGLE_LINK:
 278        case SIGNAL_TYPE_DVI_DUAL_LINK:
 279        case SIGNAL_TYPE_HDMI_TYPE_A:
 280        case SIGNAL_TYPE_LVDS:
 281        case SIGNAL_TYPE_RGB:
 282                transaction_type = DDC_TRANSACTION_TYPE_I2C;
 283                break;
 284
 285        case SIGNAL_TYPE_DISPLAY_PORT:
 286        case SIGNAL_TYPE_EDP:
 287                transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 288                break;
 289
 290        case SIGNAL_TYPE_DISPLAY_PORT_MST:
 291                /* MST does not use I2COverAux, but there is the
 292                 * SPECIAL use case for "immediate dwnstrm device
 293                 * access" (EPR#370830).
 294                 */
 295                transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 296                break;
 297
 298        default:
 299                break;
 300        }
 301
 302        return transaction_type;
 303}
 304
 305static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
 306                                              struct graphics_object_id downstream)
 307{
 308        if (downstream.type == OBJECT_TYPE_CONNECTOR) {
 309                switch (downstream.id) {
 310                case CONNECTOR_ID_SINGLE_LINK_DVII:
 311                        switch (encoder.id) {
 312                        case ENCODER_ID_INTERNAL_DAC1:
 313                        case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 314                        case ENCODER_ID_INTERNAL_DAC2:
 315                        case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 316                                return SIGNAL_TYPE_RGB;
 317                        default:
 318                                return SIGNAL_TYPE_DVI_SINGLE_LINK;
 319                        }
 320                break;
 321                case CONNECTOR_ID_DUAL_LINK_DVII:
 322                {
 323                        switch (encoder.id) {
 324                        case ENCODER_ID_INTERNAL_DAC1:
 325                        case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
 326                        case ENCODER_ID_INTERNAL_DAC2:
 327                        case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
 328                                return SIGNAL_TYPE_RGB;
 329                        default:
 330                                return SIGNAL_TYPE_DVI_DUAL_LINK;
 331                        }
 332                }
 333                break;
 334                case CONNECTOR_ID_SINGLE_LINK_DVID:
 335                        return SIGNAL_TYPE_DVI_SINGLE_LINK;
 336                case CONNECTOR_ID_DUAL_LINK_DVID:
 337                        return SIGNAL_TYPE_DVI_DUAL_LINK;
 338                case CONNECTOR_ID_VGA:
 339                        return SIGNAL_TYPE_RGB;
 340                case CONNECTOR_ID_HDMI_TYPE_A:
 341                        return SIGNAL_TYPE_HDMI_TYPE_A;
 342                case CONNECTOR_ID_LVDS:
 343                        return SIGNAL_TYPE_LVDS;
 344                case CONNECTOR_ID_DISPLAY_PORT:
 345                        return SIGNAL_TYPE_DISPLAY_PORT;
 346                case CONNECTOR_ID_EDP:
 347                        return SIGNAL_TYPE_EDP;
 348                default:
 349                        return SIGNAL_TYPE_NONE;
 350                }
 351        } else if (downstream.type == OBJECT_TYPE_ENCODER) {
 352                switch (downstream.id) {
 353                case ENCODER_ID_EXTERNAL_NUTMEG:
 354                case ENCODER_ID_EXTERNAL_TRAVIS:
 355                        return SIGNAL_TYPE_DISPLAY_PORT;
 356                default:
 357                        return SIGNAL_TYPE_NONE;
 358                }
 359        }
 360
 361        return SIGNAL_TYPE_NONE;
 362}
 363
 364/*
 365 * dc_link_is_dp_sink_present() - Check if there is a native DP
 366 * or passive DP-HDMI dongle connected
 367 */
 368bool dc_link_is_dp_sink_present(struct dc_link *link)
 369{
 370        enum gpio_result gpio_result;
 371        uint32_t clock_pin = 0;
 372        uint8_t retry = 0;
 373        struct ddc *ddc;
 374
 375        enum connector_id connector_id =
 376                dal_graphics_object_id_get_connector_id(link->link_id);
 377
 378        bool present =
 379                ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
 380                (connector_id == CONNECTOR_ID_EDP));
 381
 382        ddc = dal_ddc_service_get_ddc_pin(link->ddc);
 383
 384        if (!ddc) {
 385                BREAK_TO_DEBUGGER();
 386                return present;
 387        }
 388
 389        /* Open GPIO and set it to I2C mode */
 390        /* Note: this GpioMode_Input will be converted
 391         * to GpioConfigType_I2cAuxDualMode in GPIO component,
 392         * which indicates we need additional delay
 393         */
 394
 395        if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
 396                         GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
 397                dal_ddc_close(ddc);
 398
 399                return present;
 400        }
 401
 402        /*
 403         * Read GPIO: DP sink is present if both clock and data pins are zero
 404         *
 405         * [W/A] plug-unplug DP cable, sometimes customer board has
 406         * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI
 407         * then monitor can't br light up. Add retry 3 times
 408         * But in real passive dongle, it need additional 3ms to detect
 409         */
 410        do {
 411                gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
 412                ASSERT(gpio_result == GPIO_RESULT_OK);
 413                if (clock_pin)
 414                        udelay(1000);
 415                else
 416                        break;
 417        } while (retry++ < 3);
 418
 419        present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
 420
 421        dal_ddc_close(ddc);
 422
 423        return present;
 424}
 425
 426/*
 427 * @brief
 428 * Detect output sink type
 429 */
 430static enum signal_type link_detect_sink(struct dc_link *link,
 431                                         enum dc_detect_reason reason)
 432{
 433        enum signal_type result;
 434        struct graphics_object_id enc_id;
 435
 436        if (link->is_dig_mapping_flexible)
 437                enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
 438        else
 439                enc_id = link->link_enc->id;
 440        result = get_basic_signal_type(enc_id, link->link_id);
 441
 442        /* Use basic signal type for link without physical connector. */
 443        if (link->ep_type != DISPLAY_ENDPOINT_PHY)
 444                return result;
 445
 446        /* Internal digital encoder will detect only dongles
 447         * that require digital signal
 448         */
 449
 450        /* Detection mechanism is different
 451         * for different native connectors.
 452         * LVDS connector supports only LVDS signal;
 453         * PCIE is a bus slot, the actual connector needs to be detected first;
 454         * eDP connector supports only eDP signal;
 455         * HDMI should check straps for audio
 456         */
 457
 458        /* PCIE detects the actual connector on add-on board */
 459        if (link->link_id.id == CONNECTOR_ID_PCIE) {
 460                /* ZAZTODO implement PCIE add-on card detection */
 461        }
 462
 463        switch (link->link_id.id) {
 464        case CONNECTOR_ID_HDMI_TYPE_A: {
 465                /* check audio support:
 466                 * if native HDMI is not supported, switch to DVI
 467                 */
 468                struct audio_support *aud_support =
 469                                        &link->dc->res_pool->audio_support;
 470
 471                if (!aud_support->hdmi_audio_native)
 472                        if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
 473                                result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 474        }
 475        break;
 476        case CONNECTOR_ID_DISPLAY_PORT: {
 477                /* DP HPD short pulse. Passive DP dongle will not
 478                 * have short pulse
 479                 */
 480                if (reason != DETECT_REASON_HPDRX) {
 481                        /* Check whether DP signal detected: if not -
 482                         * we assume signal is DVI; it could be corrected
 483                         * to HDMI after dongle detection
 484                         */
 485                        if (!dm_helpers_is_dp_sink_present(link))
 486                                result = SIGNAL_TYPE_DVI_SINGLE_LINK;
 487                }
 488        }
 489        break;
 490        default:
 491        break;
 492        }
 493
 494        return result;
 495}
 496
 497static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
 498                                                                 struct audio_support *audio_support)
 499{
 500        enum signal_type signal = SIGNAL_TYPE_NONE;
 501
 502        switch (dongle_type) {
 503        case DISPLAY_DONGLE_DP_HDMI_DONGLE:
 504                if (audio_support->hdmi_audio_on_dongle)
 505                        signal = SIGNAL_TYPE_HDMI_TYPE_A;
 506                else
 507                        signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 508                break;
 509        case DISPLAY_DONGLE_DP_DVI_DONGLE:
 510                signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 511                break;
 512        case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
 513                if (audio_support->hdmi_audio_native)
 514                        signal =  SIGNAL_TYPE_HDMI_TYPE_A;
 515                else
 516                        signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 517                break;
 518        default:
 519                signal = SIGNAL_TYPE_NONE;
 520                break;
 521        }
 522
 523        return signal;
 524}
 525
 526static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
 527                                                    struct display_sink_capability *sink_cap,
 528                                                    struct audio_support *audio_support)
 529{
 530        dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
 531
 532        return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
 533                                                        audio_support);
 534}
 535
 536static void link_disconnect_sink(struct dc_link *link)
 537{
 538        if (link->local_sink) {
 539                dc_sink_release(link->local_sink);
 540                link->local_sink = NULL;
 541        }
 542
 543        link->dpcd_sink_count = 0;
 544}
 545
 546static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
 547{
 548        dc_sink_release(link->local_sink);
 549        link->local_sink = prev_sink;
 550}
 551
 552#if defined(CONFIG_DRM_AMD_DC_HDCP)
 553bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
 554{
 555        bool ret = false;
 556
 557        switch (signal) {
 558        case SIGNAL_TYPE_DISPLAY_PORT:
 559        case SIGNAL_TYPE_DISPLAY_PORT_MST:
 560                ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
 561                break;
 562        case SIGNAL_TYPE_DVI_SINGLE_LINK:
 563        case SIGNAL_TYPE_DVI_DUAL_LINK:
 564        case SIGNAL_TYPE_HDMI_TYPE_A:
 565        /* HDMI doesn't tell us its HDCP(1.4) capability, so assume to always be capable,
 566         * we can poll for bksv but some displays have an issue with this. Since its so rare
 567         * for a display to not be 1.4 capable, this assumtion is ok
 568         */
 569                ret = true;
 570                break;
 571        default:
 572                break;
 573        }
 574        return ret;
 575}
 576
 577bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
 578{
 579        bool ret = false;
 580
 581        switch (signal) {
 582        case SIGNAL_TYPE_DISPLAY_PORT:
 583        case SIGNAL_TYPE_DISPLAY_PORT_MST:
 584                ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
 585                                link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
 586                                (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
 587                break;
 588        case SIGNAL_TYPE_DVI_SINGLE_LINK:
 589        case SIGNAL_TYPE_DVI_DUAL_LINK:
 590        case SIGNAL_TYPE_HDMI_TYPE_A:
 591                ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
 592                break;
 593        default:
 594                break;
 595        }
 596
 597        return ret;
 598}
 599
 600static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
 601{
 602        struct hdcp_protection_message msg22;
 603        struct hdcp_protection_message msg14;
 604
 605        memset(&msg22, 0, sizeof(struct hdcp_protection_message));
 606        memset(&msg14, 0, sizeof(struct hdcp_protection_message));
 607        memset(link->hdcp_caps.rx_caps.raw, 0,
 608                sizeof(link->hdcp_caps.rx_caps.raw));
 609
 610        if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
 611                        link->ddc->transaction_type ==
 612                        DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
 613                        link->connector_signal == SIGNAL_TYPE_EDP) {
 614                msg22.data = link->hdcp_caps.rx_caps.raw;
 615                msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
 616                msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
 617        } else {
 618                msg22.data = &link->hdcp_caps.rx_caps.fields.version;
 619                msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
 620                msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
 621        }
 622        msg22.version = HDCP_VERSION_22;
 623        msg22.link = HDCP_LINK_PRIMARY;
 624        msg22.max_retries = 5;
 625        dc_process_hdcp_msg(signal, link, &msg22);
 626
 627        if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 628                msg14.data = &link->hdcp_caps.bcaps.raw;
 629                msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
 630                msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
 631                msg14.version = HDCP_VERSION_14;
 632                msg14.link = HDCP_LINK_PRIMARY;
 633                msg14.max_retries = 5;
 634
 635                dc_process_hdcp_msg(signal, link, &msg14);
 636        }
 637
 638}
 639#endif
 640
 641static void read_current_link_settings_on_detect(struct dc_link *link)
 642{
 643        union lane_count_set lane_count_set = { {0} };
 644        uint8_t link_bw_set;
 645        uint8_t link_rate_set;
 646        uint32_t read_dpcd_retry_cnt = 10;
 647        enum dc_status status = DC_ERROR_UNEXPECTED;
 648        int i;
 649        union max_down_spread max_down_spread = { {0} };
 650
 651        // Read DPCD 00101h to find out the number of lanes currently set
 652        for (i = 0; i < read_dpcd_retry_cnt; i++) {
 653                status = core_link_read_dpcd(link,
 654                                             DP_LANE_COUNT_SET,
 655                                             &lane_count_set.raw,
 656                                             sizeof(lane_count_set));
 657                /* First DPCD read after VDD ON can fail if the particular board
 658                 * does not have HPD pin wired correctly. So if DPCD read fails,
 659                 * which it should never happen, retry a few times. Target worst
 660                 * case scenario of 80 ms.
 661                 */
 662                if (status == DC_OK) {
 663                        link->cur_link_settings.lane_count =
 664                                        lane_count_set.bits.LANE_COUNT_SET;
 665                        break;
 666                }
 667
 668                msleep(8);
 669        }
 670
 671        // Read DPCD 00100h to find if standard link rates are set
 672        core_link_read_dpcd(link, DP_LINK_BW_SET,
 673                            &link_bw_set, sizeof(link_bw_set));
 674
 675        if (link_bw_set == 0) {
 676                if (link->connector_signal == SIGNAL_TYPE_EDP) {
 677                        /* If standard link rates are not being used,
 678                         * Read DPCD 00115h to find the edp link rate set used
 679                         */
 680                        core_link_read_dpcd(link, DP_LINK_RATE_SET,
 681                                            &link_rate_set, sizeof(link_rate_set));
 682
 683                        // edp_supported_link_rates_count = 0 for DP
 684                        if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
 685                                link->cur_link_settings.link_rate =
 686                                        link->dpcd_caps.edp_supported_link_rates[link_rate_set];
 687                                link->cur_link_settings.link_rate_set = link_rate_set;
 688                                link->cur_link_settings.use_link_rate_set = true;
 689                        }
 690                } else {
 691                        // Link Rate not found. Seamless boot may not work.
 692                        ASSERT(false);
 693                }
 694        } else {
 695                link->cur_link_settings.link_rate = link_bw_set;
 696                link->cur_link_settings.use_link_rate_set = false;
 697        }
 698        // Read DPCD 00003h to find the max down spread.
 699        core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
 700                            &max_down_spread.raw, sizeof(max_down_spread));
 701        link->cur_link_settings.link_spread =
 702                max_down_spread.bits.MAX_DOWN_SPREAD ?
 703                LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
 704}
 705
 706static bool detect_dp(struct dc_link *link,
 707                      struct display_sink_capability *sink_caps,
 708                      enum dc_detect_reason reason)
 709{
 710        struct audio_support *audio_support = &link->dc->res_pool->audio_support;
 711
 712        sink_caps->signal = link_detect_sink(link, reason);
 713        sink_caps->transaction_type =
 714                get_ddc_transaction_type(sink_caps->signal);
 715
 716        if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
 717                sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
 718                if (!detect_dp_sink_caps(link))
 719                        return false;
 720                if (is_mst_supported(link)) {
 721                        sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
 722                        link->type = dc_connection_mst_branch;
 723
 724                        dal_ddc_service_set_transaction_type(link->ddc,
 725                                                             sink_caps->transaction_type);
 726
 727#if defined(CONFIG_DRM_AMD_DC_HDCP)
 728                        /* In case of fallback to SST when topology discovery below fails
 729                         * HDCP caps will be querried again later by the upper layer (caller
 730                         * of this function). */
 731                        query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
 732#endif
 733                }
 734
 735                if (link->type != dc_connection_mst_branch &&
 736                                is_dp_branch_device(link))
 737                        /* DP SST branch */
 738                        link->type = dc_connection_sst_branch;
 739        } else {
 740                /* DP passive dongles */
 741                sink_caps->signal = dp_passive_dongle_detection(link->ddc,
 742                                                                sink_caps,
 743                                                                audio_support);
 744                link->dpcd_caps.dongle_type = sink_caps->dongle_type;
 745        }
 746
 747        return true;
 748}
 749
 750static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
 751{
 752        if (old_edid->length != new_edid->length)
 753                return false;
 754
 755        if (new_edid->length == 0)
 756                return false;
 757
 758        return (memcmp(old_edid->raw_edid,
 759                       new_edid->raw_edid, new_edid->length) == 0);
 760}
 761
 762static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
 763{
 764        /**
 765         * something is terribly wrong if time out is > 200ms. (5Hz)
 766         * 500 microseconds * 400 tries us 200 ms
 767         **/
 768        unsigned int sleep_time_in_microseconds = 500;
 769        unsigned int tries_allowed = 400;
 770        bool is_in_alt_mode;
 771        unsigned long long enter_timestamp;
 772        unsigned long long finish_timestamp;
 773        unsigned long long time_taken_in_ns;
 774        int tries_taken;
 775
 776        DC_LOGGER_INIT(link->ctx->logger);
 777
 778        if (!link->link_enc->funcs->is_in_alt_mode)
 779                return true;
 780
 781        is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
 782        DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
 783
 784        if (is_in_alt_mode)
 785                return true;
 786
 787        enter_timestamp = dm_get_timestamp(link->ctx);
 788
 789        for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
 790                udelay(sleep_time_in_microseconds);
 791                /* ask the link if alt mode is enabled, if so return ok */
 792                if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
 793                        finish_timestamp = dm_get_timestamp(link->ctx);
 794                        time_taken_in_ns =
 795                                dm_get_elapse_time_in_ns(link->ctx,
 796                                                         finish_timestamp,
 797                                                         enter_timestamp);
 798                        DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
 799                                       div_u64(time_taken_in_ns, 1000000));
 800                        return true;
 801                }
 802        }
 803        finish_timestamp = dm_get_timestamp(link->ctx);
 804        time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
 805                                                    enter_timestamp);
 806        DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
 807                       div_u64(time_taken_in_ns, 1000000));
 808        return false;
 809}
 810
 811/*
 812 * dc_link_detect() - Detect if a sink is attached to a given link
 813 *
 814 * link->local_sink is created or destroyed as needed.
 815 *
 816 * This does not create remote sinks but will trigger DM
 817 * to start MST detection if a branch is detected.
 818 */
 819static bool dc_link_detect_helper(struct dc_link *link,
 820                                  enum dc_detect_reason reason)
 821{
 822        struct dc_sink_init_data sink_init_data = { 0 };
 823        struct display_sink_capability sink_caps = { 0 };
 824        uint32_t i;
 825        bool converter_disable_audio = false;
 826        struct audio_support *aud_support = &link->dc->res_pool->audio_support;
 827        bool same_edid = false;
 828        enum dc_edid_status edid_status;
 829        struct dc_context *dc_ctx = link->ctx;
 830        struct dc_sink *sink = NULL;
 831        struct dc_sink *prev_sink = NULL;
 832        struct dpcd_caps prev_dpcd_caps;
 833        enum dc_connection_type new_connection_type = dc_connection_none;
 834        enum dc_connection_type pre_connection_type = dc_connection_none;
 835        bool perform_dp_seamless_boot = false;
 836        const uint32_t post_oui_delay = 30; // 30ms
 837
 838        DC_LOGGER_INIT(link->ctx->logger);
 839
 840        if (dc_is_virtual_signal(link->connector_signal))
 841                return false;
 842
 843        if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
 844                link->connector_signal == SIGNAL_TYPE_EDP) &&
 845                (!link->dc->config.allow_edp_hotplug_detection)) &&
 846                link->local_sink) {
 847                // need to re-write OUI and brightness in resume case
 848                if (link->connector_signal == SIGNAL_TYPE_EDP) {
 849                        dpcd_set_source_specific_data(link);
 850                        msleep(post_oui_delay);
 851                        dc_link_set_default_brightness_aux(link);
 852                        //TODO: use cached
 853                }
 854
 855                return true;
 856        }
 857
 858        if (!dc_link_detect_sink(link, &new_connection_type)) {
 859                BREAK_TO_DEBUGGER();
 860                return false;
 861        }
 862
 863        prev_sink = link->local_sink;
 864        if (prev_sink) {
 865                dc_sink_retain(prev_sink);
 866                memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
 867        }
 868
 869        link_disconnect_sink(link);
 870        if (new_connection_type != dc_connection_none) {
 871                pre_connection_type = link->type;
 872                link->type = new_connection_type;
 873                link->link_state_valid = false;
 874
 875                /* From Disconnected-to-Connected. */
 876                switch (link->connector_signal) {
 877                case SIGNAL_TYPE_HDMI_TYPE_A: {
 878                        sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 879                        if (aud_support->hdmi_audio_native)
 880                                sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
 881                        else
 882                                sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 883                        break;
 884                }
 885
 886                case SIGNAL_TYPE_DVI_SINGLE_LINK: {
 887                        sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 888                        sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
 889                        break;
 890                }
 891
 892                case SIGNAL_TYPE_DVI_DUAL_LINK: {
 893                        sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 894                        sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
 895                        break;
 896                }
 897
 898                case SIGNAL_TYPE_LVDS: {
 899                        sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
 900                        sink_caps.signal = SIGNAL_TYPE_LVDS;
 901                        break;
 902                }
 903
 904                case SIGNAL_TYPE_EDP: {
 905                        read_current_link_settings_on_detect(link);
 906
 907                        detect_edp_sink_caps(link);
 908                        read_current_link_settings_on_detect(link);
 909                        sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
 910                        sink_caps.signal = SIGNAL_TYPE_EDP;
 911                        break;
 912                }
 913
 914                case SIGNAL_TYPE_DISPLAY_PORT: {
 915                        /* wa HPD high coming too early*/
 916                        if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
 917                            link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
 918                                /* if alt mode times out, return false */
 919                                if (!wait_for_entering_dp_alt_mode(link))
 920                                        return false;
 921                        }
 922
 923                        if (!detect_dp(link, &sink_caps, reason)) {
 924                                if (prev_sink)
 925                                        dc_sink_release(prev_sink);
 926                                return false;
 927                        }
 928
 929                        if (link->type == dc_connection_mst_branch) {
 930                                LINK_INFO("link=%d, mst branch is now Connected\n",
 931                                          link->link_index);
 932                                /* Need to setup mst link_cap struct here
 933                                 * otherwise dc_link_detect() will leave mst link_cap
 934                                 * empty which leads to allocate_mst_payload() has "0"
 935                                 * pbn_per_slot value leading to exception on dc_fixpt_div()
 936                                 */
 937                                dp_verify_mst_link_cap(link);
 938
 939                                /*
 940                                 * This call will initiate MST topology discovery. Which
 941                                 * will detect MST ports and add new DRM connector DRM
 942                                 * framework. Then read EDID via remote i2c over aux. In
 943                                 * the end, will notify DRM detect result and save EDID
 944                                 * into DRM framework.
 945                                 *
 946                                 * .detect is called by .fill_modes.
 947                                 * .fill_modes is called by user mode ioctl
 948                                 * DRM_IOCTL_MODE_GETCONNECTOR.
 949                                 *
 950                                 * .get_modes is called by .fill_modes.
 951                                 *
 952                                 * call .get_modes, AMDGPU DM implementation will create
 953                                 * new dc_sink and add to dc_link. For long HPD plug
 954                                 * in/out, MST has its own handle.
 955                                 *
 956                                 * Therefore, just after dc_create, link->sink is not
 957                                 * created for MST until user mode app calls
 958                                 * DRM_IOCTL_MODE_GETCONNECTOR.
 959                                 *
 960                                 * Need check ->sink usages in case ->sink = NULL
 961                                 * TODO: s3 resume check
 962                                 */
 963
 964                                dm_helpers_dp_update_branch_info(link->ctx, link);
 965                                if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
 966                                                link, reason == DETECT_REASON_BOOT)) {
 967                                        if (prev_sink)
 968                                                dc_sink_release(prev_sink);
 969                                        return false;
 970                                } else {
 971                                        link->type = dc_connection_sst_branch;
 972                                        sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
 973                                }
 974                        }
 975
 976                        /* Active SST downstream branch device unplug*/
 977                        if (link->type == dc_connection_sst_branch &&
 978                            link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
 979                                if (prev_sink)
 980                                        /* Downstream unplug */
 981                                        dc_sink_release(prev_sink);
 982                                return true;
 983                        }
 984
 985                        /* disable audio for non DP to HDMI active sst converter */
 986                        if (link->type == dc_connection_sst_branch &&
 987                                        is_dp_active_dongle(link) &&
 988                                        (link->dpcd_caps.dongle_type !=
 989                                                        DISPLAY_DONGLE_DP_HDMI_CONVERTER))
 990                                converter_disable_audio = true;
 991
 992                        // link switch from MST to non-MST stop topology manager
 993                        if (pre_connection_type == dc_connection_mst_branch &&
 994                                        link->type != dc_connection_mst_branch)
 995                                dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
 996
 997
 998                        // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified.
 999                        if (reason == DETECT_REASON_BOOT &&
1000                                        !dc_ctx->dc->config.power_down_display_on_boot &&
1001                                        link->link_status.link_active)
1002                                perform_dp_seamless_boot = true;
1003
1004                        if (perform_dp_seamless_boot) {
1005                                read_current_link_settings_on_detect(link);
1006                                link->verified_link_cap = link->reported_link_cap;
1007                        }
1008
1009                        break;
1010                }
1011
1012                default:
1013                        DC_ERROR("Invalid connector type! signal:%d\n",
1014                                 link->connector_signal);
1015                        if (prev_sink)
1016                                dc_sink_release(prev_sink);
1017                        return false;
1018                } /* switch() */
1019
1020                if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1021                        link->dpcd_sink_count =
1022                                link->dpcd_caps.sink_count.bits.SINK_COUNT;
1023                else
1024                        link->dpcd_sink_count = 1;
1025
1026                dal_ddc_service_set_transaction_type(link->ddc,
1027                                                     sink_caps.transaction_type);
1028
1029                link->aux_mode =
1030                        dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1031
1032                sink_init_data.link = link;
1033                sink_init_data.sink_signal = sink_caps.signal;
1034
1035                sink = dc_sink_create(&sink_init_data);
1036                if (!sink) {
1037                        DC_ERROR("Failed to create sink!\n");
1038                        if (prev_sink)
1039                                dc_sink_release(prev_sink);
1040                        return false;
1041                }
1042
1043                sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1044                sink->converter_disable_audio = converter_disable_audio;
1045
1046                /* dc_sink_create returns a new reference */
1047                link->local_sink = sink;
1048
1049                edid_status = dm_helpers_read_local_edid(link->ctx,
1050                                                         link, sink);
1051
1052                switch (edid_status) {
1053                case EDID_BAD_CHECKSUM:
1054                        DC_LOG_ERROR("EDID checksum invalid.\n");
1055                        break;
1056                case EDID_NO_RESPONSE:
1057                        DC_LOG_ERROR("No EDID read.\n");
1058                        /*
1059                         * Abort detection for non-DP connectors if we have
1060                         * no EDID
1061                         *
1062                         * DP needs to report as connected if HDP is high
1063                         * even if we have no EDID in order to go to
1064                         * fail-safe mode
1065                         */
1066                        if (dc_is_hdmi_signal(link->connector_signal) ||
1067                            dc_is_dvi_signal(link->connector_signal)) {
1068                                if (prev_sink)
1069                                        dc_sink_release(prev_sink);
1070
1071                                return false;
1072                        }
1073                        break;
1074                default:
1075                        break;
1076                }
1077
1078                // Check if edid is the same
1079                if ((prev_sink) &&
1080                    (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1081                        same_edid = is_same_edid(&prev_sink->dc_edid,
1082                                                 &sink->dc_edid);
1083
1084                if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1085                        link->ctx->dc->debug.hdmi20_disable = true;
1086
1087                if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1088                    sink_caps.transaction_type ==
1089                    DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1090                        /*
1091                         * TODO debug why Dell 2413 doesn't like
1092                         *  two link trainings
1093                         */
1094#if defined(CONFIG_DRM_AMD_DC_HDCP)
1095                        query_hdcp_capability(sink->sink_signal, link);
1096#endif
1097
1098                        // verify link cap for SST non-seamless boot
1099                        if (!perform_dp_seamless_boot)
1100                                dp_verify_link_cap_with_retries(link,
1101                                                                &link->reported_link_cap,
1102                                                                LINK_TRAINING_MAX_VERIFY_RETRY);
1103                } else {
1104                        // If edid is the same, then discard new sink and revert back to original sink
1105                        if (same_edid) {
1106                                link_disconnect_remap(prev_sink, link);
1107                                sink = prev_sink;
1108                                prev_sink = NULL;
1109                        }
1110#if defined(CONFIG_DRM_AMD_DC_HDCP)
1111                        query_hdcp_capability(sink->sink_signal, link);
1112#endif
1113                }
1114
1115                /* HDMI-DVI Dongle */
1116                if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1117                    !sink->edid_caps.edid_hdmi)
1118                        sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1119
1120                /* Connectivity log: detection */
1121                for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1122                        CONN_DATA_DETECT(link,
1123                                         &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1124                                         DC_EDID_BLOCK_SIZE,
1125                                         "%s: [Block %d] ", sink->edid_caps.display_name, i);
1126                }
1127
1128                DC_LOG_DETECTION_EDID_PARSER("%s: "
1129                        "manufacturer_id = %X, "
1130                        "product_id = %X, "
1131                        "serial_number = %X, "
1132                        "manufacture_week = %d, "
1133                        "manufacture_year = %d, "
1134                        "display_name = %s, "
1135                        "speaker_flag = %d, "
1136                        "audio_mode_count = %d\n",
1137                        __func__,
1138                        sink->edid_caps.manufacturer_id,
1139                        sink->edid_caps.product_id,
1140                        sink->edid_caps.serial_number,
1141                        sink->edid_caps.manufacture_week,
1142                        sink->edid_caps.manufacture_year,
1143                        sink->edid_caps.display_name,
1144                        sink->edid_caps.speaker_flags,
1145                        sink->edid_caps.audio_mode_count);
1146
1147                for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1148                        DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1149                                "format_code = %d, "
1150                                "channel_count = %d, "
1151                                "sample_rate = %d, "
1152                                "sample_size = %d\n",
1153                                __func__,
1154                                i,
1155                                sink->edid_caps.audio_modes[i].format_code,
1156                                sink->edid_caps.audio_modes[i].channel_count,
1157                                sink->edid_caps.audio_modes[i].sample_rate,
1158                                sink->edid_caps.audio_modes[i].sample_size);
1159                }
1160        } else {
1161                /* From Connected-to-Disconnected. */
1162                if (link->type == dc_connection_mst_branch) {
1163                        LINK_INFO("link=%d, mst branch is now Disconnected\n",
1164                                  link->link_index);
1165
1166                        dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1167
1168                        link->mst_stream_alloc_table.stream_count = 0;
1169                        memset(link->mst_stream_alloc_table.stream_allocations,
1170                               0,
1171                               sizeof(link->mst_stream_alloc_table.stream_allocations));
1172                }
1173
1174                link->type = dc_connection_none;
1175                sink_caps.signal = SIGNAL_TYPE_NONE;
1176                /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
1177                 *  is not cleared. If we emulate a DP signal on this connection, it thinks
1178                 *  the dongle is still there and limits the number of modes we can emulate.
1179                 *  Clear dongle_max_pix_clk on disconnect to fix this
1180                 */
1181                link->dongle_max_pix_clk = 0;
1182        }
1183
1184        LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1185                  link->link_index, sink,
1186                  (sink_caps.signal ==
1187                   SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1188                  prev_sink, same_edid);
1189
1190        if (prev_sink)
1191                dc_sink_release(prev_sink);
1192
1193        return true;
1194}
1195
1196bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1197{
1198        const struct dc *dc = link->dc;
1199        bool ret;
1200        bool can_apply_seamless_boot = false;
1201        int i;
1202
1203        for (i = 0; i < dc->current_state->stream_count; i++) {
1204                if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
1205                        can_apply_seamless_boot = true;
1206                        break;
1207                }
1208        }
1209
1210        /* get out of low power state */
1211        if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1212                clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1213
1214        ret = dc_link_detect_helper(link, reason);
1215
1216        /* Go back to power optimized state */
1217        if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1218                clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1219
1220        return ret;
1221}
1222
1223bool dc_link_get_hpd_state(struct dc_link *dc_link)
1224{
1225        uint32_t state;
1226
1227        dal_gpio_lock_pin(dc_link->hpd_gpio);
1228        dal_gpio_get_value(dc_link->hpd_gpio, &state);
1229        dal_gpio_unlock_pin(dc_link->hpd_gpio);
1230
1231        return state;
1232}
1233
1234static enum hpd_source_id get_hpd_line(struct dc_link *link)
1235{
1236        struct gpio *hpd;
1237        enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1238
1239        hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1240                           link->ctx->gpio_service);
1241
1242        if (hpd) {
1243                switch (dal_irq_get_source(hpd)) {
1244                case DC_IRQ_SOURCE_HPD1:
1245                        hpd_id = HPD_SOURCEID1;
1246                break;
1247                case DC_IRQ_SOURCE_HPD2:
1248                        hpd_id = HPD_SOURCEID2;
1249                break;
1250                case DC_IRQ_SOURCE_HPD3:
1251                        hpd_id = HPD_SOURCEID3;
1252                break;
1253                case DC_IRQ_SOURCE_HPD4:
1254                        hpd_id = HPD_SOURCEID4;
1255                break;
1256                case DC_IRQ_SOURCE_HPD5:
1257                        hpd_id = HPD_SOURCEID5;
1258                break;
1259                case DC_IRQ_SOURCE_HPD6:
1260                        hpd_id = HPD_SOURCEID6;
1261                break;
1262                default:
1263                        BREAK_TO_DEBUGGER();
1264                break;
1265                }
1266
1267                dal_gpio_destroy_irq(&hpd);
1268        }
1269
1270        return hpd_id;
1271}
1272
1273static enum channel_id get_ddc_line(struct dc_link *link)
1274{
1275        struct ddc *ddc;
1276        enum channel_id channel = CHANNEL_ID_UNKNOWN;
1277
1278        ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1279
1280        if (ddc) {
1281                switch (dal_ddc_get_line(ddc)) {
1282                case GPIO_DDC_LINE_DDC1:
1283                        channel = CHANNEL_ID_DDC1;
1284                        break;
1285                case GPIO_DDC_LINE_DDC2:
1286                        channel = CHANNEL_ID_DDC2;
1287                        break;
1288                case GPIO_DDC_LINE_DDC3:
1289                        channel = CHANNEL_ID_DDC3;
1290                        break;
1291                case GPIO_DDC_LINE_DDC4:
1292                        channel = CHANNEL_ID_DDC4;
1293                        break;
1294                case GPIO_DDC_LINE_DDC5:
1295                        channel = CHANNEL_ID_DDC5;
1296                        break;
1297                case GPIO_DDC_LINE_DDC6:
1298                        channel = CHANNEL_ID_DDC6;
1299                        break;
1300                case GPIO_DDC_LINE_DDC_VGA:
1301                        channel = CHANNEL_ID_DDC_VGA;
1302                        break;
1303                case GPIO_DDC_LINE_I2C_PAD:
1304                        channel = CHANNEL_ID_I2C_PAD;
1305                        break;
1306                default:
1307                        BREAK_TO_DEBUGGER();
1308                        break;
1309                }
1310        }
1311
1312        return channel;
1313}
1314
1315static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1316{
1317        switch (encoder.id) {
1318        case ENCODER_ID_INTERNAL_UNIPHY:
1319                switch (encoder.enum_id) {
1320                case ENUM_ID_1:
1321                        return TRANSMITTER_UNIPHY_A;
1322                case ENUM_ID_2:
1323                        return TRANSMITTER_UNIPHY_B;
1324                default:
1325                        return TRANSMITTER_UNKNOWN;
1326                }
1327        break;
1328        case ENCODER_ID_INTERNAL_UNIPHY1:
1329                switch (encoder.enum_id) {
1330                case ENUM_ID_1:
1331                        return TRANSMITTER_UNIPHY_C;
1332                case ENUM_ID_2:
1333                        return TRANSMITTER_UNIPHY_D;
1334                default:
1335                        return TRANSMITTER_UNKNOWN;
1336                }
1337        break;
1338        case ENCODER_ID_INTERNAL_UNIPHY2:
1339                switch (encoder.enum_id) {
1340                case ENUM_ID_1:
1341                        return TRANSMITTER_UNIPHY_E;
1342                case ENUM_ID_2:
1343                        return TRANSMITTER_UNIPHY_F;
1344                default:
1345                        return TRANSMITTER_UNKNOWN;
1346                }
1347        break;
1348        case ENCODER_ID_INTERNAL_UNIPHY3:
1349                switch (encoder.enum_id) {
1350                case ENUM_ID_1:
1351                        return TRANSMITTER_UNIPHY_G;
1352                default:
1353                        return TRANSMITTER_UNKNOWN;
1354                }
1355        break;
1356        case ENCODER_ID_EXTERNAL_NUTMEG:
1357                switch (encoder.enum_id) {
1358                case ENUM_ID_1:
1359                        return TRANSMITTER_NUTMEG_CRT;
1360                default:
1361                        return TRANSMITTER_UNKNOWN;
1362                }
1363        break;
1364        case ENCODER_ID_EXTERNAL_TRAVIS:
1365                switch (encoder.enum_id) {
1366                case ENUM_ID_1:
1367                        return TRANSMITTER_TRAVIS_CRT;
1368                case ENUM_ID_2:
1369                        return TRANSMITTER_TRAVIS_LCD;
1370                default:
1371                        return TRANSMITTER_UNKNOWN;
1372                }
1373        break;
1374        default:
1375                return TRANSMITTER_UNKNOWN;
1376        }
1377}
1378
1379static bool dc_link_construct(struct dc_link *link,
1380                              const struct link_init_data *init_params)
1381{
1382        uint8_t i;
1383        struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1384        struct dc_context *dc_ctx = init_params->ctx;
1385        struct encoder_init_data enc_init_data = { 0 };
1386        struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1387        struct integrated_info *info;
1388        struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1389        const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1390        struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1391
1392        DC_LOGGER_INIT(dc_ctx->logger);
1393
1394        info = kzalloc(sizeof(*info), GFP_KERNEL);
1395        if (!info)
1396                goto create_fail;
1397
1398        link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1399        link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1400
1401        link->link_status.dpcd_caps = &link->dpcd_caps;
1402
1403        link->dc = init_params->dc;
1404        link->ctx = dc_ctx;
1405        link->link_index = init_params->link_index;
1406
1407        memset(&link->preferred_training_settings, 0,
1408               sizeof(struct dc_link_training_overrides));
1409        memset(&link->preferred_link_setting, 0,
1410               sizeof(struct dc_link_settings));
1411
1412        link->link_id =
1413                bios->funcs->get_connector_id(bios, init_params->connector_index);
1414
1415        link->ep_type = DISPLAY_ENDPOINT_PHY;
1416
1417        DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1418
1419        if (bios->funcs->get_disp_connector_caps_info) {
1420                bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1421                link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1422                DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1423        }
1424
1425        if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1426                dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1427                                     __func__, init_params->connector_index,
1428                                     link->link_id.type, OBJECT_TYPE_CONNECTOR);
1429                goto create_fail;
1430        }
1431
1432        if (link->dc->res_pool->funcs->link_init)
1433                link->dc->res_pool->funcs->link_init(link);
1434
1435        link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1436                                      link->ctx->gpio_service);
1437
1438        if (link->hpd_gpio) {
1439                dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1440                dal_gpio_unlock_pin(link->hpd_gpio);
1441                link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1442
1443                DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1444                DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1445        }
1446
1447        switch (link->link_id.id) {
1448        case CONNECTOR_ID_HDMI_TYPE_A:
1449                link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1450
1451                break;
1452        case CONNECTOR_ID_SINGLE_LINK_DVID:
1453        case CONNECTOR_ID_SINGLE_LINK_DVII:
1454                link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1455                break;
1456        case CONNECTOR_ID_DUAL_LINK_DVID:
1457        case CONNECTOR_ID_DUAL_LINK_DVII:
1458                link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1459                break;
1460        case CONNECTOR_ID_DISPLAY_PORT:
1461                link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1462
1463                if (link->hpd_gpio)
1464                        link->irq_source_hpd_rx =
1465                                        dal_irq_get_rx_source(link->hpd_gpio);
1466
1467                break;
1468        case CONNECTOR_ID_EDP:
1469                link->connector_signal = SIGNAL_TYPE_EDP;
1470
1471                if (link->hpd_gpio) {
1472                        if (!link->dc->config.allow_edp_hotplug_detection)
1473                                link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1474                        link->irq_source_hpd_rx =
1475                                        dal_irq_get_rx_source(link->hpd_gpio);
1476                }
1477
1478                break;
1479        case CONNECTOR_ID_LVDS:
1480                link->connector_signal = SIGNAL_TYPE_LVDS;
1481                break;
1482        default:
1483                DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1484                               link->link_id.id);
1485                goto create_fail;
1486        }
1487
1488        /* TODO: #DAL3 Implement id to str function.*/
1489        LINK_INFO("Connector[%d] description:"
1490                  "signal %d\n",
1491                  init_params->connector_index,
1492                  link->connector_signal);
1493
1494        ddc_service_init_data.ctx = link->ctx;
1495        ddc_service_init_data.id = link->link_id;
1496        ddc_service_init_data.link = link;
1497        link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1498
1499        if (!link->ddc) {
1500                DC_ERROR("Failed to create ddc_service!\n");
1501                goto ddc_create_fail;
1502        }
1503
1504        if (!link->ddc->ddc_pin) {
1505                DC_ERROR("Failed to get I2C info for connector!\n");
1506                goto ddc_create_fail;
1507        }
1508
1509        link->ddc_hw_inst =
1510                dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1511
1512
1513        if (link->dc->res_pool->funcs->panel_cntl_create &&
1514                (link->link_id.id == CONNECTOR_ID_EDP ||
1515                        link->link_id.id == CONNECTOR_ID_LVDS)) {
1516                panel_cntl_init_data.ctx = dc_ctx;
1517                panel_cntl_init_data.inst =
1518                        panel_cntl_init_data.ctx->dc_edp_id_count;
1519                link->panel_cntl =
1520                        link->dc->res_pool->funcs->panel_cntl_create(
1521                                                                &panel_cntl_init_data);
1522                panel_cntl_init_data.ctx->dc_edp_id_count++;
1523
1524                if (link->panel_cntl == NULL) {
1525                        DC_ERROR("Failed to create link panel_cntl!\n");
1526                        goto panel_cntl_create_fail;
1527                }
1528        }
1529
1530        enc_init_data.ctx = dc_ctx;
1531        bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1532                              &enc_init_data.encoder);
1533        enc_init_data.connector = link->link_id;
1534        enc_init_data.channel = get_ddc_line(link);
1535        enc_init_data.hpd_source = get_hpd_line(link);
1536
1537        link->hpd_src = enc_init_data.hpd_source;
1538
1539        enc_init_data.transmitter =
1540                translate_encoder_to_transmitter(enc_init_data.encoder);
1541        link->link_enc =
1542                link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1543
1544        if (!link->link_enc) {
1545                DC_ERROR("Failed to create link encoder!\n");
1546                goto link_enc_create_fail;
1547        }
1548
1549        DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1550
1551        /* Update link encoder tracking variables. These are used for the dynamic
1552         * assignment of link encoders to streams.
1553         */
1554        link->eng_id = link->link_enc->preferred_engine;
1555        link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1556        link->dc->res_pool->dig_link_enc_count++;
1557
1558        link->link_enc_hw_inst = link->link_enc->transmitter;
1559
1560        for (i = 0; i < 4; i++) {
1561                if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1562                                             link->link_id, i,
1563                                             &link->device_tag) != BP_RESULT_OK) {
1564                        DC_ERROR("Failed to find device tag!\n");
1565                        goto device_tag_fail;
1566                }
1567
1568                /* Look for device tag that matches connector signal,
1569                 * CRT for rgb, LCD for other supported signal tyes
1570                 */
1571                if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1572                                                      link->device_tag.dev_id))
1573                        continue;
1574                if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1575                    link->connector_signal != SIGNAL_TYPE_RGB)
1576                        continue;
1577                if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1578                    link->connector_signal == SIGNAL_TYPE_RGB)
1579                        continue;
1580
1581                DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1582                DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1583                DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1584                break;
1585        }
1586
1587        if (bios->integrated_info)
1588                memcpy(info, bios->integrated_info, sizeof(*info));
1589
1590        /* Look for channel mapping corresponding to connector and device tag */
1591        for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1592                struct external_display_path *path =
1593                        &info->ext_disp_conn_info.path[i];
1594
1595                if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1596                    path->device_connector_id.id == link->link_id.id &&
1597                    path->device_connector_id.type == link->link_id.type) {
1598                        if (link->device_tag.acpi_device != 0 &&
1599                            path->device_acpi_enum == link->device_tag.acpi_device) {
1600                                link->ddi_channel_mapping = path->channel_mapping;
1601                                link->chip_caps = path->caps;
1602                                DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1603                                DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1604                        } else if (path->device_tag ==
1605                                   link->device_tag.dev_id.raw_device_tag) {
1606                                link->ddi_channel_mapping = path->channel_mapping;
1607                                link->chip_caps = path->caps;
1608                                DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1609                                DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1610                        }
1611                        break;
1612                }
1613        }
1614
1615        if (bios->funcs->get_atom_dc_golden_table)
1616                bios->funcs->get_atom_dc_golden_table(bios);
1617
1618        /*
1619         * TODO check if GPIO programmed correctly
1620         *
1621         * If GPIO isn't programmed correctly HPD might not rise or drain
1622         * fast enough, leading to bounces.
1623         */
1624        program_hpd_filter(link);
1625
1626        link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1627
1628        DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1629        kfree(info);
1630        return true;
1631device_tag_fail:
1632        link->link_enc->funcs->destroy(&link->link_enc);
1633link_enc_create_fail:
1634        if (link->panel_cntl != NULL)
1635                link->panel_cntl->funcs->destroy(&link->panel_cntl);
1636panel_cntl_create_fail:
1637        dal_ddc_service_destroy(&link->ddc);
1638ddc_create_fail:
1639create_fail:
1640
1641        if (link->hpd_gpio) {
1642                dal_gpio_destroy_irq(&link->hpd_gpio);
1643                link->hpd_gpio = NULL;
1644        }
1645
1646        DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1647        kfree(info);
1648
1649        return false;
1650}
1651
1652/*******************************************************************************
1653 * Public functions
1654 ******************************************************************************/
1655struct dc_link *link_create(const struct link_init_data *init_params)
1656{
1657        struct dc_link *link =
1658                        kzalloc(sizeof(*link), GFP_KERNEL);
1659
1660        if (NULL == link)
1661                goto alloc_fail;
1662
1663        if (false == dc_link_construct(link, init_params))
1664                goto construct_fail;
1665
1666        return link;
1667
1668construct_fail:
1669        kfree(link);
1670
1671alloc_fail:
1672        return NULL;
1673}
1674
1675void link_destroy(struct dc_link **link)
1676{
1677        dc_link_destruct(*link);
1678        kfree(*link);
1679        *link = NULL;
1680}
1681
1682static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1683{
1684        struct dc_stream_state *stream = pipe_ctx->stream;
1685
1686        if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1687                struct dc_link *link = stream->link;
1688                union down_spread_ctrl old_downspread;
1689                union down_spread_ctrl new_downspread;
1690
1691                core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1692                                &old_downspread.raw, sizeof(old_downspread));
1693
1694                new_downspread.raw = old_downspread.raw;
1695
1696                new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1697                                (stream->ignore_msa_timing_param) ? 1 : 0;
1698
1699                if (new_downspread.raw != old_downspread.raw) {
1700                        core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1701                                &new_downspread.raw, sizeof(new_downspread));
1702                }
1703
1704        } else {
1705                dm_helpers_mst_enable_stream_features(stream);
1706        }
1707}
1708
1709static enum dc_status enable_link_dp(struct dc_state *state,
1710                                     struct pipe_ctx *pipe_ctx)
1711{
1712        struct dc_stream_state *stream = pipe_ctx->stream;
1713        enum dc_status status;
1714        bool skip_video_pattern;
1715        struct dc_link *link = stream->link;
1716        struct dc_link_settings link_settings = {0};
1717        bool fec_enable;
1718        int i;
1719        bool apply_seamless_boot_optimization = false;
1720        uint32_t bl_oled_enable_delay = 50; // in ms
1721        const uint32_t post_oui_delay = 30; // 30ms
1722        /* Reduce link bandwidth between failed link training attempts. */
1723        bool do_fallback = false;
1724
1725        // check for seamless boot
1726        for (i = 0; i < state->stream_count; i++) {
1727                if (state->streams[i]->apply_seamless_boot_optimization) {
1728                        apply_seamless_boot_optimization = true;
1729                        break;
1730                }
1731        }
1732
1733        /* get link settings for video mode timing */
1734        decide_link_settings(stream, &link_settings);
1735
1736        if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1737                /*in case it is not on*/
1738                link->dc->hwss.edp_power_control(link, true);
1739                link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1740        }
1741
1742        pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1743                        link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1744        if (state->clk_mgr && !apply_seamless_boot_optimization)
1745                state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1746                                                     state, false);
1747
1748        // during mode switch we do DP_SET_POWER off then on, and OUI is lost
1749        dpcd_set_source_specific_data(link);
1750        if (link->dpcd_sink_ext_caps.raw != 0)
1751                msleep(post_oui_delay);
1752
1753        skip_video_pattern = true;
1754
1755        if (link_settings.link_rate == LINK_RATE_LOW)
1756                skip_video_pattern = false;
1757
1758        if (perform_link_training_with_retries(&link_settings,
1759                                               skip_video_pattern,
1760                                               LINK_TRAINING_ATTEMPTS,
1761                                               pipe_ctx,
1762                                               pipe_ctx->stream->signal,
1763                                               do_fallback)) {
1764                link->cur_link_settings = link_settings;
1765                status = DC_OK;
1766        } else {
1767                status = DC_FAIL_DP_LINK_TRAINING;
1768        }
1769
1770        if (link->preferred_training_settings.fec_enable)
1771                fec_enable = *link->preferred_training_settings.fec_enable;
1772        else
1773                fec_enable = true;
1774
1775        dp_set_fec_enable(link, fec_enable);
1776
1777        // during mode set we do DP_SET_POWER off then on, aux writes are lost
1778        if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1779                link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1780                link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1781                dc_link_set_default_brightness_aux(link); // TODO: use cached if known
1782                if (link->dpcd_sink_ext_caps.bits.oled == 1)
1783                        msleep(bl_oled_enable_delay);
1784                dc_link_backlight_enable_aux(link, true);
1785        }
1786
1787        return status;
1788}
1789
1790static enum dc_status enable_link_edp(
1791                struct dc_state *state,
1792                struct pipe_ctx *pipe_ctx)
1793{
1794        enum dc_status status;
1795
1796        status = enable_link_dp(state, pipe_ctx);
1797
1798        return status;
1799}
1800
1801static enum dc_status enable_link_dp_mst(
1802                struct dc_state *state,
1803                struct pipe_ctx *pipe_ctx)
1804{
1805        struct dc_link *link = pipe_ctx->stream->link;
1806
1807        /* sink signal type after MST branch is MST. Multiple MST sinks
1808         * share one link. Link DP PHY is enable or training only once.
1809         */
1810        if (link->link_status.link_active)
1811                return DC_OK;
1812
1813        /* clear payload table */
1814        dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1815
1816        /* to make sure the pending down rep can be processed
1817         * before enabling the link
1818         */
1819        dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1820
1821        /* set the sink to MST mode before enabling the link */
1822        dp_enable_mst_on_sink(link, true);
1823
1824        return enable_link_dp(state, pipe_ctx);
1825}
1826
1827static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1828                enum engine_id eng_id,
1829                struct ext_hdmi_settings *settings)
1830{
1831        bool result = false;
1832        int i = 0;
1833        struct integrated_info *integrated_info =
1834                        pipe_ctx->stream->ctx->dc_bios->integrated_info;
1835
1836        if (integrated_info == NULL)
1837                return false;
1838
1839        /*
1840         * Get retimer settings from sbios for passing SI eye test for DCE11
1841         * The setting values are varied based on board revision and port id
1842         * Therefore the setting values of each ports is passed by sbios.
1843         */
1844
1845        // Check if current bios contains ext Hdmi settings
1846        if (integrated_info->gpu_cap_info & 0x20) {
1847                switch (eng_id) {
1848                case ENGINE_ID_DIGA:
1849                        settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1850                        settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1851                        settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1852                        memmove(settings->reg_settings,
1853                                        integrated_info->dp0_ext_hdmi_reg_settings,
1854                                        sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1855                        memmove(settings->reg_settings_6g,
1856                                        integrated_info->dp0_ext_hdmi_6g_reg_settings,
1857                                        sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1858                        result = true;
1859                        break;
1860                case ENGINE_ID_DIGB:
1861                        settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1862                        settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1863                        settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1864                        memmove(settings->reg_settings,
1865                                        integrated_info->dp1_ext_hdmi_reg_settings,
1866                                        sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1867                        memmove(settings->reg_settings_6g,
1868                                        integrated_info->dp1_ext_hdmi_6g_reg_settings,
1869                                        sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1870                        result = true;
1871                        break;
1872                case ENGINE_ID_DIGC:
1873                        settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1874                        settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1875                        settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1876                        memmove(settings->reg_settings,
1877                                        integrated_info->dp2_ext_hdmi_reg_settings,
1878                                        sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1879                        memmove(settings->reg_settings_6g,
1880                                        integrated_info->dp2_ext_hdmi_6g_reg_settings,
1881                                        sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1882                        result = true;
1883                        break;
1884                case ENGINE_ID_DIGD:
1885                        settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1886                        settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1887                        settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1888                        memmove(settings->reg_settings,
1889                                        integrated_info->dp3_ext_hdmi_reg_settings,
1890                                        sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1891                        memmove(settings->reg_settings_6g,
1892                                        integrated_info->dp3_ext_hdmi_6g_reg_settings,
1893                                        sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1894                        result = true;
1895                        break;
1896                default:
1897                        break;
1898                }
1899
1900                if (result == true) {
1901                        // Validate settings from bios integrated info table
1902                        if (settings->slv_addr == 0)
1903                                return false;
1904                        if (settings->reg_num > 9)
1905                                return false;
1906                        if (settings->reg_num_6g > 3)
1907                                return false;
1908
1909                        for (i = 0; i < settings->reg_num; i++) {
1910                                if (settings->reg_settings[i].i2c_reg_index > 0x20)
1911                                        return false;
1912                        }
1913
1914                        for (i = 0; i < settings->reg_num_6g; i++) {
1915                                if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1916                                        return false;
1917                        }
1918                }
1919        }
1920
1921        return result;
1922}
1923
1924static bool i2c_write(struct pipe_ctx *pipe_ctx,
1925                uint8_t address, uint8_t *buffer, uint32_t length)
1926{
1927        struct i2c_command cmd = {0};
1928        struct i2c_payload payload = {0};
1929
1930        memset(&payload, 0, sizeof(payload));
1931        memset(&cmd, 0, sizeof(cmd));
1932
1933        cmd.number_of_payloads = 1;
1934        cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1935        cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1936
1937        payload.address = address;
1938        payload.data = buffer;
1939        payload.length = length;
1940        payload.write = true;
1941        cmd.payloads = &payload;
1942
1943        if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1944                        pipe_ctx->stream->link, &cmd))
1945                return true;
1946
1947        return false;
1948}
1949
1950static void write_i2c_retimer_setting(
1951                struct pipe_ctx *pipe_ctx,
1952                bool is_vga_mode,
1953                bool is_over_340mhz,
1954                struct ext_hdmi_settings *settings)
1955{
1956        uint8_t slave_address = (settings->slv_addr >> 1);
1957        uint8_t buffer[2];
1958        const uint8_t apply_rx_tx_change = 0x4;
1959        uint8_t offset = 0xA;
1960        uint8_t value = 0;
1961        int i = 0;
1962        bool i2c_success = false;
1963        DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1964
1965        memset(&buffer, 0, sizeof(buffer));
1966
1967        /* Start Ext-Hdmi programming*/
1968
1969        for (i = 0; i < settings->reg_num; i++) {
1970                /* Apply 3G settings */
1971                if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1972
1973                        buffer[0] = settings->reg_settings[i].i2c_reg_index;
1974                        buffer[1] = settings->reg_settings[i].i2c_reg_val;
1975                        i2c_success = i2c_write(pipe_ctx, slave_address,
1976                                                buffer, sizeof(buffer));
1977                        RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1978                                offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1979                                slave_address, buffer[0], buffer[1], i2c_success?1:0);
1980
1981                        if (!i2c_success)
1982                                goto i2c_write_fail;
1983
1984                        /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
1985                         * needs to be set to 1 on every 0xA-0xC write.
1986                         */
1987                        if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1988                                settings->reg_settings[i].i2c_reg_index == 0xB ||
1989                                settings->reg_settings[i].i2c_reg_index == 0xC) {
1990
1991                                /* Query current value from offset 0xA */
1992                                if (settings->reg_settings[i].i2c_reg_index == 0xA)
1993                                        value = settings->reg_settings[i].i2c_reg_val;
1994                                else {
1995                                        i2c_success =
1996                                                dal_ddc_service_query_ddc_data(
1997                                                pipe_ctx->stream->link->ddc,
1998                                                slave_address, &offset, 1, &value, 1);
1999                                        if (!i2c_success)
2000                                                goto i2c_write_fail;
2001                                }
2002
2003                                buffer[0] = offset;
2004                                /* Set APPLY_RX_TX_CHANGE bit to 1 */
2005                                buffer[1] = value | apply_rx_tx_change;
2006                                i2c_success = i2c_write(pipe_ctx, slave_address,
2007                                                buffer, sizeof(buffer));
2008                                RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2009                                        offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2010                                        slave_address, buffer[0], buffer[1], i2c_success?1:0);
2011                                if (!i2c_success)
2012                                        goto i2c_write_fail;
2013                        }
2014                }
2015        }
2016
2017        /* Apply 3G settings */
2018        if (is_over_340mhz) {
2019                for (i = 0; i < settings->reg_num_6g; i++) {
2020                        /* Apply 3G settings */
2021                        if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2022
2023                                buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2024                                buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2025                                i2c_success = i2c_write(pipe_ctx, slave_address,
2026                                                        buffer, sizeof(buffer));
2027                                RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2028                                        offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2029                                        slave_address, buffer[0], buffer[1], i2c_success?1:0);
2030
2031                                if (!i2c_success)
2032                                        goto i2c_write_fail;
2033
2034                                /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A
2035                                 * needs to be set to 1 on every 0xA-0xC write.
2036                                 */
2037                                if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2038                                        settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2039                                        settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2040
2041                                        /* Query current value from offset 0xA */
2042                                        if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2043                                                value = settings->reg_settings_6g[i].i2c_reg_val;
2044                                        else {
2045                                                i2c_success =
2046                                                                dal_ddc_service_query_ddc_data(
2047                                                                pipe_ctx->stream->link->ddc,
2048                                                                slave_address, &offset, 1, &value, 1);
2049                                                if (!i2c_success)
2050                                                        goto i2c_write_fail;
2051                                        }
2052
2053                                        buffer[0] = offset;
2054                                        /* Set APPLY_RX_TX_CHANGE bit to 1 */
2055                                        buffer[1] = value | apply_rx_tx_change;
2056                                        i2c_success = i2c_write(pipe_ctx, slave_address,
2057                                                        buffer, sizeof(buffer));
2058                                        RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2059                                                offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2060                                                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2061                                        if (!i2c_success)
2062                                                goto i2c_write_fail;
2063                                }
2064                        }
2065                }
2066        }
2067
2068        if (is_vga_mode) {
2069                /* Program additional settings if using 640x480 resolution */
2070
2071                /* Write offset 0xFF to 0x01 */
2072                buffer[0] = 0xff;
2073                buffer[1] = 0x01;
2074                i2c_success = i2c_write(pipe_ctx, slave_address,
2075                                buffer, sizeof(buffer));
2076                RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2077                                offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2078                                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2079                if (!i2c_success)
2080                        goto i2c_write_fail;
2081
2082                /* Write offset 0x00 to 0x23 */
2083                buffer[0] = 0x00;
2084                buffer[1] = 0x23;
2085                i2c_success = i2c_write(pipe_ctx, slave_address,
2086                                buffer, sizeof(buffer));
2087                RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2088                        offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2089                        slave_address, buffer[0], buffer[1], i2c_success?1:0);
2090                if (!i2c_success)
2091                        goto i2c_write_fail;
2092
2093                /* Write offset 0xff to 0x00 */
2094                buffer[0] = 0xff;
2095                buffer[1] = 0x00;
2096                i2c_success = i2c_write(pipe_ctx, slave_address,
2097                                buffer, sizeof(buffer));
2098                RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2099                        offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2100                        slave_address, buffer[0], buffer[1], i2c_success?1:0);
2101                if (!i2c_success)
2102                        goto i2c_write_fail;
2103
2104        }
2105
2106        return;
2107
2108i2c_write_fail:
2109        DC_LOG_DEBUG("Set retimer failed");
2110}
2111
2112static void write_i2c_default_retimer_setting(
2113                struct pipe_ctx *pipe_ctx,
2114                bool is_vga_mode,
2115                bool is_over_340mhz)
2116{
2117        uint8_t slave_address = (0xBA >> 1);
2118        uint8_t buffer[2];
2119        bool i2c_success = false;
2120        DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2121
2122        memset(&buffer, 0, sizeof(buffer));
2123
2124        /* Program Slave Address for tuning single integrity */
2125        /* Write offset 0x0A to 0x13 */
2126        buffer[0] = 0x0A;
2127        buffer[1] = 0x13;
2128        i2c_success = i2c_write(pipe_ctx, slave_address,
2129                        buffer, sizeof(buffer));
2130        RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2131                offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2132                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2133        if (!i2c_success)
2134                goto i2c_write_fail;
2135
2136        /* Write offset 0x0A to 0x17 */
2137        buffer[0] = 0x0A;
2138        buffer[1] = 0x17;
2139        i2c_success = i2c_write(pipe_ctx, slave_address,
2140                        buffer, sizeof(buffer));
2141        RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2142                offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2143                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2144        if (!i2c_success)
2145                goto i2c_write_fail;
2146
2147        /* Write offset 0x0B to 0xDA or 0xD8 */
2148        buffer[0] = 0x0B;
2149        buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2150        i2c_success = i2c_write(pipe_ctx, slave_address,
2151                        buffer, sizeof(buffer));
2152        RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2153                offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2154                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2155        if (!i2c_success)
2156                goto i2c_write_fail;
2157
2158        /* Write offset 0x0A to 0x17 */
2159        buffer[0] = 0x0A;
2160        buffer[1] = 0x17;
2161        i2c_success = i2c_write(pipe_ctx, slave_address,
2162                        buffer, sizeof(buffer));
2163        RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2164                offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2165                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2166        if (!i2c_success)
2167                goto i2c_write_fail;
2168
2169        /* Write offset 0x0C to 0x1D or 0x91 */
2170        buffer[0] = 0x0C;
2171        buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2172        i2c_success = i2c_write(pipe_ctx, slave_address,
2173                        buffer, sizeof(buffer));
2174        RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2175                offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2176                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2177        if (!i2c_success)
2178                goto i2c_write_fail;
2179
2180        /* Write offset 0x0A to 0x17 */
2181        buffer[0] = 0x0A;
2182        buffer[1] = 0x17;
2183        i2c_success = i2c_write(pipe_ctx, slave_address,
2184                        buffer, sizeof(buffer));
2185        RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2186                offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2187                slave_address, buffer[0], buffer[1], i2c_success?1:0);
2188        if (!i2c_success)
2189                goto i2c_write_fail;
2190
2191
2192        if (is_vga_mode) {
2193                /* Program additional settings if using 640x480 resolution */
2194
2195                /* Write offset 0xFF to 0x01 */
2196                buffer[0] = 0xff;
2197                buffer[1] = 0x01;
2198                i2c_success = i2c_write(pipe_ctx, slave_address,
2199                                buffer, sizeof(buffer));
2200                RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2201                        offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2202                        slave_address, buffer[0], buffer[1], i2c_success?1:0);
2203                if (!i2c_success)
2204                        goto i2c_write_fail;
2205
2206                /* Write offset 0x00 to 0x23 */
2207                buffer[0] = 0x00;
2208                buffer[1] = 0x23;
2209                i2c_success = i2c_write(pipe_ctx, slave_address,
2210                                buffer, sizeof(buffer));
2211                RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2212                        offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2213                        slave_address, buffer[0], buffer[1], i2c_success?1:0);
2214                if (!i2c_success)
2215                        goto i2c_write_fail;
2216
2217                /* Write offset 0xff to 0x00 */
2218                buffer[0] = 0xff;
2219                buffer[1] = 0x00;
2220                i2c_success = i2c_write(pipe_ctx, slave_address,
2221                                buffer, sizeof(buffer));
2222                RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2223                        offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2224                        slave_address, buffer[0], buffer[1], i2c_success?1:0);
2225                if (!i2c_success)
2226                        goto i2c_write_fail;
2227        }
2228
2229        return;
2230
2231i2c_write_fail:
2232        DC_LOG_DEBUG("Set default retimer failed");
2233}
2234
2235static void write_i2c_redriver_setting(
2236                struct pipe_ctx *pipe_ctx,
2237                bool is_over_340mhz)
2238{
2239        uint8_t slave_address = (0xF0 >> 1);
2240        uint8_t buffer[16];
2241        bool i2c_success = false;
2242        DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2243
2244        memset(&buffer, 0, sizeof(buffer));
2245
2246        // Program Slave Address for tuning single integrity
2247        buffer[3] = 0x4E;
2248        buffer[4] = 0x4E;
2249        buffer[5] = 0x4E;
2250        buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2251
2252        i2c_success = i2c_write(pipe_ctx, slave_address,
2253                                        buffer, sizeof(buffer));
2254        RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2255                \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2256                offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2257                i2c_success = %d\n",
2258                slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2259
2260        if (!i2c_success)
2261                DC_LOG_DEBUG("Set redriver failed");
2262}
2263
2264static void disable_link(struct dc_link *link, enum signal_type signal)
2265{
2266        /*
2267         * TODO: implement call for dp_set_hw_test_pattern
2268         * it is needed for compliance testing
2269         */
2270
2271        /* Here we need to specify that encoder output settings
2272         * need to be calculated as for the set mode,
2273         * it will lead to querying dynamic link capabilities
2274         * which should be done before enable output
2275         */
2276
2277        if (dc_is_dp_signal(signal)) {
2278                /* SST DP, eDP */
2279                if (dc_is_dp_sst_signal(signal))
2280                        dp_disable_link_phy(link, signal);
2281                else
2282                        dp_disable_link_phy_mst(link, signal);
2283
2284                if (dc_is_dp_sst_signal(signal) ||
2285                                link->mst_stream_alloc_table.stream_count == 0) {
2286                        dp_set_fec_enable(link, false);
2287                        dp_set_fec_ready(link, false);
2288                }
2289        } else {
2290                if (signal != SIGNAL_TYPE_VIRTUAL)
2291                        link->link_enc->funcs->disable_output(link->link_enc, signal);
2292        }
2293
2294        if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2295                /* MST disable link only when no stream use the link */
2296                if (link->mst_stream_alloc_table.stream_count <= 0)
2297                        link->link_status.link_active = false;
2298        } else {
2299                link->link_status.link_active = false;
2300        }
2301}
2302
2303static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2304{
2305        struct dc_stream_state *stream = pipe_ctx->stream;
2306        struct dc_link *link = stream->link;
2307        enum dc_color_depth display_color_depth;
2308        enum engine_id eng_id;
2309        struct ext_hdmi_settings settings = {0};
2310        bool is_over_340mhz = false;
2311        bool is_vga_mode = (stream->timing.h_addressable == 640)
2312                        && (stream->timing.v_addressable == 480);
2313
2314        if (stream->phy_pix_clk == 0)
2315                stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2316        if (stream->phy_pix_clk > 340000)
2317                is_over_340mhz = true;
2318
2319        if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2320                unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2321                                EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2322                if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2323                        /* DP159, Retimer settings */
2324                        eng_id = pipe_ctx->stream_res.stream_enc->id;
2325
2326                        if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2327                                write_i2c_retimer_setting(pipe_ctx,
2328                                                is_vga_mode, is_over_340mhz, &settings);
2329                        } else {
2330                                write_i2c_default_retimer_setting(pipe_ctx,
2331                                                is_vga_mode, is_over_340mhz);
2332                        }
2333                } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2334                        /* PI3EQX1204, Redriver settings */
2335                        write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2336                }
2337        }
2338
2339        if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2340                dal_ddc_service_write_scdc_data(
2341                        stream->link->ddc,
2342                        stream->phy_pix_clk,
2343                        stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2344
2345        memset(&stream->link->cur_link_settings, 0,
2346                        sizeof(struct dc_link_settings));
2347
2348        display_color_depth = stream->timing.display_color_depth;
2349        if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2350                display_color_depth = COLOR_DEPTH_888;
2351
2352        link->link_enc->funcs->enable_tmds_output(
2353                        link->link_enc,
2354                        pipe_ctx->clock_source->id,
2355                        display_color_depth,
2356                        pipe_ctx->stream->signal,
2357                        stream->phy_pix_clk);
2358
2359        if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2360                dal_ddc_service_read_scdc_data(link->ddc);
2361}
2362
2363static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2364{
2365        struct dc_stream_state *stream = pipe_ctx->stream;
2366        struct dc_link *link = stream->link;
2367
2368        if (stream->phy_pix_clk == 0)
2369                stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2370
2371        memset(&stream->link->cur_link_settings, 0,
2372                        sizeof(struct dc_link_settings));
2373
2374        link->link_enc->funcs->enable_lvds_output(
2375                        link->link_enc,
2376                        pipe_ctx->clock_source->id,
2377                        stream->phy_pix_clk);
2378
2379}
2380
2381/****************************enable_link***********************************/
2382static enum dc_status enable_link(
2383                struct dc_state *state,
2384                struct pipe_ctx *pipe_ctx)
2385{
2386        enum dc_status status = DC_ERROR_UNEXPECTED;
2387        struct dc_stream_state *stream = pipe_ctx->stream;
2388        struct dc_link *link = stream->link;
2389
2390        /* There's some scenarios where driver is unloaded with display
2391         * still enabled. When driver is reloaded, it may cause a display
2392         * to not light up if there is a mismatch between old and new
2393         * link settings. Need to call disable first before enabling at
2394         * new link settings.
2395         */
2396        if (link->link_status.link_active) {
2397                disable_link(link, pipe_ctx->stream->signal);
2398        }
2399
2400        switch (pipe_ctx->stream->signal) {
2401        case SIGNAL_TYPE_DISPLAY_PORT:
2402                status = enable_link_dp(state, pipe_ctx);
2403                break;
2404        case SIGNAL_TYPE_EDP:
2405                status = enable_link_edp(state, pipe_ctx);
2406                break;
2407        case SIGNAL_TYPE_DISPLAY_PORT_MST:
2408                status = enable_link_dp_mst(state, pipe_ctx);
2409                msleep(200);
2410                break;
2411        case SIGNAL_TYPE_DVI_SINGLE_LINK:
2412        case SIGNAL_TYPE_DVI_DUAL_LINK:
2413        case SIGNAL_TYPE_HDMI_TYPE_A:
2414                enable_link_hdmi(pipe_ctx);
2415                status = DC_OK;
2416                break;
2417        case SIGNAL_TYPE_LVDS:
2418                enable_link_lvds(pipe_ctx);
2419                status = DC_OK;
2420                break;
2421        case SIGNAL_TYPE_VIRTUAL:
2422                status = DC_OK;
2423                break;
2424        default:
2425                break;
2426        }
2427
2428        if (status == DC_OK)
2429                pipe_ctx->stream->link->link_status.link_active = true;
2430
2431        return status;
2432}
2433
2434static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2435{
2436
2437        uint32_t pxl_clk = timing->pix_clk_100hz;
2438
2439        if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2440                pxl_clk /= 2;
2441        else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2442                pxl_clk = pxl_clk * 2 / 3;
2443
2444        if (timing->display_color_depth == COLOR_DEPTH_101010)
2445                pxl_clk = pxl_clk * 10 / 8;
2446        else if (timing->display_color_depth == COLOR_DEPTH_121212)
2447                pxl_clk = pxl_clk * 12 / 8;
2448
2449        return pxl_clk;
2450}
2451
2452static bool dp_active_dongle_validate_timing(
2453                const struct dc_crtc_timing *timing,
2454                const struct dpcd_caps *dpcd_caps)
2455{
2456        const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2457
2458        switch (dpcd_caps->dongle_type) {
2459        case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2460        case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2461        case DISPLAY_DONGLE_DP_DVI_DONGLE:
2462                if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2463                        return true;
2464                else
2465                        return false;
2466        default:
2467                break;
2468        }
2469
2470        if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2471                dongle_caps->extendedCapValid == false)
2472                return true;
2473
2474        /* Check Pixel Encoding */
2475        switch (timing->pixel_encoding) {
2476        case PIXEL_ENCODING_RGB:
2477        case PIXEL_ENCODING_YCBCR444:
2478                break;
2479        case PIXEL_ENCODING_YCBCR422:
2480                if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2481                        return false;
2482                break;
2483        case PIXEL_ENCODING_YCBCR420:
2484                if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2485                        return false;
2486                break;
2487        default:
2488                /* Invalid Pixel Encoding*/
2489                return false;
2490        }
2491
2492        switch (timing->display_color_depth) {
2493        case COLOR_DEPTH_666:
2494        case COLOR_DEPTH_888:
2495                /*888 and 666 should always be supported*/
2496                break;
2497        case COLOR_DEPTH_101010:
2498                if (dongle_caps->dp_hdmi_max_bpc < 10)
2499                        return false;
2500                break;
2501        case COLOR_DEPTH_121212:
2502                if (dongle_caps->dp_hdmi_max_bpc < 12)
2503                        return false;
2504                break;
2505        case COLOR_DEPTH_141414:
2506        case COLOR_DEPTH_161616:
2507        default:
2508                /* These color depths are currently not supported */
2509                return false;
2510        }
2511
2512        if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2513                return false;
2514
2515        return true;
2516}
2517
2518enum dc_status dc_link_validate_mode_timing(
2519                const struct dc_stream_state *stream,
2520                struct dc_link *link,
2521                const struct dc_crtc_timing *timing)
2522{
2523        uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2524        struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2525
2526        /* A hack to avoid failing any modes for EDID override feature on
2527         * topology change such as lower quality cable for DP or different dongle
2528         */
2529        if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2530                return DC_OK;
2531
2532        /* Passive Dongle */
2533        if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2534                return DC_EXCEED_DONGLE_CAP;
2535
2536        /* Active Dongle*/
2537        if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2538                return DC_EXCEED_DONGLE_CAP;
2539
2540        switch (stream->signal) {
2541        case SIGNAL_TYPE_EDP:
2542        case SIGNAL_TYPE_DISPLAY_PORT:
2543                if (!dp_validate_mode_timing(
2544                                link,
2545                                timing))
2546                        return DC_NO_DP_LINK_BANDWIDTH;
2547                break;
2548
2549        default:
2550                break;
2551        }
2552
2553        return DC_OK;
2554}
2555
2556static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2557{
2558        int i;
2559        struct dc *dc = NULL;
2560        struct abm *abm = NULL;
2561
2562        if (!link || !link->ctx)
2563                return NULL;
2564
2565        dc = link->ctx->dc;
2566
2567        for (i = 0; i < MAX_PIPES; i++) {
2568                struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2569                struct dc_stream_state *stream = pipe_ctx.stream;
2570
2571                if (stream && stream->link == link) {
2572                        abm = pipe_ctx.stream_res.abm;
2573                        break;
2574                }
2575        }
2576        return abm;
2577}
2578
2579int dc_link_get_backlight_level(const struct dc_link *link)
2580{
2581
2582        struct abm *abm = get_abm_from_stream_res(link);
2583
2584        if (abm == NULL || abm->funcs->get_current_backlight == NULL)
2585                return DC_ERROR_UNEXPECTED;
2586
2587        return (int) abm->funcs->get_current_backlight(abm);
2588}
2589
2590int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2591{
2592        struct abm *abm = get_abm_from_stream_res(link);
2593
2594        if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2595                return DC_ERROR_UNEXPECTED;
2596
2597        return (int) abm->funcs->get_target_backlight(abm);
2598}
2599
2600static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2601{
2602        int i;
2603        struct dc *dc = link->ctx->dc;
2604        struct pipe_ctx *pipe_ctx = NULL;
2605
2606        for (i = 0; i < MAX_PIPES; i++) {
2607                if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2608                        if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2609                                pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2610                                break;
2611                        }
2612                }
2613        }
2614
2615        return pipe_ctx;
2616}
2617
2618bool dc_link_set_backlight_level(const struct dc_link *link,
2619                uint32_t backlight_pwm_u16_16,
2620                uint32_t frame_ramp)
2621{
2622        struct dc  *dc = link->ctx->dc;
2623
2624        DC_LOGGER_INIT(link->ctx->logger);
2625        DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2626                        backlight_pwm_u16_16, backlight_pwm_u16_16);
2627
2628        if (dc_is_embedded_signal(link->connector_signal)) {
2629                struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2630
2631                if (pipe_ctx) {
2632                        /* Disable brightness ramping when the display is blanked
2633                         * as it can hang the DMCU
2634                         */
2635                        if (pipe_ctx->plane_state == NULL)
2636                                frame_ramp = 0;
2637                } else {
2638                        return false;
2639                }
2640
2641                dc->hwss.set_backlight_level(
2642                                pipe_ctx,
2643                                backlight_pwm_u16_16,
2644                                frame_ramp);
2645        }
2646        return true;
2647}
2648
2649bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
2650                bool wait, bool force_static)
2651{
2652        struct dc  *dc = link->ctx->dc;
2653        struct dmcu *dmcu = dc->res_pool->dmcu;
2654        struct dmub_psr *psr = dc->res_pool->psr;
2655        unsigned int panel_inst;
2656
2657        if (psr == NULL && force_static)
2658                return false;
2659
2660        if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2661                return false;
2662
2663        link->psr_settings.psr_allow_active = allow_active;
2664#if defined(CONFIG_DRM_AMD_DC_DCN)
2665        if (!allow_active)
2666                dc_z10_restore(dc);
2667#endif
2668
2669        if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2670                if (force_static && psr->funcs->psr_force_static)
2671                        psr->funcs->psr_force_static(psr, panel_inst);
2672                psr->funcs->psr_enable(psr, allow_active, wait, panel_inst);
2673        } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2674                dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2675        else
2676                return false;
2677
2678        return true;
2679}
2680
2681bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2682{
2683        struct dc  *dc = link->ctx->dc;
2684        struct dmcu *dmcu = dc->res_pool->dmcu;
2685        struct dmub_psr *psr = dc->res_pool->psr;
2686        unsigned int panel_inst;
2687
2688        if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2689                return false;
2690
2691        if (psr != NULL && link->psr_settings.psr_feature_enabled)
2692                psr->funcs->psr_get_state(psr, state, panel_inst);
2693        else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2694                dmcu->funcs->get_psr_state(dmcu, state);
2695
2696        return true;
2697}
2698
2699static inline enum physical_phy_id
2700transmitter_to_phy_id(enum transmitter transmitter_value)
2701{
2702        switch (transmitter_value) {
2703        case TRANSMITTER_UNIPHY_A:
2704                return PHYLD_0;
2705        case TRANSMITTER_UNIPHY_B:
2706                return PHYLD_1;
2707        case TRANSMITTER_UNIPHY_C:
2708                return PHYLD_2;
2709        case TRANSMITTER_UNIPHY_D:
2710                return PHYLD_3;
2711        case TRANSMITTER_UNIPHY_E:
2712                return PHYLD_4;
2713        case TRANSMITTER_UNIPHY_F:
2714                return PHYLD_5;
2715        case TRANSMITTER_NUTMEG_CRT:
2716                return PHYLD_6;
2717        case TRANSMITTER_TRAVIS_CRT:
2718                return PHYLD_7;
2719        case TRANSMITTER_TRAVIS_LCD:
2720                return PHYLD_8;
2721        case TRANSMITTER_UNIPHY_G:
2722                return PHYLD_9;
2723        case TRANSMITTER_COUNT:
2724                return PHYLD_COUNT;
2725        case TRANSMITTER_UNKNOWN:
2726                return PHYLD_UNKNOWN;
2727        default:
2728                WARN_ONCE(1, "Unknown transmitter value %d\n",
2729                          transmitter_value);
2730                return PHYLD_UNKNOWN;
2731        }
2732}
2733
2734bool dc_link_setup_psr(struct dc_link *link,
2735                const struct dc_stream_state *stream, struct psr_config *psr_config,
2736                struct psr_context *psr_context)
2737{
2738        struct dc *dc;
2739        struct dmcu *dmcu;
2740        struct dmub_psr *psr;
2741        int i;
2742        unsigned int panel_inst;
2743        /* updateSinkPsrDpcdConfig*/
2744        union dpcd_psr_configuration psr_configuration;
2745
2746        psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2747
2748        if (!link)
2749                return false;
2750
2751        dc = link->ctx->dc;
2752        dmcu = dc->res_pool->dmcu;
2753        psr = dc->res_pool->psr;
2754
2755        if (!dmcu && !psr)
2756                return false;
2757
2758        if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2759                return false;
2760
2761
2762        memset(&psr_configuration, 0, sizeof(psr_configuration));
2763
2764        psr_configuration.bits.ENABLE                    = 1;
2765        psr_configuration.bits.CRC_VERIFICATION          = 1;
2766        psr_configuration.bits.FRAME_CAPTURE_INDICATION  =
2767                        psr_config->psr_frame_capture_indication_req;
2768
2769        /* Check for PSR v2*/
2770        if (psr_config->psr_version == 0x2) {
2771                /* For PSR v2 selective update.
2772                 * Indicates whether sink should start capturing
2773                 * immediately following active scan line,
2774                 * or starting with the 2nd active scan line.
2775                 */
2776                psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2777                /*For PSR v2, determines whether Sink should generate
2778                 * IRQ_HPD when CRC mismatch is detected.
2779                 */
2780                psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR    = 1;
2781        }
2782
2783        dm_helpers_dp_write_dpcd(
2784                link->ctx,
2785                link,
2786                368,
2787                &psr_configuration.raw,
2788                sizeof(psr_configuration.raw));
2789
2790        psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2791        psr_context->transmitterId = link->link_enc->transmitter;
2792        psr_context->engineId = link->link_enc->preferred_engine;
2793
2794        for (i = 0; i < MAX_PIPES; i++) {
2795                if (dc->current_state->res_ctx.pipe_ctx[i].stream
2796                                == stream) {
2797                        /* dmcu -1 for all controller id values,
2798                         * therefore +1 here
2799                         */
2800                        psr_context->controllerId =
2801                                dc->current_state->res_ctx.
2802                                pipe_ctx[i].stream_res.tg->inst + 1;
2803                        break;
2804                }
2805        }
2806
2807        /* Hardcoded for now.  Can be Pcie or Uniphy (or Unknown)*/
2808        psr_context->phyType = PHY_TYPE_UNIPHY;
2809        /*PhyId is associated with the transmitter id*/
2810        psr_context->smuPhyId =
2811                transmitter_to_phy_id(link->link_enc->transmitter);
2812
2813        psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2814        psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2815                                        timing.pix_clk_100hz * 100),
2816                                        stream->timing.v_total),
2817                                        stream->timing.h_total);
2818
2819        psr_context->psrSupportedDisplayConfig = true;
2820        psr_context->psrExitLinkTrainingRequired =
2821                psr_config->psr_exit_link_training_required;
2822        psr_context->sdpTransmitLineNumDeadline =
2823                psr_config->psr_sdp_transmit_line_num_deadline;
2824        psr_context->psrFrameCaptureIndicationReq =
2825                psr_config->psr_frame_capture_indication_req;
2826
2827        psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */
2828
2829        psr_context->numberOfControllers =
2830                        link->dc->res_pool->timing_generator_count;
2831
2832        psr_context->rfb_update_auto_en = true;
2833
2834        /* 2 frames before enter PSR. */
2835        psr_context->timehyst_frames = 2;
2836        /* half a frame
2837         * (units in 100 lines, i.e. a value of 1 represents 100 lines)
2838         */
2839        psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2840        psr_context->aux_repeats = 10;
2841
2842        psr_context->psr_level.u32all = 0;
2843
2844        /*skip power down the single pipe since it blocks the cstate*/
2845#if defined(CONFIG_DRM_AMD_DC_DCN)
2846        if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
2847                psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2848                if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
2849                        psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
2850        }
2851#else
2852        if (link->ctx->asic_id.chip_family >= FAMILY_RV)
2853                psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2854#endif
2855
2856        /* SMU will perform additional powerdown sequence.
2857         * For unsupported ASICs, set psr_level flag to skip PSR
2858         *  static screen notification to SMU.
2859         *  (Always set for DAL2, did not check ASIC)
2860         */
2861        psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2862        psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
2863
2864        /* Complete PSR entry before aborting to prevent intermittent
2865         * freezes on certain eDPs
2866         */
2867        psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2868
2869        /* Controls additional delay after remote frame capture before
2870         * continuing power down, default = 0
2871         */
2872        psr_context->frame_delay = 0;
2873
2874        if (psr)
2875                link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
2876                        link, psr_context, panel_inst);
2877        else
2878                link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2879
2880        /* psr_enabled == 0 indicates setup_psr did not succeed, but this
2881         * should not happen since firmware should be running at this point
2882         */
2883        if (link->psr_settings.psr_feature_enabled == 0)
2884                ASSERT(0);
2885
2886        return true;
2887
2888}
2889
2890void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
2891{
2892        struct dc  *dc = link->ctx->dc;
2893        struct dmub_psr *psr = dc->res_pool->psr;
2894        unsigned int panel_inst;
2895
2896        if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2897                return;
2898
2899        /* PSR residency measurements only supported on DMCUB */
2900        if (psr != NULL && link->psr_settings.psr_feature_enabled)
2901                psr->funcs->psr_get_residency(psr, residency, panel_inst);
2902        else
2903                *residency = 0;
2904}
2905
2906const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2907{
2908        return &link->link_status;
2909}
2910
2911void core_link_resume(struct dc_link *link)
2912{
2913        if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2914                program_hpd_filter(link);
2915}
2916
2917static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2918{
2919        struct fixed31_32 mbytes_per_sec;
2920        uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2921                        &stream->link->cur_link_settings);
2922        link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
2923
2924        mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2925
2926        return dc_fixpt_div_int(mbytes_per_sec, 54);
2927}
2928
2929static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
2930{
2931        struct fixed31_32 peak_kbps;
2932        uint32_t numerator = 0;
2933        uint32_t denominator = 1;
2934
2935        /*
2936         * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
2937         * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
2938         * common multiplier to render an integer PBN for all link rate/lane
2939         * counts combinations
2940         * calculate
2941         * peak_kbps *= (1006/1000)
2942         * peak_kbps *= (64/54)
2943         * peak_kbps *= 8    convert to bytes
2944         */
2945
2946        numerator = 64 * PEAK_FACTOR_X1000;
2947        denominator = 54 * 8 * 1000 * 1000;
2948        kbps *= numerator;
2949        peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2950
2951        return peak_kbps;
2952}
2953
2954static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2955{
2956        uint64_t kbps;
2957
2958        kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2959        return get_pbn_from_bw_in_kbps(kbps);
2960}
2961
2962static void update_mst_stream_alloc_table(
2963        struct dc_link *link,
2964        struct stream_encoder *stream_enc,
2965        const struct dp_mst_stream_allocation_table *proposed_table)
2966{
2967        struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2968                        { 0 } };
2969        struct link_mst_stream_allocation *dc_alloc;
2970
2971        int i;
2972        int j;
2973
2974        /* if DRM proposed_table has more than one new payload */
2975        ASSERT(proposed_table->stream_count -
2976                        link->mst_stream_alloc_table.stream_count < 2);
2977
2978        /* copy proposed_table to link, add stream encoder */
2979        for (i = 0; i < proposed_table->stream_count; i++) {
2980
2981                for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2982                        dc_alloc =
2983                        &link->mst_stream_alloc_table.stream_allocations[j];
2984
2985                        if (dc_alloc->vcp_id ==
2986                                proposed_table->stream_allocations[i].vcp_id) {
2987
2988                                work_table[i] = *dc_alloc;
2989                                work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
2990                                break; /* exit j loop */
2991                        }
2992                }
2993
2994                /* new vcp_id */
2995                if (j == link->mst_stream_alloc_table.stream_count) {
2996                        work_table[i].vcp_id =
2997                                proposed_table->stream_allocations[i].vcp_id;
2998                        work_table[i].slot_count =
2999                                proposed_table->stream_allocations[i].slot_count;
3000                        work_table[i].stream_enc = stream_enc;
3001                }
3002        }
3003
3004        /* update link->mst_stream_alloc_table with work_table */
3005        link->mst_stream_alloc_table.stream_count =
3006                        proposed_table->stream_count;
3007        for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3008                link->mst_stream_alloc_table.stream_allocations[i] =
3009                                work_table[i];
3010}
3011
3012/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table
3013 * because stream_encoder is not exposed to dm
3014 */
3015enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3016{
3017        struct dc_stream_state *stream = pipe_ctx->stream;
3018        struct dc_link *link = stream->link;
3019        struct link_encoder *link_encoder = link->link_enc;
3020        struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3021        struct dp_mst_stream_allocation_table proposed_table = {0};
3022        struct fixed31_32 avg_time_slots_per_mtp;
3023        struct fixed31_32 pbn;
3024        struct fixed31_32 pbn_per_slot;
3025        uint8_t i;
3026        enum act_return_status ret;
3027        DC_LOGGER_INIT(link->ctx->logger);
3028
3029        /* enable_link_dp_mst already check link->enabled_stream_count
3030         * and stream is in link->stream[]. This is called during set mode,
3031         * stream_enc is available.
3032         */
3033
3034        /* get calculate VC payload for stream: stream_alloc */
3035        if (dm_helpers_dp_mst_write_payload_allocation_table(
3036                stream->ctx,
3037                stream,
3038                &proposed_table,
3039                true)) {
3040                update_mst_stream_alloc_table(
3041                                        link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3042        }
3043        else
3044                DC_LOG_WARNING("Failed to update"
3045                                "MST allocation table for"
3046                                "pipe idx:%d\n",
3047                                pipe_ctx->pipe_idx);
3048
3049        DC_LOG_MST("%s  "
3050                        "stream_count: %d: \n ",
3051                        __func__,
3052                        link->mst_stream_alloc_table.stream_count);
3053
3054        for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3055                DC_LOG_MST("stream_enc[%d]: %p      "
3056                "stream[%d].vcp_id: %d      "
3057                "stream[%d].slot_count: %d\n",
3058                i,
3059                (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3060                i,
3061                link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3062                i,
3063                link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3064        }
3065
3066        ASSERT(proposed_table.stream_count > 0);
3067
3068        /* program DP source TX for payload */
3069        link_encoder->funcs->update_mst_stream_allocation_table(
3070                link_encoder,
3071                &link->mst_stream_alloc_table);
3072
3073        /* send down message */
3074        ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3075                        stream->ctx,
3076                        stream);
3077
3078        if (ret != ACT_LINK_LOST) {
3079                dm_helpers_dp_mst_send_payload_allocation(
3080                                stream->ctx,
3081                                stream,
3082                                true);
3083        }
3084
3085        /* slot X.Y for only current stream */
3086        pbn_per_slot = get_pbn_per_slot(stream);
3087        if (pbn_per_slot.value == 0) {
3088                DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3089                return DC_UNSUPPORTED_VALUE;
3090        }
3091        pbn = get_pbn_from_timing(pipe_ctx);
3092        avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3093
3094        stream_encoder->funcs->set_throttled_vcp_size(
3095                stream_encoder,
3096                avg_time_slots_per_mtp);
3097
3098        return DC_OK;
3099
3100}
3101
3102static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3103{
3104        struct dc_stream_state *stream = pipe_ctx->stream;
3105        struct dc_link *link = stream->link;
3106        struct link_encoder *link_encoder = link->link_enc;
3107        struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3108        struct dp_mst_stream_allocation_table proposed_table = {0};
3109        struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3110        uint8_t i;
3111        bool mst_mode = (link->type == dc_connection_mst_branch);
3112        DC_LOGGER_INIT(link->ctx->logger);
3113
3114        /* deallocate_mst_payload is called before disable link. When mode or
3115         * disable/enable monitor, new stream is created which is not in link
3116         * stream[] yet. For this, payload is not allocated yet, so de-alloc
3117         * should not done. For new mode set, map_resources will get engine
3118         * for new stream, so stream_enc->id should be validated until here.
3119         */
3120
3121        /* slot X.Y */
3122        stream_encoder->funcs->set_throttled_vcp_size(
3123                stream_encoder,
3124                avg_time_slots_per_mtp);
3125
3126        /* TODO: which component is responsible for remove payload table? */
3127        if (mst_mode) {
3128                if (dm_helpers_dp_mst_write_payload_allocation_table(
3129                                stream->ctx,
3130                                stream,
3131                                &proposed_table,
3132                                false)) {
3133
3134                        update_mst_stream_alloc_table(
3135                                link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3136                }
3137                else {
3138                                DC_LOG_WARNING("Failed to update"
3139                                                "MST allocation table for"
3140                                                "pipe idx:%d\n",
3141                                                pipe_ctx->pipe_idx);
3142                }
3143        }
3144
3145        DC_LOG_MST("%s"
3146                        "stream_count: %d: ",
3147                        __func__,
3148                        link->mst_stream_alloc_table.stream_count);
3149
3150        for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3151                DC_LOG_MST("stream_enc[%d]: %p      "
3152                "stream[%d].vcp_id: %d      "
3153                "stream[%d].slot_count: %d\n",
3154                i,
3155                (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3156                i,
3157                link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3158                i,
3159                link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3160        }
3161
3162        link_encoder->funcs->update_mst_stream_allocation_table(
3163                link_encoder,
3164                &link->mst_stream_alloc_table);
3165
3166        if (mst_mode) {
3167                dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3168                        stream->ctx,
3169                        stream);
3170
3171                dm_helpers_dp_mst_send_payload_allocation(
3172                        stream->ctx,
3173                        stream,
3174                        false);
3175        }
3176
3177        return DC_OK;
3178}
3179
3180
3181#if defined(CONFIG_DRM_AMD_DC_HDCP)
3182static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3183{
3184        struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3185        if (cp_psp && cp_psp->funcs.update_stream_config) {
3186                struct cp_psp_stream_config config = {0};
3187                enum dp_panel_mode panel_mode =
3188                                dp_get_panel_mode(pipe_ctx->stream->link);
3189
3190                config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3191                /*stream_enc_inst*/
3192                config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3193                config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3194#if defined(CONFIG_DRM_AMD_DC_DCN)
3195                config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3196                config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3197                config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3198#endif
3199                config.dpms_off = dpms_off;
3200                config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3201                config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
3202                config.mst_enabled = (pipe_ctx->stream->signal ==
3203                                SIGNAL_TYPE_DISPLAY_PORT_MST);
3204                cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3205        }
3206}
3207#endif
3208
3209void core_link_enable_stream(
3210                struct dc_state *state,
3211                struct pipe_ctx *pipe_ctx)
3212{
3213        struct dc *dc = pipe_ctx->stream->ctx->dc;
3214        struct dc_stream_state *stream = pipe_ctx->stream;
3215        enum dc_status status;
3216#if defined(CONFIG_DRM_AMD_DC_DCN)
3217        enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
3218#endif
3219        DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3220
3221        if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3222                        dc_is_virtual_signal(pipe_ctx->stream->signal))
3223                return;
3224
3225        if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3226                stream->link->link_enc->funcs->setup(
3227                        stream->link->link_enc,
3228                        pipe_ctx->stream->signal);
3229                pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3230                        pipe_ctx->stream_res.stream_enc,
3231                        pipe_ctx->stream_res.tg->inst,
3232                        stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3233        }
3234
3235        if (dc_is_dp_signal(pipe_ctx->stream->signal))
3236                pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3237                        pipe_ctx->stream_res.stream_enc,
3238                        &stream->timing,
3239                        stream->output_color_space,
3240                        stream->use_vsc_sdp_for_colorimetry,
3241                        stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3242
3243        if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3244                pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3245                        pipe_ctx->stream_res.stream_enc,
3246                        &stream->timing,
3247                        stream->phy_pix_clk,
3248                        pipe_ctx->stream_res.audio != NULL);
3249
3250        pipe_ctx->stream->link->link_state_valid = true;
3251
3252#if defined(CONFIG_DRM_AMD_DC_DCN)
3253        if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3254                pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
3255#endif
3256
3257        if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3258                pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3259                        pipe_ctx->stream_res.stream_enc,
3260                        &stream->timing,
3261                        (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3262                        true : false);
3263
3264        if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3265                pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3266                        pipe_ctx->stream_res.stream_enc,
3267                        &stream->timing);
3268
3269        if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3270                bool apply_edp_fast_boot_optimization =
3271                        pipe_ctx->stream->apply_edp_fast_boot_optimization;
3272
3273                pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3274
3275                resource_build_info_frame(pipe_ctx);
3276                dc->hwss.update_info_frame(pipe_ctx);
3277
3278                /* Do not touch link on seamless boot optimization. */
3279                if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3280                        pipe_ctx->stream->dpms_off = false;
3281
3282                        /* Still enable stream features & audio on seamless boot for DP external displays */
3283                        if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
3284                                enable_stream_features(pipe_ctx);
3285                                if (pipe_ctx->stream_res.audio != NULL) {
3286                                        pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
3287                                        dc->hwss.enable_audio_stream(pipe_ctx);
3288                                }
3289                        }
3290
3291#if defined(CONFIG_DRM_AMD_DC_HDCP)
3292                        update_psp_stream_config(pipe_ctx, false);
3293#endif
3294                        return;
3295                }
3296
3297                /* eDP lit up by bios already, no need to enable again. */
3298                if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3299                                        apply_edp_fast_boot_optimization &&
3300                                        !pipe_ctx->stream->timing.flags.DSC) {
3301                        pipe_ctx->stream->dpms_off = false;
3302#if defined(CONFIG_DRM_AMD_DC_HDCP)
3303                        update_psp_stream_config(pipe_ctx, false);
3304#endif
3305                        return;
3306                }
3307
3308                if (pipe_ctx->stream->dpms_off)
3309                        return;
3310
3311                /* Have to setup DSC before DIG FE and BE are connected (which happens before the
3312                 * link training). This is to make sure the bandwidth sent to DIG BE won't be
3313                 * bigger than what the link and/or DIG BE can handle. VBID[6]/CompressedStream_flag
3314                 * will be automatically set at a later time when the video is enabled
3315                 * (DP_VID_STREAM_EN = 1).
3316                 */
3317                if (pipe_ctx->stream->timing.flags.DSC) {
3318                        if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3319                                        dc_is_virtual_signal(pipe_ctx->stream->signal))
3320                                dp_set_dsc_enable(pipe_ctx, true);
3321                }
3322
3323                status = enable_link(state, pipe_ctx);
3324
3325                if (status != DC_OK) {
3326                        DC_LOG_WARNING("enabling link %u failed: %d\n",
3327                        pipe_ctx->stream->link->link_index,
3328                        status);
3329
3330                        /* Abort stream enable *unless* the failure was due to
3331                         * DP link training - some DP monitors will recover and
3332                         * show the stream anyway. But MST displays can't proceed
3333                         * without link training.
3334                         */
3335                        if (status != DC_FAIL_DP_LINK_TRAINING ||
3336                                        pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3337                                BREAK_TO_DEBUGGER();
3338                                return;
3339                        }
3340                }
3341
3342                /* turn off otg test pattern if enable */
3343                if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3344                        pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3345                                        CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3346                                        COLOR_DEPTH_UNDEFINED);
3347
3348                /* This second call is needed to reconfigure the DIG
3349                 * as a workaround for the incorrect value being applied
3350                 * from transmitter control.
3351                 */
3352                if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3353                        stream->link->link_enc->funcs->setup(
3354                                stream->link->link_enc,
3355                                pipe_ctx->stream->signal);
3356
3357                dc->hwss.enable_stream(pipe_ctx);
3358
3359                /* Set DPS PPS SDP (AKA "info frames") */
3360                if (pipe_ctx->stream->timing.flags.DSC) {
3361                        if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3362                                        dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3363                                dp_set_dsc_on_rx(pipe_ctx, true);
3364                                dp_set_dsc_pps_sdp(pipe_ctx, true);
3365                        }
3366                }
3367
3368                if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3369                        dc_link_allocate_mst_payload(pipe_ctx);
3370
3371                dc->hwss.unblank_stream(pipe_ctx,
3372                        &pipe_ctx->stream->link->cur_link_settings);
3373
3374                if (stream->sink_patches.delay_ignore_msa > 0)
3375                        msleep(stream->sink_patches.delay_ignore_msa);
3376
3377                if (dc_is_dp_signal(pipe_ctx->stream->signal))
3378                        enable_stream_features(pipe_ctx);
3379#if defined(CONFIG_DRM_AMD_DC_HDCP)
3380                update_psp_stream_config(pipe_ctx, false);
3381#endif
3382
3383                dc->hwss.enable_audio_stream(pipe_ctx);
3384
3385        } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
3386                if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3387                                dc_is_virtual_signal(pipe_ctx->stream->signal))
3388                        dp_set_dsc_enable(pipe_ctx, true);
3389
3390        }
3391
3392        if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3393                core_link_set_avmute(pipe_ctx, false);
3394        }
3395}
3396
3397void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3398{
3399        struct dc  *dc = pipe_ctx->stream->ctx->dc;
3400        struct dc_stream_state *stream = pipe_ctx->stream;
3401        struct dc_link *link = stream->sink->link;
3402
3403        if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3404                        dc_is_virtual_signal(pipe_ctx->stream->signal))
3405                return;
3406
3407        if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
3408                if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
3409                        core_link_set_avmute(pipe_ctx, true);
3410        }
3411
3412        dc->hwss.disable_audio_stream(pipe_ctx);
3413
3414#if defined(CONFIG_DRM_AMD_DC_HDCP)
3415        update_psp_stream_config(pipe_ctx, true);
3416#endif
3417        dc->hwss.blank_stream(pipe_ctx);
3418
3419        if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3420                deallocate_mst_payload(pipe_ctx);
3421
3422        if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3423                struct ext_hdmi_settings settings = {0};
3424                enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3425
3426                unsigned short masked_chip_caps = link->chip_caps &
3427                                EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3428                //Need to inform that sink is going to use legacy HDMI mode.
3429                dal_ddc_service_write_scdc_data(
3430                        link->ddc,
3431                        165000,//vbios only handles 165Mhz.
3432                        false);
3433                if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3434                        /* DP159, Retimer settings */
3435                        if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3436                                write_i2c_retimer_setting(pipe_ctx,
3437                                                false, false, &settings);
3438                        else
3439                                write_i2c_default_retimer_setting(pipe_ctx,
3440                                                false, false);
3441                } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3442                        /* PI3EQX1204, Redriver settings */
3443                        write_i2c_redriver_setting(pipe_ctx, false);
3444                }
3445        }
3446
3447        disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3448
3449        dc->hwss.disable_stream(pipe_ctx);
3450
3451        if (pipe_ctx->stream->timing.flags.DSC) {
3452                if (dc_is_dp_signal(pipe_ctx->stream->signal))
3453                        dp_set_dsc_enable(pipe_ctx, false);
3454        }
3455}
3456
3457void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3458{
3459        struct dc  *dc = pipe_ctx->stream->ctx->dc;
3460
3461        if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3462                return;
3463
3464        dc->hwss.set_avmute(pipe_ctx, enable);
3465}
3466
3467/**
3468 *  dc_link_enable_hpd_filter:
3469 *     If enable is true, programs HPD filter on associated HPD line using
3470 *     delay_on_disconnect/delay_on_connect values dependent on
3471 *     link->connector_signal
3472 *
3473 *     If enable is false, programs HPD filter on associated HPD line with no
3474 *     delays on connect or disconnect
3475 *
3476 *  @link:   pointer to the dc link
3477 *  @enable: boolean specifying whether to enable hbd
3478 */
3479void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3480{
3481        struct gpio *hpd;
3482
3483        if (enable) {
3484                link->is_hpd_filter_disabled = false;
3485                program_hpd_filter(link);
3486        } else {
3487                link->is_hpd_filter_disabled = true;
3488                /* Obtain HPD handle */
3489                hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3490
3491                if (!hpd)
3492                        return;
3493
3494                /* Setup HPD filtering */
3495                if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3496                        struct gpio_hpd_config config;
3497
3498                        config.delay_on_connect = 0;
3499                        config.delay_on_disconnect = 0;
3500
3501                        dal_irq_setup_hpd_filter(hpd, &config);
3502
3503                        dal_gpio_close(hpd);
3504                } else {
3505                        ASSERT_CRITICAL(false);
3506                }
3507                /* Release HPD handle */
3508                dal_gpio_destroy_irq(&hpd);
3509        }
3510}
3511
3512uint32_t dc_bandwidth_in_kbps_from_timing(
3513        const struct dc_crtc_timing *timing)
3514{
3515        uint32_t bits_per_channel = 0;
3516        uint32_t kbps;
3517
3518#if defined(CONFIG_DRM_AMD_DC_DCN)
3519        if (timing->flags.DSC)
3520                return dc_dsc_stream_bandwidth_in_kbps(timing,
3521                                timing->dsc_cfg.bits_per_pixel,
3522                                timing->dsc_cfg.num_slices_h,
3523                                timing->dsc_cfg.is_dp);
3524#endif
3525
3526        switch (timing->display_color_depth) {
3527        case COLOR_DEPTH_666:
3528                bits_per_channel = 6;
3529                break;
3530        case COLOR_DEPTH_888:
3531                bits_per_channel = 8;
3532                break;
3533        case COLOR_DEPTH_101010:
3534                bits_per_channel = 10;
3535                break;
3536        case COLOR_DEPTH_121212:
3537                bits_per_channel = 12;
3538                break;
3539        case COLOR_DEPTH_141414:
3540                bits_per_channel = 14;
3541                break;
3542        case COLOR_DEPTH_161616:
3543                bits_per_channel = 16;
3544                break;
3545        default:
3546                ASSERT(bits_per_channel != 0);
3547                bits_per_channel = 8;
3548                break;
3549        }
3550
3551        kbps = timing->pix_clk_100hz / 10;
3552        kbps *= bits_per_channel;
3553
3554        if (timing->flags.Y_ONLY != 1) {
3555                /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/
3556                kbps *= 3;
3557                if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3558                        kbps /= 2;
3559                else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3560                        kbps = kbps * 2 / 3;
3561        }
3562
3563        return kbps;
3564
3565}
3566
3567void dc_link_set_drive_settings(struct dc *dc,
3568                                struct link_training_settings *lt_settings,
3569                                const struct dc_link *link)
3570{
3571
3572        int i;
3573
3574        for (i = 0; i < dc->link_count; i++) {
3575                if (dc->links[i] == link)
3576                        break;
3577        }
3578
3579        if (i >= dc->link_count)
3580                ASSERT_CRITICAL(false);
3581
3582        dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3583}
3584
3585void dc_link_set_preferred_link_settings(struct dc *dc,
3586                                         struct dc_link_settings *link_setting,
3587                                         struct dc_link *link)
3588{
3589        int i;
3590        struct pipe_ctx *pipe;
3591        struct dc_stream_state *link_stream;
3592        struct dc_link_settings store_settings = *link_setting;
3593
3594        link->preferred_link_setting = store_settings;
3595
3596        /* Retrain with preferred link settings only relevant for
3597         * DP signal type
3598         * Check for non-DP signal or if passive dongle present
3599         */
3600        if (!dc_is_dp_signal(link->connector_signal) ||
3601                link->dongle_max_pix_clk > 0)
3602                return;
3603
3604        for (i = 0; i < MAX_PIPES; i++) {
3605                pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3606                if (pipe->stream && pipe->stream->link) {
3607                        if (pipe->stream->link == link) {
3608                                link_stream = pipe->stream;
3609                                break;
3610                        }
3611                }
3612        }
3613
3614        /* Stream not found */
3615        if (i == MAX_PIPES)
3616                return;
3617
3618        /* Cannot retrain link if backend is off */
3619        if (link_stream->dpms_off)
3620                return;
3621
3622        decide_link_settings(link_stream, &store_settings);
3623
3624        if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3625                (store_settings.link_rate != LINK_RATE_UNKNOWN))
3626                dp_retrain_link_dp_test(link, &store_settings, false);
3627}
3628
3629void dc_link_set_preferred_training_settings(struct dc *dc,
3630                                                 struct dc_link_settings *link_setting,
3631                                                 struct dc_link_training_overrides *lt_overrides,
3632                                                 struct dc_link *link,
3633                                                 bool skip_immediate_retrain)
3634{
3635        if (lt_overrides != NULL)
3636                link->preferred_training_settings = *lt_overrides;
3637        else
3638                memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3639
3640        if (link_setting != NULL) {
3641                link->preferred_link_setting = *link_setting;
3642        } else {
3643                link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3644                link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3645        }
3646
3647        /* Retrain now, or wait until next stream update to apply */
3648        if (skip_immediate_retrain == false)
3649                dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3650}
3651
3652void dc_link_enable_hpd(const struct dc_link *link)
3653{
3654        dc_link_dp_enable_hpd(link);
3655}
3656
3657void dc_link_disable_hpd(const struct dc_link *link)
3658{
3659        dc_link_dp_disable_hpd(link);
3660}
3661
3662void dc_link_set_test_pattern(struct dc_link *link,
3663                              enum dp_test_pattern test_pattern,
3664                              enum dp_test_pattern_color_space test_pattern_color_space,
3665                              const struct link_training_settings *p_link_settings,
3666                              const unsigned char *p_custom_pattern,
3667                              unsigned int cust_pattern_size)
3668{
3669        if (link != NULL)
3670                dc_link_dp_set_test_pattern(
3671                        link,
3672                        test_pattern,
3673                        test_pattern_color_space,
3674                        p_link_settings,
3675                        p_custom_pattern,
3676                        cust_pattern_size);
3677}
3678
3679uint32_t dc_link_bandwidth_kbps(
3680        const struct dc_link *link,
3681        const struct dc_link_settings *link_setting)
3682{
3683        uint32_t link_bw_kbps =
3684                link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */
3685
3686        link_bw_kbps *= 8;   /* 8 bits per byte*/
3687        link_bw_kbps *= link_setting->lane_count;
3688
3689        if (dc_link_should_enable_fec(link)) {
3690                /* Account for FEC overhead.
3691                 * We have to do it based on caps,
3692                 * and not based on FEC being set ready,
3693                 * because FEC is set ready too late in
3694                 * the process to correctly be picked up
3695                 * by mode enumeration.
3696                 *
3697                 * There's enough zeros at the end of 'kbps'
3698                 * that make the below operation 100% precise
3699                 * for our purposes.
3700                 * 'long long' makes it work even for HDMI 2.1
3701                 * max bandwidth (and much, much bigger bandwidths
3702                 * than that, actually).
3703                 *
3704                 * NOTE: Reducing link BW by 3% may not be precise
3705                 * because it may be a stream BT that increases by 3%, and so
3706                 * 1/1.03 = 0.970873 factor should have been used instead,
3707                 * but the difference is minimal and is in a safe direction,
3708                 * which all works well around potential ambiguity of DP 1.4a spec.
3709                 */
3710                long long fec_link_bw_kbps = link_bw_kbps * 970LL;
3711                link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
3712        }
3713
3714        return link_bw_kbps;
3715
3716}
3717
3718const struct dc_link_settings *dc_link_get_link_cap(
3719                const struct dc_link *link)
3720{
3721        if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3722                        link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3723                return &link->preferred_link_setting;
3724        return &link->verified_link_cap;
3725}
3726
3727void dc_link_overwrite_extended_receiver_cap(
3728                struct dc_link *link)
3729{
3730        dp_overwrite_extended_receiver_cap(link);
3731}
3732
3733bool dc_link_is_fec_supported(const struct dc_link *link)
3734{
3735        struct link_encoder *link_enc = NULL;
3736
3737        /* Links supporting dynamically assigned link encoder will be assigned next
3738         * available encoder if one not already assigned.
3739         */
3740        if (link->is_dig_mapping_flexible &&
3741                        link->dc->res_pool->funcs->link_encs_assign) {
3742                link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
3743                if (link_enc == NULL)
3744                        link_enc = link_enc_cfg_get_next_avail_link_enc(link->dc, link->dc->current_state);
3745        } else
3746                link_enc = link->link_enc;
3747        ASSERT(link_enc);
3748
3749        return (dc_is_dp_signal(link->connector_signal) &&
3750                        link_enc->features.fec_supported &&
3751                        link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3752                        !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3753}
3754
3755bool dc_link_should_enable_fec(const struct dc_link *link)
3756{
3757        bool is_fec_disable = false;
3758        bool ret = false;
3759
3760        if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
3761                        link->local_sink &&
3762                        link->local_sink->edid_caps.panel_patch.disable_fec) ||
3763                        (link->connector_signal == SIGNAL_TYPE_EDP &&
3764                                        link->dc->debug.force_enable_edp_fec == false)) // Disable FEC for eDP
3765                is_fec_disable = true;
3766
3767        if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
3768                ret = true;
3769
3770        return ret;
3771}
3772