linux/drivers/clocksource/sh_cmt.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * SuperH Timer Support - CMT
   4 *
   5 *  Copyright (C) 2008 Magnus Damm
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/clockchips.h>
  10#include <linux/clocksource.h>
  11#include <linux/delay.h>
  12#include <linux/err.h>
  13#include <linux/init.h>
  14#include <linux/interrupt.h>
  15#include <linux/io.h>
  16#include <linux/ioport.h>
  17#include <linux/irq.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/of_device.h>
  21#include <linux/platform_device.h>
  22#include <linux/pm_domain.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/sh_timer.h>
  25#include <linux/slab.h>
  26#include <linux/spinlock.h>
  27
  28#ifdef CONFIG_SUPERH
  29#include <asm/platform_early.h>
  30#endif
  31
  32struct sh_cmt_device;
  33
  34/*
  35 * The CMT comes in 5 different identified flavours, depending not only on the
  36 * SoC but also on the particular instance. The following table lists the main
  37 * characteristics of those flavours.
  38 *
  39 *                      16B     32B     32B-F   48B     R-Car Gen2
  40 * -----------------------------------------------------------------------------
  41 * Channels             2       1/4     1       6       2/8
  42 * Control Width        16      16      16      16      32
  43 * Counter Width        16      32      32      32/48   32/48
  44 * Shared Start/Stop    Y       Y       Y       Y       N
  45 *
  46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
  47 * located in the channel registers block. All other versions have a shared
  48 * start/stop register located in the global space.
  49 *
  50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
  51 * infers the start/stop bit position in the control register and the channel
  52 * registers block address. Some CMT instances have a subset of channels
  53 * available, in which case the index in the documentation doesn't match the
  54 * "real" index as implemented in hardware. This is for instance the case with
  55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
  56 * in the documentation but using start/stop bit 5 and having its registers
  57 * block at 0x60.
  58 *
  59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
  60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
  61 */
  62
  63enum sh_cmt_model {
  64        SH_CMT_16BIT,
  65        SH_CMT_32BIT,
  66        SH_CMT_48BIT,
  67        SH_CMT0_RCAR_GEN2,
  68        SH_CMT1_RCAR_GEN2,
  69};
  70
  71struct sh_cmt_info {
  72        enum sh_cmt_model model;
  73
  74        unsigned int channels_mask;
  75
  76        unsigned long width; /* 16 or 32 bit version of hardware block */
  77        u32 overflow_bit;
  78        u32 clear_bits;
  79
  80        /* callbacks for CMSTR and CMCSR access */
  81        u32 (*read_control)(void __iomem *base, unsigned long offs);
  82        void (*write_control)(void __iomem *base, unsigned long offs,
  83                              u32 value);
  84
  85        /* callbacks for CMCNT and CMCOR access */
  86        u32 (*read_count)(void __iomem *base, unsigned long offs);
  87        void (*write_count)(void __iomem *base, unsigned long offs, u32 value);
  88};
  89
  90struct sh_cmt_channel {
  91        struct sh_cmt_device *cmt;
  92
  93        unsigned int index;     /* Index in the documentation */
  94        unsigned int hwidx;     /* Real hardware index */
  95
  96        void __iomem *iostart;
  97        void __iomem *ioctrl;
  98
  99        unsigned int timer_bit;
 100        unsigned long flags;
 101        u32 match_value;
 102        u32 next_match_value;
 103        u32 max_match_value;
 104        raw_spinlock_t lock;
 105        struct clock_event_device ced;
 106        struct clocksource cs;
 107        u64 total_cycles;
 108        bool cs_enabled;
 109};
 110
 111struct sh_cmt_device {
 112        struct platform_device *pdev;
 113
 114        const struct sh_cmt_info *info;
 115
 116        void __iomem *mapbase;
 117        struct clk *clk;
 118        unsigned long rate;
 119
 120        raw_spinlock_t lock; /* Protect the shared start/stop register */
 121
 122        struct sh_cmt_channel *channels;
 123        unsigned int num_channels;
 124        unsigned int hw_channels;
 125
 126        bool has_clockevent;
 127        bool has_clocksource;
 128};
 129
 130#define SH_CMT16_CMCSR_CMF              (1 << 7)
 131#define SH_CMT16_CMCSR_CMIE             (1 << 6)
 132#define SH_CMT16_CMCSR_CKS8             (0 << 0)
 133#define SH_CMT16_CMCSR_CKS32            (1 << 0)
 134#define SH_CMT16_CMCSR_CKS128           (2 << 0)
 135#define SH_CMT16_CMCSR_CKS512           (3 << 0)
 136#define SH_CMT16_CMCSR_CKS_MASK         (3 << 0)
 137
 138#define SH_CMT32_CMCSR_CMF              (1 << 15)
 139#define SH_CMT32_CMCSR_OVF              (1 << 14)
 140#define SH_CMT32_CMCSR_WRFLG            (1 << 13)
 141#define SH_CMT32_CMCSR_STTF             (1 << 12)
 142#define SH_CMT32_CMCSR_STPF             (1 << 11)
 143#define SH_CMT32_CMCSR_SSIE             (1 << 10)
 144#define SH_CMT32_CMCSR_CMS              (1 << 9)
 145#define SH_CMT32_CMCSR_CMM              (1 << 8)
 146#define SH_CMT32_CMCSR_CMTOUT_IE        (1 << 7)
 147#define SH_CMT32_CMCSR_CMR_NONE         (0 << 4)
 148#define SH_CMT32_CMCSR_CMR_DMA          (1 << 4)
 149#define SH_CMT32_CMCSR_CMR_IRQ          (2 << 4)
 150#define SH_CMT32_CMCSR_CMR_MASK         (3 << 4)
 151#define SH_CMT32_CMCSR_DBGIVD           (1 << 3)
 152#define SH_CMT32_CMCSR_CKS_RCLK8        (4 << 0)
 153#define SH_CMT32_CMCSR_CKS_RCLK32       (5 << 0)
 154#define SH_CMT32_CMCSR_CKS_RCLK128      (6 << 0)
 155#define SH_CMT32_CMCSR_CKS_RCLK1        (7 << 0)
 156#define SH_CMT32_CMCSR_CKS_MASK         (7 << 0)
 157
 158static u32 sh_cmt_read16(void __iomem *base, unsigned long offs)
 159{
 160        return ioread16(base + (offs << 1));
 161}
 162
 163static u32 sh_cmt_read32(void __iomem *base, unsigned long offs)
 164{
 165        return ioread32(base + (offs << 2));
 166}
 167
 168static void sh_cmt_write16(void __iomem *base, unsigned long offs, u32 value)
 169{
 170        iowrite16(value, base + (offs << 1));
 171}
 172
 173static void sh_cmt_write32(void __iomem *base, unsigned long offs, u32 value)
 174{
 175        iowrite32(value, base + (offs << 2));
 176}
 177
 178static const struct sh_cmt_info sh_cmt_info[] = {
 179        [SH_CMT_16BIT] = {
 180                .model = SH_CMT_16BIT,
 181                .width = 16,
 182                .overflow_bit = SH_CMT16_CMCSR_CMF,
 183                .clear_bits = ~SH_CMT16_CMCSR_CMF,
 184                .read_control = sh_cmt_read16,
 185                .write_control = sh_cmt_write16,
 186                .read_count = sh_cmt_read16,
 187                .write_count = sh_cmt_write16,
 188        },
 189        [SH_CMT_32BIT] = {
 190                .model = SH_CMT_32BIT,
 191                .width = 32,
 192                .overflow_bit = SH_CMT32_CMCSR_CMF,
 193                .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 194                .read_control = sh_cmt_read16,
 195                .write_control = sh_cmt_write16,
 196                .read_count = sh_cmt_read32,
 197                .write_count = sh_cmt_write32,
 198        },
 199        [SH_CMT_48BIT] = {
 200                .model = SH_CMT_48BIT,
 201                .channels_mask = 0x3f,
 202                .width = 32,
 203                .overflow_bit = SH_CMT32_CMCSR_CMF,
 204                .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 205                .read_control = sh_cmt_read32,
 206                .write_control = sh_cmt_write32,
 207                .read_count = sh_cmt_read32,
 208                .write_count = sh_cmt_write32,
 209        },
 210        [SH_CMT0_RCAR_GEN2] = {
 211                .model = SH_CMT0_RCAR_GEN2,
 212                .channels_mask = 0x60,
 213                .width = 32,
 214                .overflow_bit = SH_CMT32_CMCSR_CMF,
 215                .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 216                .read_control = sh_cmt_read32,
 217                .write_control = sh_cmt_write32,
 218                .read_count = sh_cmt_read32,
 219                .write_count = sh_cmt_write32,
 220        },
 221        [SH_CMT1_RCAR_GEN2] = {
 222                .model = SH_CMT1_RCAR_GEN2,
 223                .channels_mask = 0xff,
 224                .width = 32,
 225                .overflow_bit = SH_CMT32_CMCSR_CMF,
 226                .clear_bits = ~(SH_CMT32_CMCSR_CMF | SH_CMT32_CMCSR_OVF),
 227                .read_control = sh_cmt_read32,
 228                .write_control = sh_cmt_write32,
 229                .read_count = sh_cmt_read32,
 230                .write_count = sh_cmt_write32,
 231        },
 232};
 233
 234#define CMCSR 0 /* channel register */
 235#define CMCNT 1 /* channel register */
 236#define CMCOR 2 /* channel register */
 237
 238#define CMCLKE  0x1000  /* CLK Enable Register (R-Car Gen2) */
 239
 240static inline u32 sh_cmt_read_cmstr(struct sh_cmt_channel *ch)
 241{
 242        if (ch->iostart)
 243                return ch->cmt->info->read_control(ch->iostart, 0);
 244        else
 245                return ch->cmt->info->read_control(ch->cmt->mapbase, 0);
 246}
 247
 248static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, u32 value)
 249{
 250        if (ch->iostart)
 251                ch->cmt->info->write_control(ch->iostart, 0, value);
 252        else
 253                ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);
 254}
 255
 256static inline u32 sh_cmt_read_cmcsr(struct sh_cmt_channel *ch)
 257{
 258        return ch->cmt->info->read_control(ch->ioctrl, CMCSR);
 259}
 260
 261static inline void sh_cmt_write_cmcsr(struct sh_cmt_channel *ch, u32 value)
 262{
 263        ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);
 264}
 265
 266static inline u32 sh_cmt_read_cmcnt(struct sh_cmt_channel *ch)
 267{
 268        return ch->cmt->info->read_count(ch->ioctrl, CMCNT);
 269}
 270
 271static inline void sh_cmt_write_cmcnt(struct sh_cmt_channel *ch, u32 value)
 272{
 273        ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);
 274}
 275
 276static inline void sh_cmt_write_cmcor(struct sh_cmt_channel *ch, u32 value)
 277{
 278        ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);
 279}
 280
 281static u32 sh_cmt_get_counter(struct sh_cmt_channel *ch, u32 *has_wrapped)
 282{
 283        u32 v1, v2, v3;
 284        u32 o1, o2;
 285
 286        o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 287
 288        /* Make sure the timer value is stable. Stolen from acpi_pm.c */
 289        do {
 290                o2 = o1;
 291                v1 = sh_cmt_read_cmcnt(ch);
 292                v2 = sh_cmt_read_cmcnt(ch);
 293                v3 = sh_cmt_read_cmcnt(ch);
 294                o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;
 295        } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
 296                          || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
 297
 298        *has_wrapped = o1;
 299        return v2;
 300}
 301
 302static void sh_cmt_start_stop_ch(struct sh_cmt_channel *ch, int start)
 303{
 304        unsigned long flags;
 305        u32 value;
 306
 307        /* start stop register shared by multiple timer channels */
 308        raw_spin_lock_irqsave(&ch->cmt->lock, flags);
 309        value = sh_cmt_read_cmstr(ch);
 310
 311        if (start)
 312                value |= 1 << ch->timer_bit;
 313        else
 314                value &= ~(1 << ch->timer_bit);
 315
 316        sh_cmt_write_cmstr(ch, value);
 317        raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);
 318}
 319
 320static int sh_cmt_enable(struct sh_cmt_channel *ch)
 321{
 322        int k, ret;
 323
 324        dev_pm_syscore_device(&ch->cmt->pdev->dev, true);
 325
 326        /* enable clock */
 327        ret = clk_enable(ch->cmt->clk);
 328        if (ret) {
 329                dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",
 330                        ch->index);
 331                goto err0;
 332        }
 333
 334        /* make sure channel is disabled */
 335        sh_cmt_start_stop_ch(ch, 0);
 336
 337        /* configure channel, periodic mode and maximum timeout */
 338        if (ch->cmt->info->width == 16) {
 339                sh_cmt_write_cmcsr(ch, SH_CMT16_CMCSR_CMIE |
 340                                   SH_CMT16_CMCSR_CKS512);
 341        } else {
 342                u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ?
 343                              SH_CMT32_CMCSR_CMTOUT_IE : 0;
 344                sh_cmt_write_cmcsr(ch, cmtout | SH_CMT32_CMCSR_CMM |
 345                                   SH_CMT32_CMCSR_CMR_IRQ |
 346                                   SH_CMT32_CMCSR_CKS_RCLK8);
 347        }
 348
 349        sh_cmt_write_cmcor(ch, 0xffffffff);
 350        sh_cmt_write_cmcnt(ch, 0);
 351
 352        /*
 353         * According to the sh73a0 user's manual, as CMCNT can be operated
 354         * only by the RCLK (Pseudo 32 kHz), there's one restriction on
 355         * modifying CMCNT register; two RCLK cycles are necessary before
 356         * this register is either read or any modification of the value
 357         * it holds is reflected in the LSI's actual operation.
 358         *
 359         * While at it, we're supposed to clear out the CMCNT as of this
 360         * moment, so make sure it's processed properly here.  This will
 361         * take RCLKx2 at maximum.
 362         */
 363        for (k = 0; k < 100; k++) {
 364                if (!sh_cmt_read_cmcnt(ch))
 365                        break;
 366                udelay(1);
 367        }
 368
 369        if (sh_cmt_read_cmcnt(ch)) {
 370                dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",
 371                        ch->index);
 372                ret = -ETIMEDOUT;
 373                goto err1;
 374        }
 375
 376        /* enable channel */
 377        sh_cmt_start_stop_ch(ch, 1);
 378        return 0;
 379 err1:
 380        /* stop clock */
 381        clk_disable(ch->cmt->clk);
 382
 383 err0:
 384        return ret;
 385}
 386
 387static void sh_cmt_disable(struct sh_cmt_channel *ch)
 388{
 389        /* disable channel */
 390        sh_cmt_start_stop_ch(ch, 0);
 391
 392        /* disable interrupts in CMT block */
 393        sh_cmt_write_cmcsr(ch, 0);
 394
 395        /* stop clock */
 396        clk_disable(ch->cmt->clk);
 397
 398        dev_pm_syscore_device(&ch->cmt->pdev->dev, false);
 399}
 400
 401/* private flags */
 402#define FLAG_CLOCKEVENT (1 << 0)
 403#define FLAG_CLOCKSOURCE (1 << 1)
 404#define FLAG_REPROGRAM (1 << 2)
 405#define FLAG_SKIPEVENT (1 << 3)
 406#define FLAG_IRQCONTEXT (1 << 4)
 407
 408static void sh_cmt_clock_event_program_verify(struct sh_cmt_channel *ch,
 409                                              int absolute)
 410{
 411        u32 value = ch->next_match_value;
 412        u32 new_match;
 413        u32 delay = 0;
 414        u32 now = 0;
 415        u32 has_wrapped;
 416
 417        now = sh_cmt_get_counter(ch, &has_wrapped);
 418        ch->flags |= FLAG_REPROGRAM; /* force reprogram */
 419
 420        if (has_wrapped) {
 421                /* we're competing with the interrupt handler.
 422                 *  -> let the interrupt handler reprogram the timer.
 423                 *  -> interrupt number two handles the event.
 424                 */
 425                ch->flags |= FLAG_SKIPEVENT;
 426                return;
 427        }
 428
 429        if (absolute)
 430                now = 0;
 431
 432        do {
 433                /* reprogram the timer hardware,
 434                 * but don't save the new match value yet.
 435                 */
 436                new_match = now + value + delay;
 437                if (new_match > ch->max_match_value)
 438                        new_match = ch->max_match_value;
 439
 440                sh_cmt_write_cmcor(ch, new_match);
 441
 442                now = sh_cmt_get_counter(ch, &has_wrapped);
 443                if (has_wrapped && (new_match > ch->match_value)) {
 444                        /* we are changing to a greater match value,
 445                         * so this wrap must be caused by the counter
 446                         * matching the old value.
 447                         * -> first interrupt reprograms the timer.
 448                         * -> interrupt number two handles the event.
 449                         */
 450                        ch->flags |= FLAG_SKIPEVENT;
 451                        break;
 452                }
 453
 454                if (has_wrapped) {
 455                        /* we are changing to a smaller match value,
 456                         * so the wrap must be caused by the counter
 457                         * matching the new value.
 458                         * -> save programmed match value.
 459                         * -> let isr handle the event.
 460                         */
 461                        ch->match_value = new_match;
 462                        break;
 463                }
 464
 465                /* be safe: verify hardware settings */
 466                if (now < new_match) {
 467                        /* timer value is below match value, all good.
 468                         * this makes sure we won't miss any match events.
 469                         * -> save programmed match value.
 470                         * -> let isr handle the event.
 471                         */
 472                        ch->match_value = new_match;
 473                        break;
 474                }
 475
 476                /* the counter has reached a value greater
 477                 * than our new match value. and since the
 478                 * has_wrapped flag isn't set we must have
 479                 * programmed a too close event.
 480                 * -> increase delay and retry.
 481                 */
 482                if (delay)
 483                        delay <<= 1;
 484                else
 485                        delay = 1;
 486
 487                if (!delay)
 488                        dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",
 489                                 ch->index);
 490
 491        } while (delay);
 492}
 493
 494static void __sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 495{
 496        if (delta > ch->max_match_value)
 497                dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",
 498                         ch->index);
 499
 500        ch->next_match_value = delta;
 501        sh_cmt_clock_event_program_verify(ch, 0);
 502}
 503
 504static void sh_cmt_set_next(struct sh_cmt_channel *ch, unsigned long delta)
 505{
 506        unsigned long flags;
 507
 508        raw_spin_lock_irqsave(&ch->lock, flags);
 509        __sh_cmt_set_next(ch, delta);
 510        raw_spin_unlock_irqrestore(&ch->lock, flags);
 511}
 512
 513static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
 514{
 515        struct sh_cmt_channel *ch = dev_id;
 516
 517        /* clear flags */
 518        sh_cmt_write_cmcsr(ch, sh_cmt_read_cmcsr(ch) &
 519                           ch->cmt->info->clear_bits);
 520
 521        /* update clock source counter to begin with if enabled
 522         * the wrap flag should be cleared by the timer specific
 523         * isr before we end up here.
 524         */
 525        if (ch->flags & FLAG_CLOCKSOURCE)
 526                ch->total_cycles += ch->match_value + 1;
 527
 528        if (!(ch->flags & FLAG_REPROGRAM))
 529                ch->next_match_value = ch->max_match_value;
 530
 531        ch->flags |= FLAG_IRQCONTEXT;
 532
 533        if (ch->flags & FLAG_CLOCKEVENT) {
 534                if (!(ch->flags & FLAG_SKIPEVENT)) {
 535                        if (clockevent_state_oneshot(&ch->ced)) {
 536                                ch->next_match_value = ch->max_match_value;
 537                                ch->flags |= FLAG_REPROGRAM;
 538                        }
 539
 540                        ch->ced.event_handler(&ch->ced);
 541                }
 542        }
 543
 544        ch->flags &= ~FLAG_SKIPEVENT;
 545
 546        if (ch->flags & FLAG_REPROGRAM) {
 547                ch->flags &= ~FLAG_REPROGRAM;
 548                sh_cmt_clock_event_program_verify(ch, 1);
 549
 550                if (ch->flags & FLAG_CLOCKEVENT)
 551                        if ((clockevent_state_shutdown(&ch->ced))
 552                            || (ch->match_value == ch->next_match_value))
 553                                ch->flags &= ~FLAG_REPROGRAM;
 554        }
 555
 556        ch->flags &= ~FLAG_IRQCONTEXT;
 557
 558        return IRQ_HANDLED;
 559}
 560
 561static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag)
 562{
 563        int ret = 0;
 564        unsigned long flags;
 565
 566        if (flag & FLAG_CLOCKSOURCE)
 567                pm_runtime_get_sync(&ch->cmt->pdev->dev);
 568
 569        raw_spin_lock_irqsave(&ch->lock, flags);
 570
 571        if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
 572                if (flag & FLAG_CLOCKEVENT)
 573                        pm_runtime_get_sync(&ch->cmt->pdev->dev);
 574                ret = sh_cmt_enable(ch);
 575        }
 576
 577        if (ret)
 578                goto out;
 579        ch->flags |= flag;
 580
 581        /* setup timeout if no clockevent */
 582        if ((flag == FLAG_CLOCKSOURCE) && (!(ch->flags & FLAG_CLOCKEVENT)))
 583                __sh_cmt_set_next(ch, ch->max_match_value);
 584 out:
 585        raw_spin_unlock_irqrestore(&ch->lock, flags);
 586
 587        return ret;
 588}
 589
 590static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag)
 591{
 592        unsigned long flags;
 593        unsigned long f;
 594
 595        raw_spin_lock_irqsave(&ch->lock, flags);
 596
 597        f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
 598        ch->flags &= ~flag;
 599
 600        if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) {
 601                sh_cmt_disable(ch);
 602                if (flag & FLAG_CLOCKEVENT)
 603                        pm_runtime_put(&ch->cmt->pdev->dev);
 604        }
 605
 606        /* adjust the timeout to maximum if only clocksource left */
 607        if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE))
 608                __sh_cmt_set_next(ch, ch->max_match_value);
 609
 610        raw_spin_unlock_irqrestore(&ch->lock, flags);
 611
 612        if (flag & FLAG_CLOCKSOURCE)
 613                pm_runtime_put(&ch->cmt->pdev->dev);
 614}
 615
 616static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)
 617{
 618        return container_of(cs, struct sh_cmt_channel, cs);
 619}
 620
 621static u64 sh_cmt_clocksource_read(struct clocksource *cs)
 622{
 623        struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 624        unsigned long flags;
 625        u32 has_wrapped;
 626        u64 value;
 627        u32 raw;
 628
 629        raw_spin_lock_irqsave(&ch->lock, flags);
 630        value = ch->total_cycles;
 631        raw = sh_cmt_get_counter(ch, &has_wrapped);
 632
 633        if (unlikely(has_wrapped))
 634                raw += ch->match_value + 1;
 635        raw_spin_unlock_irqrestore(&ch->lock, flags);
 636
 637        return value + raw;
 638}
 639
 640static int sh_cmt_clocksource_enable(struct clocksource *cs)
 641{
 642        int ret;
 643        struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 644
 645        WARN_ON(ch->cs_enabled);
 646
 647        ch->total_cycles = 0;
 648
 649        ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 650        if (!ret)
 651                ch->cs_enabled = true;
 652
 653        return ret;
 654}
 655
 656static void sh_cmt_clocksource_disable(struct clocksource *cs)
 657{
 658        struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 659
 660        WARN_ON(!ch->cs_enabled);
 661
 662        sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 663        ch->cs_enabled = false;
 664}
 665
 666static void sh_cmt_clocksource_suspend(struct clocksource *cs)
 667{
 668        struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 669
 670        if (!ch->cs_enabled)
 671                return;
 672
 673        sh_cmt_stop(ch, FLAG_CLOCKSOURCE);
 674        dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
 675}
 676
 677static void sh_cmt_clocksource_resume(struct clocksource *cs)
 678{
 679        struct sh_cmt_channel *ch = cs_to_sh_cmt(cs);
 680
 681        if (!ch->cs_enabled)
 682                return;
 683
 684        dev_pm_genpd_resume(&ch->cmt->pdev->dev);
 685        sh_cmt_start(ch, FLAG_CLOCKSOURCE);
 686}
 687
 688static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch,
 689                                       const char *name)
 690{
 691        struct clocksource *cs = &ch->cs;
 692
 693        cs->name = name;
 694        cs->rating = 125;
 695        cs->read = sh_cmt_clocksource_read;
 696        cs->enable = sh_cmt_clocksource_enable;
 697        cs->disable = sh_cmt_clocksource_disable;
 698        cs->suspend = sh_cmt_clocksource_suspend;
 699        cs->resume = sh_cmt_clocksource_resume;
 700        cs->mask = CLOCKSOURCE_MASK(sizeof(u64) * 8);
 701        cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
 702
 703        dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
 704                 ch->index);
 705
 706        clocksource_register_hz(cs, ch->cmt->rate);
 707        return 0;
 708}
 709
 710static struct sh_cmt_channel *ced_to_sh_cmt(struct clock_event_device *ced)
 711{
 712        return container_of(ced, struct sh_cmt_channel, ced);
 713}
 714
 715static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic)
 716{
 717        sh_cmt_start(ch, FLAG_CLOCKEVENT);
 718
 719        if (periodic)
 720                sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1);
 721        else
 722                sh_cmt_set_next(ch, ch->max_match_value);
 723}
 724
 725static int sh_cmt_clock_event_shutdown(struct clock_event_device *ced)
 726{
 727        struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 728
 729        sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 730        return 0;
 731}
 732
 733static int sh_cmt_clock_event_set_state(struct clock_event_device *ced,
 734                                        int periodic)
 735{
 736        struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 737
 738        /* deal with old setting first */
 739        if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced))
 740                sh_cmt_stop(ch, FLAG_CLOCKEVENT);
 741
 742        dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n",
 743                 ch->index, periodic ? "periodic" : "oneshot");
 744        sh_cmt_clock_event_start(ch, periodic);
 745        return 0;
 746}
 747
 748static int sh_cmt_clock_event_set_oneshot(struct clock_event_device *ced)
 749{
 750        return sh_cmt_clock_event_set_state(ced, 0);
 751}
 752
 753static int sh_cmt_clock_event_set_periodic(struct clock_event_device *ced)
 754{
 755        return sh_cmt_clock_event_set_state(ced, 1);
 756}
 757
 758static int sh_cmt_clock_event_next(unsigned long delta,
 759                                   struct clock_event_device *ced)
 760{
 761        struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 762
 763        BUG_ON(!clockevent_state_oneshot(ced));
 764        if (likely(ch->flags & FLAG_IRQCONTEXT))
 765                ch->next_match_value = delta - 1;
 766        else
 767                sh_cmt_set_next(ch, delta - 1);
 768
 769        return 0;
 770}
 771
 772static void sh_cmt_clock_event_suspend(struct clock_event_device *ced)
 773{
 774        struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 775
 776        dev_pm_genpd_suspend(&ch->cmt->pdev->dev);
 777        clk_unprepare(ch->cmt->clk);
 778}
 779
 780static void sh_cmt_clock_event_resume(struct clock_event_device *ced)
 781{
 782        struct sh_cmt_channel *ch = ced_to_sh_cmt(ced);
 783
 784        clk_prepare(ch->cmt->clk);
 785        dev_pm_genpd_resume(&ch->cmt->pdev->dev);
 786}
 787
 788static int sh_cmt_register_clockevent(struct sh_cmt_channel *ch,
 789                                      const char *name)
 790{
 791        struct clock_event_device *ced = &ch->ced;
 792        int irq;
 793        int ret;
 794
 795        irq = platform_get_irq(ch->cmt->pdev, ch->index);
 796        if (irq < 0)
 797                return irq;
 798
 799        ret = request_irq(irq, sh_cmt_interrupt,
 800                          IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
 801                          dev_name(&ch->cmt->pdev->dev), ch);
 802        if (ret) {
 803                dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",
 804                        ch->index, irq);
 805                return ret;
 806        }
 807
 808        ced->name = name;
 809        ced->features = CLOCK_EVT_FEAT_PERIODIC;
 810        ced->features |= CLOCK_EVT_FEAT_ONESHOT;
 811        ced->rating = 125;
 812        ced->cpumask = cpu_possible_mask;
 813        ced->set_next_event = sh_cmt_clock_event_next;
 814        ced->set_state_shutdown = sh_cmt_clock_event_shutdown;
 815        ced->set_state_periodic = sh_cmt_clock_event_set_periodic;
 816        ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot;
 817        ced->suspend = sh_cmt_clock_event_suspend;
 818        ced->resume = sh_cmt_clock_event_resume;
 819
 820        /* TODO: calculate good shift from rate and counter bit width */
 821        ced->shift = 32;
 822        ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift);
 823        ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced);
 824        ced->max_delta_ticks = ch->max_match_value;
 825        ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
 826        ced->min_delta_ticks = 0x1f;
 827
 828        dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",
 829                 ch->index);
 830        clockevents_register_device(ced);
 831
 832        return 0;
 833}
 834
 835static int sh_cmt_register(struct sh_cmt_channel *ch, const char *name,
 836                           bool clockevent, bool clocksource)
 837{
 838        int ret;
 839
 840        if (clockevent) {
 841                ch->cmt->has_clockevent = true;
 842                ret = sh_cmt_register_clockevent(ch, name);
 843                if (ret < 0)
 844                        return ret;
 845        }
 846
 847        if (clocksource) {
 848                ch->cmt->has_clocksource = true;
 849                sh_cmt_register_clocksource(ch, name);
 850        }
 851
 852        return 0;
 853}
 854
 855static int sh_cmt_setup_channel(struct sh_cmt_channel *ch, unsigned int index,
 856                                unsigned int hwidx, bool clockevent,
 857                                bool clocksource, struct sh_cmt_device *cmt)
 858{
 859        u32 value;
 860        int ret;
 861
 862        /* Skip unused channels. */
 863        if (!clockevent && !clocksource)
 864                return 0;
 865
 866        ch->cmt = cmt;
 867        ch->index = index;
 868        ch->hwidx = hwidx;
 869        ch->timer_bit = hwidx;
 870
 871        /*
 872         * Compute the address of the channel control register block. For the
 873         * timers with a per-channel start/stop register, compute its address
 874         * as well.
 875         */
 876        switch (cmt->info->model) {
 877        case SH_CMT_16BIT:
 878                ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;
 879                break;
 880        case SH_CMT_32BIT:
 881        case SH_CMT_48BIT:
 882                ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;
 883                break;
 884        case SH_CMT0_RCAR_GEN2:
 885        case SH_CMT1_RCAR_GEN2:
 886                ch->iostart = cmt->mapbase + ch->hwidx * 0x100;
 887                ch->ioctrl = ch->iostart + 0x10;
 888                ch->timer_bit = 0;
 889
 890                /* Enable the clock supply to the channel */
 891                value = ioread32(cmt->mapbase + CMCLKE);
 892                value |= BIT(hwidx);
 893                iowrite32(value, cmt->mapbase + CMCLKE);
 894                break;
 895        }
 896
 897        if (cmt->info->width == (sizeof(ch->max_match_value) * 8))
 898                ch->max_match_value = ~0;
 899        else
 900                ch->max_match_value = (1 << cmt->info->width) - 1;
 901
 902        ch->match_value = ch->max_match_value;
 903        raw_spin_lock_init(&ch->lock);
 904
 905        ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),
 906                              clockevent, clocksource);
 907        if (ret) {
 908                dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",
 909                        ch->index);
 910                return ret;
 911        }
 912        ch->cs_enabled = false;
 913
 914        return 0;
 915}
 916
 917static int sh_cmt_map_memory(struct sh_cmt_device *cmt)
 918{
 919        struct resource *mem;
 920
 921        mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);
 922        if (!mem) {
 923                dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");
 924                return -ENXIO;
 925        }
 926
 927        cmt->mapbase = ioremap(mem->start, resource_size(mem));
 928        if (cmt->mapbase == NULL) {
 929                dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");
 930                return -ENXIO;
 931        }
 932
 933        return 0;
 934}
 935
 936static const struct platform_device_id sh_cmt_id_table[] = {
 937        { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
 938        { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
 939        { }
 940};
 941MODULE_DEVICE_TABLE(platform, sh_cmt_id_table);
 942
 943static const struct of_device_id sh_cmt_of_table[] __maybe_unused = {
 944        {
 945                /* deprecated, preserved for backward compatibility */
 946                .compatible = "renesas,cmt-48",
 947                .data = &sh_cmt_info[SH_CMT_48BIT]
 948        },
 949        {
 950                /* deprecated, preserved for backward compatibility */
 951                .compatible = "renesas,cmt-48-gen2",
 952                .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 953        },
 954        {
 955                .compatible = "renesas,r8a7740-cmt1",
 956                .data = &sh_cmt_info[SH_CMT_48BIT]
 957        },
 958        {
 959                .compatible = "renesas,sh73a0-cmt1",
 960                .data = &sh_cmt_info[SH_CMT_48BIT]
 961        },
 962        {
 963                .compatible = "renesas,rcar-gen2-cmt0",
 964                .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 965        },
 966        {
 967                .compatible = "renesas,rcar-gen2-cmt1",
 968                .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 969        },
 970        {
 971                .compatible = "renesas,rcar-gen3-cmt0",
 972                .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2]
 973        },
 974        {
 975                .compatible = "renesas,rcar-gen3-cmt1",
 976                .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2]
 977        },
 978        { }
 979};
 980MODULE_DEVICE_TABLE(of, sh_cmt_of_table);
 981
 982static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)
 983{
 984        unsigned int mask;
 985        unsigned int i;
 986        int ret;
 987
 988        cmt->pdev = pdev;
 989        raw_spin_lock_init(&cmt->lock);
 990
 991        if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
 992                cmt->info = of_device_get_match_data(&pdev->dev);
 993                cmt->hw_channels = cmt->info->channels_mask;
 994        } else if (pdev->dev.platform_data) {
 995                struct sh_timer_config *cfg = pdev->dev.platform_data;
 996                const struct platform_device_id *id = pdev->id_entry;
 997
 998                cmt->info = (const struct sh_cmt_info *)id->driver_data;
 999                cmt->hw_channels = cfg->channels_mask;
1000        } else {
1001                dev_err(&cmt->pdev->dev, "missing platform data\n");
1002                return -ENXIO;
1003        }
1004
1005        /* Get hold of clock. */
1006        cmt->clk = clk_get(&cmt->pdev->dev, "fck");
1007        if (IS_ERR(cmt->clk)) {
1008                dev_err(&cmt->pdev->dev, "cannot get clock\n");
1009                return PTR_ERR(cmt->clk);
1010        }
1011
1012        ret = clk_prepare(cmt->clk);
1013        if (ret < 0)
1014                goto err_clk_put;
1015
1016        /* Determine clock rate. */
1017        ret = clk_enable(cmt->clk);
1018        if (ret < 0)
1019                goto err_clk_unprepare;
1020
1021        if (cmt->info->width == 16)
1022                cmt->rate = clk_get_rate(cmt->clk) / 512;
1023        else
1024                cmt->rate = clk_get_rate(cmt->clk) / 8;
1025
1026        /* Map the memory resource(s). */
1027        ret = sh_cmt_map_memory(cmt);
1028        if (ret < 0)
1029                goto err_clk_disable;
1030
1031        /* Allocate and setup the channels. */
1032        cmt->num_channels = hweight8(cmt->hw_channels);
1033        cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels),
1034                                GFP_KERNEL);
1035        if (cmt->channels == NULL) {
1036                ret = -ENOMEM;
1037                goto err_unmap;
1038        }
1039
1040        /*
1041         * Use the first channel as a clock event device and the second channel
1042         * as a clock source. If only one channel is available use it for both.
1043         */
1044        for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {
1045                unsigned int hwidx = ffs(mask) - 1;
1046                bool clocksource = i == 1 || cmt->num_channels == 1;
1047                bool clockevent = i == 0;
1048
1049                ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,
1050                                           clockevent, clocksource, cmt);
1051                if (ret < 0)
1052                        goto err_unmap;
1053
1054                mask &= ~(1 << hwidx);
1055        }
1056
1057        clk_disable(cmt->clk);
1058
1059        platform_set_drvdata(pdev, cmt);
1060
1061        return 0;
1062
1063err_unmap:
1064        kfree(cmt->channels);
1065        iounmap(cmt->mapbase);
1066err_clk_disable:
1067        clk_disable(cmt->clk);
1068err_clk_unprepare:
1069        clk_unprepare(cmt->clk);
1070err_clk_put:
1071        clk_put(cmt->clk);
1072        return ret;
1073}
1074
1075static int sh_cmt_probe(struct platform_device *pdev)
1076{
1077        struct sh_cmt_device *cmt = platform_get_drvdata(pdev);
1078        int ret;
1079
1080        if (!is_sh_early_platform_device(pdev)) {
1081                pm_runtime_set_active(&pdev->dev);
1082                pm_runtime_enable(&pdev->dev);
1083        }
1084
1085        if (cmt) {
1086                dev_info(&pdev->dev, "kept as earlytimer\n");
1087                goto out;
1088        }
1089
1090        cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);
1091        if (cmt == NULL)
1092                return -ENOMEM;
1093
1094        ret = sh_cmt_setup(cmt, pdev);
1095        if (ret) {
1096                kfree(cmt);
1097                pm_runtime_idle(&pdev->dev);
1098                return ret;
1099        }
1100        if (is_sh_early_platform_device(pdev))
1101                return 0;
1102
1103 out:
1104        if (cmt->has_clockevent || cmt->has_clocksource)
1105                pm_runtime_irq_safe(&pdev->dev);
1106        else
1107                pm_runtime_idle(&pdev->dev);
1108
1109        return 0;
1110}
1111
1112static int sh_cmt_remove(struct platform_device *pdev)
1113{
1114        return -EBUSY; /* cannot unregister clockevent and clocksource */
1115}
1116
1117static struct platform_driver sh_cmt_device_driver = {
1118        .probe          = sh_cmt_probe,
1119        .remove         = sh_cmt_remove,
1120        .driver         = {
1121                .name   = "sh_cmt",
1122                .of_match_table = of_match_ptr(sh_cmt_of_table),
1123        },
1124        .id_table       = sh_cmt_id_table,
1125};
1126
1127static int __init sh_cmt_init(void)
1128{
1129        return platform_driver_register(&sh_cmt_device_driver);
1130}
1131
1132static void __exit sh_cmt_exit(void)
1133{
1134        platform_driver_unregister(&sh_cmt_device_driver);
1135}
1136
1137#ifdef CONFIG_SUPERH
1138sh_early_platform_init("earlytimer", &sh_cmt_device_driver);
1139#endif
1140
1141subsys_initcall(sh_cmt_init);
1142module_exit(sh_cmt_exit);
1143
1144MODULE_AUTHOR("Magnus Damm");
1145MODULE_DESCRIPTION("SuperH CMT Timer Driver");
1146MODULE_LICENSE("GPL v2");
1147