LXR linux/drivers/clk/ti/clk-33xx.c

   1/*
   2 * AM33XX Clock init
   3 *
   4 * Copyright (C) 2013 Texas Instruments, Inc
   5 *     Tero Kristo (t-kristo@ti.com)
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation version 2.
  10 *
  11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12 * kind, whether express or implied; without even the implied warranty
  13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 * GNU General Public License for more details.
  15 */
  16
  17#include <linux/kernel.h>
  18#include <linux/list.h>
  19#include <linux/clk.h>
  20#include <linux/clk-provider.h>
  21#include <linux/clk/ti.h>
  22#include <dt-bindings/clock/am3.h>
  23
  24#include "clock.h"
  25
  26static const char * const am3_gpio1_dbclk_parents[] __initconst = {
  27        "clk-24mhz-clkctrl:0000:0",
  28        NULL,
  29};
  30
  31static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
  32        { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  33        { 0 },
  34};
  35
  36static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
  37        { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  38        { 0 },
  39};
  40
  41static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
  42        { 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
  43        { 0 },
  44};
  45
  46static const struct omap_clkctrl_reg_data am3_l4ls_clkctrl_regs[] __initconst = {
  47        { AM3_L4LS_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  48        { AM3_L4LS_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  49        { AM3_L4LS_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  50        { AM3_L4LS_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  51        { AM3_L4LS_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  52        { AM3_L4LS_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  53        { AM3_L4LS_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  54        { AM3_L4LS_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  55        { AM3_L4LS_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  56        { AM3_L4LS_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  57        { AM3_L4LS_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  58        { AM3_L4LS_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
  59        { AM3_L4LS_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
  60        { AM3_L4LS_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
  61        { AM3_L4LS_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
  62        { AM3_L4LS_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
  63        { AM3_L4LS_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
  64        { AM3_L4LS_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  65        { AM3_L4LS_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  66        { AM3_L4LS_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
  67        { AM3_L4LS_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
  68        { AM3_L4LS_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
  69        { AM3_L4LS_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  70        { AM3_L4LS_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  71        { AM3_L4LS_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  72        { AM3_L4LS_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
  73        { AM3_L4LS_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
  74        { AM3_L4LS_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  75        { AM3_L4LS_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  76        { AM3_L4LS_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  77        { AM3_L4LS_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
  78        { 0 },
  79};
  80
  81static const struct omap_clkctrl_reg_data am3_l3s_clkctrl_regs[] __initconst = {
  82        { AM3_L3S_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck" },
  83        { AM3_L3S_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk" },
  84        { AM3_L3S_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck" },
  85        { AM3_L3S_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck" },
  86        { AM3_L3S_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
  87        { 0 },
  88};
  89
  90static const struct omap_clkctrl_reg_data am3_l3_clkctrl_regs[] __initconst = {
  91        { AM3_L3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  92        { AM3_L3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck" },
  93        { AM3_L3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  94        { AM3_L3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck" },
  95        { AM3_L3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  96        { AM3_L3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  97        { AM3_L3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  98        { AM3_L3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
  99        { AM3_L3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
 100        { AM3_L3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk" },
 101        { 0 },
 102};
 103
 104static const struct omap_clkctrl_reg_data am3_l4hs_clkctrl_regs[] __initconst = {
 105        { AM3_L4HS_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk" },
 106        { 0 },
 107};
 108
 109static const struct omap_clkctrl_reg_data am3_pruss_ocp_clkctrl_regs[] __initconst = {
 110        { AM3_PRUSS_OCP_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "pruss_ocp_gclk" },
 111        { 0 },
 112};
 113
 114static const struct omap_clkctrl_reg_data am3_cpsw_125mhz_clkctrl_regs[] __initconst = {
 115        { AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" },
 116        { 0 },
 117};
 118
 119static const struct omap_clkctrl_reg_data am3_lcdc_clkctrl_regs[] __initconst = {
 120        { AM3_LCDC_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk" },
 121        { 0 },
 122};
 123
 124static const struct omap_clkctrl_reg_data am3_clk_24mhz_clkctrl_regs[] __initconst = {
 125        { AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck" },
 126        { 0 },
 127};
 128
 129static const char * const am3_gpio0_dbclk_parents[] __initconst = {
 130        "gpio0_dbclk_mux_ck",
 131        NULL,
 132};
 133
 134static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
 135        { 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
 136        { 0 },
 137};
 138
 139static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
 140        { AM3_L4_WKUP_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
 141        { AM3_L4_WKUP_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
 142        { AM3_L4_WKUP_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
 143        { AM3_L4_WKUP_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
 144        { AM3_L4_WKUP_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
 145        { AM3_L4_WKUP_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
 146        { AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
 147        { AM3_L4_WKUP_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
 148        { AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
 149        { AM3_L4_WKUP_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
 150        { 0 },
 151};
 152
 153static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
 154        "sys_clkin_ck",
 155        NULL,
 156};
 157
 158static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
 159        "l3-aon-clkctrl:0000:19",
 160        "l3-aon-clkctrl:0000:30",
 161        NULL,
 162};
 163
 164static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
 165        "l3-aon-clkctrl:0000:20",
 166        NULL,
 167};
 168
 169static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
 170        .max_div = 64,
 171        .flags = CLK_DIVIDER_POWER_OF_TWO,
 172};
 173
 174static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
 175        "l3-aon-clkctrl:0000:22",
 176        NULL,
 177};
 178
 179static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
 180        .max_div = 64,
 181        .flags = CLK_DIVIDER_POWER_OF_TWO,
 182};
 183
 184static const char * const am3_dbg_clka_ck_parents[] __initconst = {
 185        "dpll_core_m4_ck",
 186        NULL,
 187};
 188
 189static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
 190        { 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
 191        { 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
 192        { 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
 193        { 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
 194        { 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
 195        { 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
 196        { 0 },
 197};
 198
 199static const struct omap_clkctrl_reg_data am3_l3_aon_clkctrl_regs[] __initconst = {
 200        { AM3_L3_AON_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l3-aon-clkctrl:0000:24" },
 201        { 0 },
 202};
 203
 204static const struct omap_clkctrl_reg_data am3_l4_wkup_aon_clkctrl_regs[] __initconst = {
 205        { AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck" },
 206        { 0 },
 207};
 208
 209static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
 210        { AM3_MPU_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
 211        { 0 },
 212};
 213
 214static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
 215        { AM3_L4_RTC_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk-24mhz-clkctrl:0000:0" },
 216        { 0 },
 217};
 218
 219static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
 220        { AM3_GFX_L3_GFX_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "gfx_fck_div_ck" },
 221        { 0 },
 222};
 223
 224static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
 225        { AM3_L4_CEFUSE_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
 226        { 0 },
 227};
 228
 229const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
 230        { 0x44e00038, am3_l4ls_clkctrl_regs },
 231        { 0x44e0001c, am3_l3s_clkctrl_regs },
 232        { 0x44e00024, am3_l3_clkctrl_regs },
 233        { 0x44e00120, am3_l4hs_clkctrl_regs },
 234        { 0x44e000e8, am3_pruss_ocp_clkctrl_regs },
 235        { 0x44e00000, am3_cpsw_125mhz_clkctrl_regs },
 236        { 0x44e00018, am3_lcdc_clkctrl_regs },
 237        { 0x44e0014c, am3_clk_24mhz_clkctrl_regs },
 238        { 0x44e00400, am3_l4_wkup_clkctrl_regs },
 239        { 0x44e00414, am3_l3_aon_clkctrl_regs },
 240        { 0x44e004b0, am3_l4_wkup_aon_clkctrl_regs },
 241        { 0x44e00600, am3_mpu_clkctrl_regs },
 242        { 0x44e00800, am3_l4_rtc_clkctrl_regs },
 243        { 0x44e00900, am3_gfx_l3_clkctrl_regs },
 244        { 0x44e00a00, am3_l4_cefuse_clkctrl_regs },
 245        { 0 },
 246};
 247
 248static struct ti_dt_clk am33xx_clks[] = {
 249        DT_CLK(NULL, "timer_32k_ck", "clk-24mhz-clkctrl:0000:0"),
 250        DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
 251        DT_CLK(NULL, "clkdiv32k_ick", "clk-24mhz-clkctrl:0000:0"),
 252        DT_CLK(NULL, "dbg_clka_ck", "l3-aon-clkctrl:0000:30"),
 253        DT_CLK(NULL, "dbg_sysclk_ck", "l3-aon-clkctrl:0000:19"),
 254        DT_CLK(NULL, "gpio0_dbclk", "l4-wkup-clkctrl:0008:18"),
 255        DT_CLK(NULL, "gpio1_dbclk", "l4ls-clkctrl:0074:18"),
 256        DT_CLK(NULL, "gpio2_dbclk", "l4ls-clkctrl:0078:18"),
 257        DT_CLK(NULL, "gpio3_dbclk", "l4ls-clkctrl:007c:18"),
 258        DT_CLK(NULL, "stm_clk_div_ck", "l3-aon-clkctrl:0000:27"),
 259        DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l3-aon-clkctrl:0000:22"),
 260        DT_CLK(NULL, "trace_clk_div_ck", "l3-aon-clkctrl:0000:24"),
 261        DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l3-aon-clkctrl:0000:20"),
 262        { .node_name = NULL },
 263};
 264
 265static const char *enable_init_clks[] = {
 266        "dpll_ddr_m2_ck",
 267        "dpll_mpu_m2_ck",
 268        "l3_gclk",
 269        /* AM3_L3_L3_MAIN_CLKCTRL, needed during suspend */
 270        "l3-clkctrl:00bc:0",
 271        "l4hs_gclk",
 272        "l4fw_gclk",
 273        "l4ls_gclk",
 274        /* Required for external peripherals like, Audio codecs */
 275        "clkout2_ck",
 276};
 277
 278int __init am33xx_dt_clk_init(void)
 279{
 280        struct clk *clk1, *clk2;
 281
 282        if (ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT)
 283                ti_dt_clocks_register(am33xx_compat_clks);
 284        else
 285                ti_dt_clocks_register(am33xx_clks);
 286
 287        omap2_clk_disable_autoidle_all();
 288
 289        ti_clk_add_aliases();
 290
 291        omap2_clk_enable_init_clocks(enable_init_clks,
 292                                     ARRAY_SIZE(enable_init_clks));
 293
 294        /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
 295         *    physically present, in such a case HWMOD enabling of
 296         *    clock would be failure with default parent. And timer
 297         *    probe thinks clock is already enabled, this leads to
 298         *    crash upon accessing timer 3 & 6 registers in probe.
 299         *    Fix by setting parent of both these timers to master
 300         *    oscillator clock.
 301         */
 302
 303        clk1 = clk_get_sys(NULL, "sys_clkin_ck");
 304        clk2 = clk_get_sys(NULL, "timer3_fck");
 305        clk_set_parent(clk2, clk1);
 306
 307        clk2 = clk_get_sys(NULL, "timer6_fck");
 308        clk_set_parent(clk2, clk1);
 309        /*
 310         * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
 311         * the design/spec, so as a result, for example, timer which supposed
 312         * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
 313         * not expected by any use-case, so change WDT1 clock source to PRCM
 314         * 32KHz clock.
 315         */
 316        clk1 = clk_get_sys(NULL, "wdt1_fck");
 317        clk2 = clk_get_sys(NULL, "clkdiv32k_ick");
 318        clk_set_parent(clk1, clk2);
 319
 320        return 0;
 321}
 322