linux/drivers/clk/clk-si5351.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * clk-si5351.c: Silicon Laboratories Si5351A/B/C I2C Clock Generator
   4 *
   5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   6 * Rabeeh Khoury <rabeeh@solid-run.com>
   7 *
   8 * References:
   9 * [1] "Si5351A/B/C Data Sheet"
  10 *     https://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
  11 * [2] "Manually Generating an Si5351 Register Map"
  12 *     https://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
  13 */
  14
  15#include <linux/module.h>
  16#include <linux/kernel.h>
  17#include <linux/clk.h>
  18#include <linux/clk-provider.h>
  19#include <linux/delay.h>
  20#include <linux/err.h>
  21#include <linux/errno.h>
  22#include <linux/rational.h>
  23#include <linux/i2c.h>
  24#include <linux/of_platform.h>
  25#include <linux/platform_data/si5351.h>
  26#include <linux/regmap.h>
  27#include <linux/slab.h>
  28#include <linux/string.h>
  29#include <asm/div64.h>
  30
  31#include "clk-si5351.h"
  32
  33struct si5351_driver_data;
  34
  35struct si5351_parameters {
  36        unsigned long   p1;
  37        unsigned long   p2;
  38        unsigned long   p3;
  39        int             valid;
  40};
  41
  42struct si5351_hw_data {
  43        struct clk_hw                   hw;
  44        struct si5351_driver_data       *drvdata;
  45        struct si5351_parameters        params;
  46        unsigned char                   num;
  47};
  48
  49struct si5351_driver_data {
  50        enum si5351_variant     variant;
  51        struct i2c_client       *client;
  52        struct regmap           *regmap;
  53
  54        struct clk              *pxtal;
  55        const char              *pxtal_name;
  56        struct clk_hw           xtal;
  57        struct clk              *pclkin;
  58        const char              *pclkin_name;
  59        struct clk_hw           clkin;
  60
  61        struct si5351_hw_data   pll[2];
  62        struct si5351_hw_data   *msynth;
  63        struct si5351_hw_data   *clkout;
  64        size_t                  num_clkout;
  65};
  66
  67static const char * const si5351_input_names[] = {
  68        "xtal", "clkin"
  69};
  70static const char * const si5351_pll_names[] = {
  71        "si5351_plla", "si5351_pllb", "si5351_vxco"
  72};
  73static const char * const si5351_msynth_names[] = {
  74        "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
  75};
  76static const char * const si5351_clkout_names[] = {
  77        "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
  78};
  79
  80/*
  81 * Si5351 i2c regmap
  82 */
  83static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
  84{
  85        u32 val;
  86        int ret;
  87
  88        ret = regmap_read(drvdata->regmap, reg, &val);
  89        if (ret) {
  90                dev_err(&drvdata->client->dev,
  91                        "unable to read from reg%02x\n", reg);
  92                return 0;
  93        }
  94
  95        return (u8)val;
  96}
  97
  98static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
  99                                   u8 reg, u8 count, u8 *buf)
 100{
 101        return regmap_bulk_read(drvdata->regmap, reg, buf, count);
 102}
 103
 104static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
 105                                   u8 reg, u8 val)
 106{
 107        return regmap_write(drvdata->regmap, reg, val);
 108}
 109
 110static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
 111                                    u8 reg, u8 count, const u8 *buf)
 112{
 113        return regmap_raw_write(drvdata->regmap, reg, buf, count);
 114}
 115
 116static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
 117                                  u8 reg, u8 mask, u8 val)
 118{
 119        return regmap_update_bits(drvdata->regmap, reg, mask, val);
 120}
 121
 122static inline u8 si5351_msynth_params_address(int num)
 123{
 124        if (num > 5)
 125                return SI5351_CLK6_PARAMETERS + (num - 6);
 126        return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
 127}
 128
 129static void si5351_read_parameters(struct si5351_driver_data *drvdata,
 130                                   u8 reg, struct si5351_parameters *params)
 131{
 132        u8 buf[SI5351_PARAMETERS_LENGTH];
 133
 134        switch (reg) {
 135        case SI5351_CLK6_PARAMETERS:
 136        case SI5351_CLK7_PARAMETERS:
 137                buf[0] = si5351_reg_read(drvdata, reg);
 138                params->p1 = buf[0];
 139                params->p2 = 0;
 140                params->p3 = 1;
 141                break;
 142        default:
 143                si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
 144                params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
 145                params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
 146                params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
 147        }
 148        params->valid = 1;
 149}
 150
 151static void si5351_write_parameters(struct si5351_driver_data *drvdata,
 152                                    u8 reg, struct si5351_parameters *params)
 153{
 154        u8 buf[SI5351_PARAMETERS_LENGTH];
 155
 156        switch (reg) {
 157        case SI5351_CLK6_PARAMETERS:
 158        case SI5351_CLK7_PARAMETERS:
 159                buf[0] = params->p1 & 0xff;
 160                si5351_reg_write(drvdata, reg, buf[0]);
 161                break;
 162        default:
 163                buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
 164                buf[1] = params->p3 & 0xff;
 165                /* save rdiv and divby4 */
 166                buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
 167                buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
 168                buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
 169                buf[4] = params->p1 & 0xff;
 170                buf[5] = ((params->p3 & 0xf0000) >> 12) |
 171                        ((params->p2 & 0xf0000) >> 16);
 172                buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
 173                buf[7] = params->p2 & 0xff;
 174                si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
 175        }
 176}
 177
 178static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
 179{
 180        switch (reg) {
 181        case SI5351_DEVICE_STATUS:
 182        case SI5351_INTERRUPT_STATUS:
 183        case SI5351_PLL_RESET:
 184                return true;
 185        }
 186        return false;
 187}
 188
 189static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
 190{
 191        /* reserved registers */
 192        if (reg >= 4 && reg <= 8)
 193                return false;
 194        if (reg >= 10 && reg <= 14)
 195                return false;
 196        if (reg >= 173 && reg <= 176)
 197                return false;
 198        if (reg >= 178 && reg <= 182)
 199                return false;
 200        /* read-only */
 201        if (reg == SI5351_DEVICE_STATUS)
 202                return false;
 203        return true;
 204}
 205
 206static const struct regmap_config si5351_regmap_config = {
 207        .reg_bits = 8,
 208        .val_bits = 8,
 209        .cache_type = REGCACHE_RBTREE,
 210        .max_register = 187,
 211        .writeable_reg = si5351_regmap_is_writeable,
 212        .volatile_reg = si5351_regmap_is_volatile,
 213};
 214
 215/*
 216 * Si5351 xtal clock input
 217 */
 218static int si5351_xtal_prepare(struct clk_hw *hw)
 219{
 220        struct si5351_driver_data *drvdata =
 221                container_of(hw, struct si5351_driver_data, xtal);
 222        si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
 223                        SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
 224        return 0;
 225}
 226
 227static void si5351_xtal_unprepare(struct clk_hw *hw)
 228{
 229        struct si5351_driver_data *drvdata =
 230                container_of(hw, struct si5351_driver_data, xtal);
 231        si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
 232                        SI5351_XTAL_ENABLE, 0);
 233}
 234
 235static const struct clk_ops si5351_xtal_ops = {
 236        .prepare = si5351_xtal_prepare,
 237        .unprepare = si5351_xtal_unprepare,
 238};
 239
 240/*
 241 * Si5351 clkin clock input (Si5351C only)
 242 */
 243static int si5351_clkin_prepare(struct clk_hw *hw)
 244{
 245        struct si5351_driver_data *drvdata =
 246                container_of(hw, struct si5351_driver_data, clkin);
 247        si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
 248                        SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
 249        return 0;
 250}
 251
 252static void si5351_clkin_unprepare(struct clk_hw *hw)
 253{
 254        struct si5351_driver_data *drvdata =
 255                container_of(hw, struct si5351_driver_data, clkin);
 256        si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
 257                        SI5351_CLKIN_ENABLE, 0);
 258}
 259
 260/*
 261 * CMOS clock source constraints:
 262 * The input frequency range of the PLL is 10Mhz to 40MHz.
 263 * If CLKIN is >40MHz, the input divider must be used.
 264 */
 265static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
 266                                              unsigned long parent_rate)
 267{
 268        struct si5351_driver_data *drvdata =
 269                container_of(hw, struct si5351_driver_data, clkin);
 270        unsigned long rate;
 271        unsigned char idiv;
 272
 273        rate = parent_rate;
 274        if (parent_rate > 160000000) {
 275                idiv = SI5351_CLKIN_DIV_8;
 276                rate /= 8;
 277        } else if (parent_rate > 80000000) {
 278                idiv = SI5351_CLKIN_DIV_4;
 279                rate /= 4;
 280        } else if (parent_rate > 40000000) {
 281                idiv = SI5351_CLKIN_DIV_2;
 282                rate /= 2;
 283        } else {
 284                idiv = SI5351_CLKIN_DIV_1;
 285        }
 286
 287        si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
 288                        SI5351_CLKIN_DIV_MASK, idiv);
 289
 290        dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
 291                __func__, (1 << (idiv >> 6)), rate);
 292
 293        return rate;
 294}
 295
 296static const struct clk_ops si5351_clkin_ops = {
 297        .prepare = si5351_clkin_prepare,
 298        .unprepare = si5351_clkin_unprepare,
 299        .recalc_rate = si5351_clkin_recalc_rate,
 300};
 301
 302/*
 303 * Si5351 vxco clock input (Si5351B only)
 304 */
 305
 306static int si5351_vxco_prepare(struct clk_hw *hw)
 307{
 308        struct si5351_hw_data *hwdata =
 309                container_of(hw, struct si5351_hw_data, hw);
 310
 311        dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
 312
 313        return 0;
 314}
 315
 316static void si5351_vxco_unprepare(struct clk_hw *hw)
 317{
 318}
 319
 320static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
 321                                             unsigned long parent_rate)
 322{
 323        return 0;
 324}
 325
 326static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
 327                                unsigned long parent)
 328{
 329        return 0;
 330}
 331
 332static const struct clk_ops si5351_vxco_ops = {
 333        .prepare = si5351_vxco_prepare,
 334        .unprepare = si5351_vxco_unprepare,
 335        .recalc_rate = si5351_vxco_recalc_rate,
 336        .set_rate = si5351_vxco_set_rate,
 337};
 338
 339/*
 340 * Si5351 pll a/b
 341 *
 342 * Feedback Multisynth Divider Equations [2]
 343 *
 344 * fVCO = fIN * (a + b/c)
 345 *
 346 * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
 347 * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
 348 *
 349 * Feedback Multisynth Register Equations
 350 *
 351 * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
 352 * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
 353 * (3) MSNx_P3[19:0] = c
 354 *
 355 * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
 356 *
 357 * Using (4) on (1) yields:
 358 * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
 359 * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
 360 *
 361 * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
 362 *         = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
 363 *
 364 */
 365static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
 366                                int num, enum si5351_pll_src parent)
 367{
 368        u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
 369
 370        if (parent == SI5351_PLL_SRC_DEFAULT)
 371                return 0;
 372
 373        if (num > 2)
 374                return -EINVAL;
 375
 376        if (drvdata->variant != SI5351_VARIANT_C &&
 377            parent != SI5351_PLL_SRC_XTAL)
 378                return -EINVAL;
 379
 380        si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
 381                        (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
 382        return 0;
 383}
 384
 385static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
 386{
 387        struct si5351_hw_data *hwdata =
 388                container_of(hw, struct si5351_hw_data, hw);
 389        u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
 390        u8 val;
 391
 392        val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
 393
 394        return (val & mask) ? 1 : 0;
 395}
 396
 397static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
 398{
 399        struct si5351_hw_data *hwdata =
 400                container_of(hw, struct si5351_hw_data, hw);
 401
 402        if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
 403            index > 0)
 404                return -EPERM;
 405
 406        if (index > 1)
 407                return -EINVAL;
 408
 409        return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
 410                             (index == 0) ? SI5351_PLL_SRC_XTAL :
 411                             SI5351_PLL_SRC_CLKIN);
 412}
 413
 414static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
 415                                            unsigned long parent_rate)
 416{
 417        struct si5351_hw_data *hwdata =
 418                container_of(hw, struct si5351_hw_data, hw);
 419        u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
 420                SI5351_PLLB_PARAMETERS;
 421        unsigned long long rate;
 422
 423        if (!hwdata->params.valid)
 424                si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
 425
 426        if (hwdata->params.p3 == 0)
 427                return parent_rate;
 428
 429        /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
 430        rate  = hwdata->params.p1 * hwdata->params.p3;
 431        rate += 512 * hwdata->params.p3;
 432        rate += hwdata->params.p2;
 433        rate *= parent_rate;
 434        do_div(rate, 128 * hwdata->params.p3);
 435
 436        dev_dbg(&hwdata->drvdata->client->dev,
 437                "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
 438                __func__, clk_hw_get_name(hw),
 439                hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
 440                parent_rate, (unsigned long)rate);
 441
 442        return (unsigned long)rate;
 443}
 444
 445static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 446                                  unsigned long *parent_rate)
 447{
 448        struct si5351_hw_data *hwdata =
 449                container_of(hw, struct si5351_hw_data, hw);
 450        unsigned long rfrac, denom, a, b, c;
 451        unsigned long long lltmp;
 452
 453        if (rate < SI5351_PLL_VCO_MIN)
 454                rate = SI5351_PLL_VCO_MIN;
 455        if (rate > SI5351_PLL_VCO_MAX)
 456                rate = SI5351_PLL_VCO_MAX;
 457
 458        /* determine integer part of feedback equation */
 459        a = rate / *parent_rate;
 460
 461        if (a < SI5351_PLL_A_MIN)
 462                rate = *parent_rate * SI5351_PLL_A_MIN;
 463        if (a > SI5351_PLL_A_MAX)
 464                rate = *parent_rate * SI5351_PLL_A_MAX;
 465
 466        /* find best approximation for b/c = fVCO mod fIN */
 467        denom = 1000 * 1000;
 468        lltmp = rate % (*parent_rate);
 469        lltmp *= denom;
 470        do_div(lltmp, *parent_rate);
 471        rfrac = (unsigned long)lltmp;
 472
 473        b = 0;
 474        c = 1;
 475        if (rfrac)
 476                rational_best_approximation(rfrac, denom,
 477                                    SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
 478
 479        /* calculate parameters */
 480        hwdata->params.p3  = c;
 481        hwdata->params.p2  = (128 * b) % c;
 482        hwdata->params.p1  = 128 * a;
 483        hwdata->params.p1 += (128 * b / c);
 484        hwdata->params.p1 -= 512;
 485
 486        /* recalculate rate by fIN * (a + b/c) */
 487        lltmp  = *parent_rate;
 488        lltmp *= b;
 489        do_div(lltmp, c);
 490
 491        rate  = (unsigned long)lltmp;
 492        rate += *parent_rate * a;
 493
 494        dev_dbg(&hwdata->drvdata->client->dev,
 495                "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
 496                __func__, clk_hw_get_name(hw), a, b, c,
 497                *parent_rate, rate);
 498
 499        return rate;
 500}
 501
 502static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 503                               unsigned long parent_rate)
 504{
 505        struct si5351_hw_data *hwdata =
 506                container_of(hw, struct si5351_hw_data, hw);
 507        u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
 508                SI5351_PLLB_PARAMETERS;
 509
 510        /* write multisynth parameters */
 511        si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
 512
 513        /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
 514        si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
 515                SI5351_CLK_INTEGER_MODE,
 516                (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
 517
 518        /* Do a pll soft reset on the affected pll */
 519        si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
 520                         hwdata->num == 0 ? SI5351_PLL_RESET_A :
 521                                            SI5351_PLL_RESET_B);
 522
 523        dev_dbg(&hwdata->drvdata->client->dev,
 524                "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
 525                __func__, clk_hw_get_name(hw),
 526                hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
 527                parent_rate, rate);
 528
 529        return 0;
 530}
 531
 532static const struct clk_ops si5351_pll_ops = {
 533        .set_parent = si5351_pll_set_parent,
 534        .get_parent = si5351_pll_get_parent,
 535        .recalc_rate = si5351_pll_recalc_rate,
 536        .round_rate = si5351_pll_round_rate,
 537        .set_rate = si5351_pll_set_rate,
 538};
 539
 540/*
 541 * Si5351 multisync divider
 542 *
 543 * for fOUT <= 150 MHz:
 544 *
 545 * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
 546 *
 547 * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
 548 * fIN = fVCO0, fVCO1
 549 *
 550 * Output Clock Multisynth Register Equations
 551 *
 552 * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
 553 * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
 554 * MSx_P3[19:0] = c
 555 *
 556 * MS[6,7] are integer (P1) divide only, P1 = divide value,
 557 * P2 and P3 are not applicable
 558 *
 559 * for 150MHz < fOUT <= 160MHz:
 560 *
 561 * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
 562 */
 563static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
 564                                   int num, enum si5351_multisynth_src parent)
 565{
 566        if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
 567                return 0;
 568
 569        if (num > 8)
 570                return -EINVAL;
 571
 572        si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
 573                        (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
 574                        SI5351_CLK_PLL_SELECT);
 575        return 0;
 576}
 577
 578static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
 579{
 580        struct si5351_hw_data *hwdata =
 581                container_of(hw, struct si5351_hw_data, hw);
 582        u8 val;
 583
 584        val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
 585
 586        return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
 587}
 588
 589static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
 590{
 591        struct si5351_hw_data *hwdata =
 592                container_of(hw, struct si5351_hw_data, hw);
 593
 594        return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
 595                               (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
 596                               SI5351_MULTISYNTH_SRC_VCO1);
 597}
 598
 599static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
 600                                               unsigned long parent_rate)
 601{
 602        struct si5351_hw_data *hwdata =
 603                container_of(hw, struct si5351_hw_data, hw);
 604        u8 reg = si5351_msynth_params_address(hwdata->num);
 605        unsigned long long rate;
 606        unsigned long m;
 607
 608        if (!hwdata->params.valid)
 609                si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
 610
 611        /*
 612         * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
 613         * multisync6-7: fOUT = fIN / P1
 614         */
 615        rate = parent_rate;
 616        if (hwdata->num > 5) {
 617                m = hwdata->params.p1;
 618        } else if (hwdata->params.p3 == 0) {
 619                return parent_rate;
 620        } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
 621                    SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
 622                m = 4;
 623        } else {
 624                rate *= 128 * hwdata->params.p3;
 625                m = hwdata->params.p1 * hwdata->params.p3;
 626                m += hwdata->params.p2;
 627                m += 512 * hwdata->params.p3;
 628        }
 629
 630        if (m == 0)
 631                return 0;
 632        do_div(rate, m);
 633
 634        dev_dbg(&hwdata->drvdata->client->dev,
 635                "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
 636                __func__, clk_hw_get_name(hw),
 637                hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
 638                m, parent_rate, (unsigned long)rate);
 639
 640        return (unsigned long)rate;
 641}
 642
 643static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
 644                                     unsigned long *parent_rate)
 645{
 646        struct si5351_hw_data *hwdata =
 647                container_of(hw, struct si5351_hw_data, hw);
 648        unsigned long long lltmp;
 649        unsigned long a, b, c;
 650        int divby4;
 651
 652        /* multisync6-7 can only handle freqencies < 150MHz */
 653        if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
 654                rate = SI5351_MULTISYNTH67_MAX_FREQ;
 655
 656        /* multisync frequency is 1MHz .. 160MHz */
 657        if (rate > SI5351_MULTISYNTH_MAX_FREQ)
 658                rate = SI5351_MULTISYNTH_MAX_FREQ;
 659        if (rate < SI5351_MULTISYNTH_MIN_FREQ)
 660                rate = SI5351_MULTISYNTH_MIN_FREQ;
 661
 662        divby4 = 0;
 663        if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
 664                divby4 = 1;
 665
 666        /* multisync can set pll */
 667        if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
 668                /*
 669                 * find largest integer divider for max
 670                 * vco frequency and given target rate
 671                 */
 672                if (divby4 == 0) {
 673                        lltmp = SI5351_PLL_VCO_MAX;
 674                        do_div(lltmp, rate);
 675                        a = (unsigned long)lltmp;
 676                } else
 677                        a = 4;
 678
 679                b = 0;
 680                c = 1;
 681
 682                *parent_rate = a * rate;
 683        } else if (hwdata->num >= 6) {
 684                /* determine the closest integer divider */
 685                a = DIV_ROUND_CLOSEST(*parent_rate, rate);
 686                if (a < SI5351_MULTISYNTH_A_MIN)
 687                        a = SI5351_MULTISYNTH_A_MIN;
 688                if (a > SI5351_MULTISYNTH67_A_MAX)
 689                        a = SI5351_MULTISYNTH67_A_MAX;
 690
 691                b = 0;
 692                c = 1;
 693        } else {
 694                unsigned long rfrac, denom;
 695
 696                /* disable divby4 */
 697                if (divby4) {
 698                        rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
 699                        divby4 = 0;
 700                }
 701
 702                /* determine integer part of divider equation */
 703                a = *parent_rate / rate;
 704                if (a < SI5351_MULTISYNTH_A_MIN)
 705                        a = SI5351_MULTISYNTH_A_MIN;
 706                if (a > SI5351_MULTISYNTH_A_MAX)
 707                        a = SI5351_MULTISYNTH_A_MAX;
 708
 709                /* find best approximation for b/c = fVCO mod fOUT */
 710                denom = 1000 * 1000;
 711                lltmp = (*parent_rate) % rate;
 712                lltmp *= denom;
 713                do_div(lltmp, rate);
 714                rfrac = (unsigned long)lltmp;
 715
 716                b = 0;
 717                c = 1;
 718                if (rfrac)
 719                        rational_best_approximation(rfrac, denom,
 720                            SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
 721                            &b, &c);
 722        }
 723
 724        /* recalculate rate by fOUT = fIN / (a + b/c) */
 725        lltmp  = *parent_rate;
 726        lltmp *= c;
 727        do_div(lltmp, a * c + b);
 728        rate  = (unsigned long)lltmp;
 729
 730        /* calculate parameters */
 731        if (divby4) {
 732                hwdata->params.p3 = 1;
 733                hwdata->params.p2 = 0;
 734                hwdata->params.p1 = 0;
 735        } else if (hwdata->num >= 6) {
 736                hwdata->params.p3 = 0;
 737                hwdata->params.p2 = 0;
 738                hwdata->params.p1 = a;
 739        } else {
 740                hwdata->params.p3  = c;
 741                hwdata->params.p2  = (128 * b) % c;
 742                hwdata->params.p1  = 128 * a;
 743                hwdata->params.p1 += (128 * b / c);
 744                hwdata->params.p1 -= 512;
 745        }
 746
 747        dev_dbg(&hwdata->drvdata->client->dev,
 748                "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
 749                __func__, clk_hw_get_name(hw), a, b, c, divby4,
 750                *parent_rate, rate);
 751
 752        return rate;
 753}
 754
 755static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
 756                                  unsigned long parent_rate)
 757{
 758        struct si5351_hw_data *hwdata =
 759                container_of(hw, struct si5351_hw_data, hw);
 760        u8 reg = si5351_msynth_params_address(hwdata->num);
 761        int divby4 = 0;
 762
 763        /* write multisynth parameters */
 764        si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
 765
 766        if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
 767                divby4 = 1;
 768
 769        /* enable/disable integer mode and divby4 on multisynth0-5 */
 770        if (hwdata->num < 6) {
 771                si5351_set_bits(hwdata->drvdata, reg + 2,
 772                                SI5351_OUTPUT_CLK_DIVBY4,
 773                                (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
 774                si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
 775                        SI5351_CLK_INTEGER_MODE,
 776                        (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
 777        }
 778
 779        dev_dbg(&hwdata->drvdata->client->dev,
 780                "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
 781                __func__, clk_hw_get_name(hw),
 782                hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
 783                divby4, parent_rate, rate);
 784
 785        return 0;
 786}
 787
 788static const struct clk_ops si5351_msynth_ops = {
 789        .set_parent = si5351_msynth_set_parent,
 790        .get_parent = si5351_msynth_get_parent,
 791        .recalc_rate = si5351_msynth_recalc_rate,
 792        .round_rate = si5351_msynth_round_rate,
 793        .set_rate = si5351_msynth_set_rate,
 794};
 795
 796/*
 797 * Si5351 clkout divider
 798 */
 799static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
 800                                   int num, enum si5351_clkout_src parent)
 801{
 802        u8 val;
 803
 804        if (num > 8)
 805                return -EINVAL;
 806
 807        switch (parent) {
 808        case SI5351_CLKOUT_SRC_MSYNTH_N:
 809                val = SI5351_CLK_INPUT_MULTISYNTH_N;
 810                break;
 811        case SI5351_CLKOUT_SRC_MSYNTH_0_4:
 812                /* clk0/clk4 can only connect to its own multisync */
 813                if (num == 0 || num == 4)
 814                        val = SI5351_CLK_INPUT_MULTISYNTH_N;
 815                else
 816                        val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
 817                break;
 818        case SI5351_CLKOUT_SRC_XTAL:
 819                val = SI5351_CLK_INPUT_XTAL;
 820                break;
 821        case SI5351_CLKOUT_SRC_CLKIN:
 822                if (drvdata->variant != SI5351_VARIANT_C)
 823                        return -EINVAL;
 824
 825                val = SI5351_CLK_INPUT_CLKIN;
 826                break;
 827        default:
 828                return 0;
 829        }
 830
 831        si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
 832                        SI5351_CLK_INPUT_MASK, val);
 833        return 0;
 834}
 835
 836static int _si5351_clkout_set_drive_strength(
 837        struct si5351_driver_data *drvdata, int num,
 838        enum si5351_drive_strength drive)
 839{
 840        u8 mask;
 841
 842        if (num > 8)
 843                return -EINVAL;
 844
 845        switch (drive) {
 846        case SI5351_DRIVE_2MA:
 847                mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
 848                break;
 849        case SI5351_DRIVE_4MA:
 850                mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
 851                break;
 852        case SI5351_DRIVE_6MA:
 853                mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
 854                break;
 855        case SI5351_DRIVE_8MA:
 856                mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
 857                break;
 858        default:
 859                return 0;
 860        }
 861
 862        si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
 863                        SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
 864        return 0;
 865}
 866
 867static int _si5351_clkout_set_disable_state(
 868        struct si5351_driver_data *drvdata, int num,
 869        enum si5351_disable_state state)
 870{
 871        u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
 872                SI5351_CLK7_4_DISABLE_STATE;
 873        u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
 874        u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
 875        u8 val;
 876
 877        if (num > 8)
 878                return -EINVAL;
 879
 880        switch (state) {
 881        case SI5351_DISABLE_LOW:
 882                val = SI5351_CLK_DISABLE_STATE_LOW;
 883                break;
 884        case SI5351_DISABLE_HIGH:
 885                val = SI5351_CLK_DISABLE_STATE_HIGH;
 886                break;
 887        case SI5351_DISABLE_FLOATING:
 888                val = SI5351_CLK_DISABLE_STATE_FLOAT;
 889                break;
 890        case SI5351_DISABLE_NEVER:
 891                val = SI5351_CLK_DISABLE_STATE_NEVER;
 892                break;
 893        default:
 894                return 0;
 895        }
 896
 897        si5351_set_bits(drvdata, reg, mask, val << shift);
 898
 899        return 0;
 900}
 901
 902static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
 903{
 904        u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
 905        u8 mask = val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
 906                                                       SI5351_PLL_RESET_A;
 907        unsigned int v;
 908        int err;
 909
 910        switch (val & SI5351_CLK_INPUT_MASK) {
 911        case SI5351_CLK_INPUT_XTAL:
 912        case SI5351_CLK_INPUT_CLKIN:
 913                return;  /* pll not used, no need to reset */
 914        }
 915
 916        si5351_reg_write(drvdata, SI5351_PLL_RESET, mask);
 917
 918        err = regmap_read_poll_timeout(drvdata->regmap, SI5351_PLL_RESET, v,
 919                                 !(v & mask), 0, 20000);
 920        if (err < 0)
 921                dev_err(&drvdata->client->dev, "Reset bit didn't clear\n");
 922
 923        dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
 924                __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
 925                (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
 926}
 927
 928static int si5351_clkout_prepare(struct clk_hw *hw)
 929{
 930        struct si5351_hw_data *hwdata =
 931                container_of(hw, struct si5351_hw_data, hw);
 932        struct si5351_platform_data *pdata =
 933                hwdata->drvdata->client->dev.platform_data;
 934
 935        si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
 936                        SI5351_CLK_POWERDOWN, 0);
 937
 938        /*
 939         * Do a pll soft reset on the parent pll -- needed to get a
 940         * deterministic phase relationship between the output clocks.
 941         */
 942        if (pdata->clkout[hwdata->num].pll_reset)
 943                _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
 944
 945        si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
 946                        (1 << hwdata->num), 0);
 947        return 0;
 948}
 949
 950static void si5351_clkout_unprepare(struct clk_hw *hw)
 951{
 952        struct si5351_hw_data *hwdata =
 953                container_of(hw, struct si5351_hw_data, hw);
 954
 955        si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
 956                        SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
 957        si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
 958                        (1 << hwdata->num), (1 << hwdata->num));
 959}
 960
 961static u8 si5351_clkout_get_parent(struct clk_hw *hw)
 962{
 963        struct si5351_hw_data *hwdata =
 964                container_of(hw, struct si5351_hw_data, hw);
 965        int index = 0;
 966        unsigned char val;
 967
 968        val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
 969        switch (val & SI5351_CLK_INPUT_MASK) {
 970        case SI5351_CLK_INPUT_MULTISYNTH_N:
 971                index = 0;
 972                break;
 973        case SI5351_CLK_INPUT_MULTISYNTH_0_4:
 974                index = 1;
 975                break;
 976        case SI5351_CLK_INPUT_XTAL:
 977                index = 2;
 978                break;
 979        case SI5351_CLK_INPUT_CLKIN:
 980                index = 3;
 981                break;
 982        }
 983
 984        return index;
 985}
 986
 987static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
 988{
 989        struct si5351_hw_data *hwdata =
 990                container_of(hw, struct si5351_hw_data, hw);
 991        enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
 992
 993        switch (index) {
 994        case 0:
 995                parent = SI5351_CLKOUT_SRC_MSYNTH_N;
 996                break;
 997        case 1:
 998                parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
 999                break;
1000        case 2:
1001                parent = SI5351_CLKOUT_SRC_XTAL;
1002                break;
1003        case 3:
1004                parent = SI5351_CLKOUT_SRC_CLKIN;
1005                break;
1006        }
1007
1008        return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
1009}
1010
1011static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
1012                                               unsigned long parent_rate)
1013{
1014        struct si5351_hw_data *hwdata =
1015                container_of(hw, struct si5351_hw_data, hw);
1016        unsigned char reg;
1017        unsigned char rdiv;
1018
1019        if (hwdata->num <= 5)
1020                reg = si5351_msynth_params_address(hwdata->num) + 2;
1021        else
1022                reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
1023
1024        rdiv = si5351_reg_read(hwdata->drvdata, reg);
1025        if (hwdata->num == 6) {
1026                rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
1027        } else {
1028                rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
1029                rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
1030        }
1031
1032        return parent_rate >> rdiv;
1033}
1034
1035static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
1036                                     unsigned long *parent_rate)
1037{
1038        struct si5351_hw_data *hwdata =
1039                container_of(hw, struct si5351_hw_data, hw);
1040        unsigned char rdiv;
1041
1042        /* clkout6/7 can only handle output freqencies < 150MHz */
1043        if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
1044                rate = SI5351_CLKOUT67_MAX_FREQ;
1045
1046        /* clkout freqency is 8kHz - 160MHz */
1047        if (rate > SI5351_CLKOUT_MAX_FREQ)
1048                rate = SI5351_CLKOUT_MAX_FREQ;
1049        if (rate < SI5351_CLKOUT_MIN_FREQ)
1050                rate = SI5351_CLKOUT_MIN_FREQ;
1051
1052        /* request frequency if multisync master */
1053        if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
1054                /* use r divider for frequencies below 1MHz */
1055                rdiv = SI5351_OUTPUT_CLK_DIV_1;
1056                while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
1057                       rdiv < SI5351_OUTPUT_CLK_DIV_128) {
1058                        rdiv += 1;
1059                        rate *= 2;
1060                }
1061                *parent_rate = rate;
1062        } else {
1063                unsigned long new_rate, new_err, err;
1064
1065                /* round to closed rdiv */
1066                rdiv = SI5351_OUTPUT_CLK_DIV_1;
1067                new_rate = *parent_rate;
1068                err = abs(new_rate - rate);
1069                do {
1070                        new_rate >>= 1;
1071                        new_err = abs(new_rate - rate);
1072                        if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1073                                break;
1074                        rdiv++;
1075                        err = new_err;
1076                } while (1);
1077        }
1078        rate = *parent_rate >> rdiv;
1079
1080        dev_dbg(&hwdata->drvdata->client->dev,
1081                "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1082                __func__, clk_hw_get_name(hw), (1 << rdiv),
1083                *parent_rate, rate);
1084
1085        return rate;
1086}
1087
1088static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1089                                  unsigned long parent_rate)
1090{
1091        struct si5351_hw_data *hwdata =
1092                container_of(hw, struct si5351_hw_data, hw);
1093        unsigned long new_rate, new_err, err;
1094        unsigned char rdiv;
1095
1096        /* round to closed rdiv */
1097        rdiv = SI5351_OUTPUT_CLK_DIV_1;
1098        new_rate = parent_rate;
1099        err = abs(new_rate - rate);
1100        do {
1101                new_rate >>= 1;
1102                new_err = abs(new_rate - rate);
1103                if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1104                        break;
1105                rdiv++;
1106                err = new_err;
1107        } while (1);
1108
1109        /* write output divider */
1110        switch (hwdata->num) {
1111        case 6:
1112                si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1113                                SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
1114                break;
1115        case 7:
1116                si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1117                                SI5351_OUTPUT_CLK_DIV_MASK,
1118                                rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1119                break;
1120        default:
1121                si5351_set_bits(hwdata->drvdata,
1122                                si5351_msynth_params_address(hwdata->num) + 2,
1123                                SI5351_OUTPUT_CLK_DIV_MASK,
1124                                rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1125        }
1126
1127        /* powerup clkout */
1128        si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
1129                        SI5351_CLK_POWERDOWN, 0);
1130
1131        dev_dbg(&hwdata->drvdata->client->dev,
1132                "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1133                __func__, clk_hw_get_name(hw), (1 << rdiv),
1134                parent_rate, rate);
1135
1136        return 0;
1137}
1138
1139static const struct clk_ops si5351_clkout_ops = {
1140        .prepare = si5351_clkout_prepare,
1141        .unprepare = si5351_clkout_unprepare,
1142        .set_parent = si5351_clkout_set_parent,
1143        .get_parent = si5351_clkout_get_parent,
1144        .recalc_rate = si5351_clkout_recalc_rate,
1145        .round_rate = si5351_clkout_round_rate,
1146        .set_rate = si5351_clkout_set_rate,
1147};
1148
1149/*
1150 * Si5351 i2c probe and DT
1151 */
1152#ifdef CONFIG_OF
1153static const struct of_device_id si5351_dt_ids[] = {
1154        { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
1155        { .compatible = "silabs,si5351a-msop",
1156                                         .data = (void *)SI5351_VARIANT_A3, },
1157        { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
1158        { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
1159        { }
1160};
1161MODULE_DEVICE_TABLE(of, si5351_dt_ids);
1162
1163static int si5351_dt_parse(struct i2c_client *client,
1164                           enum si5351_variant variant)
1165{
1166        struct device_node *child, *np = client->dev.of_node;
1167        struct si5351_platform_data *pdata;
1168        struct property *prop;
1169        const __be32 *p;
1170        int num = 0;
1171        u32 val;
1172
1173        if (np == NULL)
1174                return 0;
1175
1176        pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1177        if (!pdata)
1178                return -ENOMEM;
1179
1180        /*
1181         * property silabs,pll-source : <num src>, [<..>]
1182         * allow to selectively set pll source
1183         */
1184        of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
1185                if (num >= 2) {
1186                        dev_err(&client->dev,
1187                                "invalid pll %d on pll-source prop\n", num);
1188                        return -EINVAL;
1189                }
1190
1191                p = of_prop_next_u32(prop, p, &val);
1192                if (!p) {
1193                        dev_err(&client->dev,
1194                                "missing pll-source for pll %d\n", num);
1195                        return -EINVAL;
1196                }
1197
1198                switch (val) {
1199                case 0:
1200                        pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
1201                        break;
1202                case 1:
1203                        if (variant != SI5351_VARIANT_C) {
1204                                dev_err(&client->dev,
1205                                        "invalid parent %d for pll %d\n",
1206                                        val, num);
1207                                return -EINVAL;
1208                        }
1209                        pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
1210                        break;
1211                default:
1212                        dev_err(&client->dev,
1213                                 "invalid parent %d for pll %d\n", val, num);
1214                        return -EINVAL;
1215                }
1216        }
1217
1218        /* per clkout properties */
1219        for_each_child_of_node(np, child) {
1220                if (of_property_read_u32(child, "reg", &num)) {
1221                        dev_err(&client->dev, "missing reg property of %pOFn\n",
1222                                child);
1223                        goto put_child;
1224                }
1225
1226                if (num >= 8 ||
1227                    (variant == SI5351_VARIANT_A3 && num >= 3)) {
1228                        dev_err(&client->dev, "invalid clkout %d\n", num);
1229                        goto put_child;
1230                }
1231
1232                if (!of_property_read_u32(child, "silabs,multisynth-source",
1233                                          &val)) {
1234                        switch (val) {
1235                        case 0:
1236                                pdata->clkout[num].multisynth_src =
1237                                        SI5351_MULTISYNTH_SRC_VCO0;
1238                                break;
1239                        case 1:
1240                                pdata->clkout[num].multisynth_src =
1241                                        SI5351_MULTISYNTH_SRC_VCO1;
1242                                break;
1243                        default:
1244                                dev_err(&client->dev,
1245                                        "invalid parent %d for multisynth %d\n",
1246                                        val, num);
1247                                goto put_child;
1248                        }
1249                }
1250
1251                if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
1252                        switch (val) {
1253                        case 0:
1254                                pdata->clkout[num].clkout_src =
1255                                        SI5351_CLKOUT_SRC_MSYNTH_N;
1256                                break;
1257                        case 1:
1258                                pdata->clkout[num].clkout_src =
1259                                        SI5351_CLKOUT_SRC_MSYNTH_0_4;
1260                                break;
1261                        case 2:
1262                                pdata->clkout[num].clkout_src =
1263                                        SI5351_CLKOUT_SRC_XTAL;
1264                                break;
1265                        case 3:
1266                                if (variant != SI5351_VARIANT_C) {
1267                                        dev_err(&client->dev,
1268                                                "invalid parent %d for clkout %d\n",
1269                                                val, num);
1270                                        goto put_child;
1271                                }
1272                                pdata->clkout[num].clkout_src =
1273                                        SI5351_CLKOUT_SRC_CLKIN;
1274                                break;
1275                        default:
1276                                dev_err(&client->dev,
1277                                        "invalid parent %d for clkout %d\n",
1278                                        val, num);
1279                                goto put_child;
1280                        }
1281                }
1282
1283                if (!of_property_read_u32(child, "silabs,drive-strength",
1284                                          &val)) {
1285                        switch (val) {
1286                        case SI5351_DRIVE_2MA:
1287                        case SI5351_DRIVE_4MA:
1288                        case SI5351_DRIVE_6MA:
1289                        case SI5351_DRIVE_8MA:
1290                                pdata->clkout[num].drive = val;
1291                                break;
1292                        default:
1293                                dev_err(&client->dev,
1294                                        "invalid drive strength %d for clkout %d\n",
1295                                        val, num);
1296                                goto put_child;
1297                        }
1298                }
1299
1300                if (!of_property_read_u32(child, "silabs,disable-state",
1301                                          &val)) {
1302                        switch (val) {
1303                        case 0:
1304                                pdata->clkout[num].disable_state =
1305                                        SI5351_DISABLE_LOW;
1306                                break;
1307                        case 1:
1308                                pdata->clkout[num].disable_state =
1309                                        SI5351_DISABLE_HIGH;
1310                                break;
1311                        case 2:
1312                                pdata->clkout[num].disable_state =
1313                                        SI5351_DISABLE_FLOATING;
1314                                break;
1315                        case 3:
1316                                pdata->clkout[num].disable_state =
1317                                        SI5351_DISABLE_NEVER;
1318                                break;
1319                        default:
1320                                dev_err(&client->dev,
1321                                        "invalid disable state %d for clkout %d\n",
1322                                        val, num);
1323                                goto put_child;
1324                        }
1325                }
1326
1327                if (!of_property_read_u32(child, "clock-frequency", &val))
1328                        pdata->clkout[num].rate = val;
1329
1330                pdata->clkout[num].pll_master =
1331                        of_property_read_bool(child, "silabs,pll-master");
1332
1333                pdata->clkout[num].pll_reset =
1334                        of_property_read_bool(child, "silabs,pll-reset");
1335        }
1336        client->dev.platform_data = pdata;
1337
1338        return 0;
1339put_child:
1340        of_node_put(child);
1341        return -EINVAL;
1342}
1343
1344static struct clk_hw *
1345si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1346{
1347        struct si5351_driver_data *drvdata = data;
1348        unsigned int idx = clkspec->args[0];
1349
1350        if (idx >= drvdata->num_clkout) {
1351                pr_err("%s: invalid index %u\n", __func__, idx);
1352                return ERR_PTR(-EINVAL);
1353        }
1354
1355        return &drvdata->clkout[idx].hw;
1356}
1357#else
1358static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
1359{
1360        return 0;
1361}
1362
1363static struct clk_hw *
1364si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1365{
1366        return NULL;
1367}
1368#endif /* CONFIG_OF */
1369
1370static int si5351_i2c_probe(struct i2c_client *client,
1371                            const struct i2c_device_id *id)
1372{
1373        enum si5351_variant variant = (enum si5351_variant)id->driver_data;
1374        struct si5351_platform_data *pdata;
1375        struct si5351_driver_data *drvdata;
1376        struct clk_init_data init;
1377        const char *parent_names[4];
1378        u8 num_parents, num_clocks;
1379        int ret, n;
1380
1381        ret = si5351_dt_parse(client, variant);
1382        if (ret)
1383                return ret;
1384
1385        pdata = client->dev.platform_data;
1386        if (!pdata)
1387                return -EINVAL;
1388
1389        drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
1390        if (!drvdata)
1391                return -ENOMEM;
1392
1393        i2c_set_clientdata(client, drvdata);
1394        drvdata->client = client;
1395        drvdata->variant = variant;
1396        drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
1397        drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
1398
1399        if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
1400            PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
1401                return -EPROBE_DEFER;
1402
1403        /*
1404         * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
1405         *   VARIANT_C can have CLKIN instead.
1406         */
1407        if (IS_ERR(drvdata->pxtal) &&
1408            (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
1409                dev_err(&client->dev, "missing parent clock\n");
1410                return -EINVAL;
1411        }
1412
1413        drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
1414        if (IS_ERR(drvdata->regmap)) {
1415                dev_err(&client->dev, "failed to allocate register map\n");
1416                return PTR_ERR(drvdata->regmap);
1417        }
1418
1419        /* Disable interrupts */
1420        si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
1421        /* Ensure pll select is on XTAL for Si5351A/B */
1422        if (drvdata->variant != SI5351_VARIANT_C)
1423                si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
1424                                SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
1425
1426        /* setup clock configuration */
1427        for (n = 0; n < 2; n++) {
1428                ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
1429                if (ret) {
1430                        dev_err(&client->dev,
1431                                "failed to reparent pll %d to %d\n",
1432                                n, pdata->pll_src[n]);
1433                        return ret;
1434                }
1435        }
1436
1437        for (n = 0; n < 8; n++) {
1438                ret = _si5351_msynth_reparent(drvdata, n,
1439                                              pdata->clkout[n].multisynth_src);
1440                if (ret) {
1441                        dev_err(&client->dev,
1442                                "failed to reparent multisynth %d to %d\n",
1443                                n, pdata->clkout[n].multisynth_src);
1444                        return ret;
1445                }
1446
1447                ret = _si5351_clkout_reparent(drvdata, n,
1448                                              pdata->clkout[n].clkout_src);
1449                if (ret) {
1450                        dev_err(&client->dev,
1451                                "failed to reparent clkout %d to %d\n",
1452                                n, pdata->clkout[n].clkout_src);
1453                        return ret;
1454                }
1455
1456                ret = _si5351_clkout_set_drive_strength(drvdata, n,
1457                                                        pdata->clkout[n].drive);
1458                if (ret) {
1459                        dev_err(&client->dev,
1460                                "failed set drive strength of clkout%d to %d\n",
1461                                n, pdata->clkout[n].drive);
1462                        return ret;
1463                }
1464
1465                ret = _si5351_clkout_set_disable_state(drvdata, n,
1466                                                pdata->clkout[n].disable_state);
1467                if (ret) {
1468                        dev_err(&client->dev,
1469                                "failed set disable state of clkout%d to %d\n",
1470                                n, pdata->clkout[n].disable_state);
1471                        return ret;
1472                }
1473        }
1474
1475        /* register xtal input clock gate */
1476        memset(&init, 0, sizeof(init));
1477        init.name = si5351_input_names[0];
1478        init.ops = &si5351_xtal_ops;
1479        init.flags = 0;
1480        if (!IS_ERR(drvdata->pxtal)) {
1481                drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
1482                init.parent_names = &drvdata->pxtal_name;
1483                init.num_parents = 1;
1484        }
1485        drvdata->xtal.init = &init;
1486        ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
1487        if (ret) {
1488                dev_err(&client->dev, "unable to register %s\n", init.name);
1489                return ret;
1490        }
1491
1492        /* register clkin input clock gate */
1493        if (drvdata->variant == SI5351_VARIANT_C) {
1494                memset(&init, 0, sizeof(init));
1495                init.name = si5351_input_names[1];
1496                init.ops = &si5351_clkin_ops;
1497                if (!IS_ERR(drvdata->pclkin)) {
1498                        drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
1499                        init.parent_names = &drvdata->pclkin_name;
1500                        init.num_parents = 1;
1501                }
1502                drvdata->clkin.init = &init;
1503                ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);
1504                if (ret) {
1505                        dev_err(&client->dev, "unable to register %s\n",
1506                                init.name);
1507                        return ret;
1508                }
1509        }
1510
1511        /* Si5351C allows to mux either xtal or clkin to PLL input */
1512        num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
1513        parent_names[0] = si5351_input_names[0];
1514        parent_names[1] = si5351_input_names[1];
1515
1516        /* register PLLA */
1517        drvdata->pll[0].num = 0;
1518        drvdata->pll[0].drvdata = drvdata;
1519        drvdata->pll[0].hw.init = &init;
1520        memset(&init, 0, sizeof(init));
1521        init.name = si5351_pll_names[0];
1522        init.ops = &si5351_pll_ops;
1523        init.flags = 0;
1524        init.parent_names = parent_names;
1525        init.num_parents = num_parents;
1526        ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
1527        if (ret) {
1528                dev_err(&client->dev, "unable to register %s\n", init.name);
1529                return ret;
1530        }
1531
1532        /* register PLLB or VXCO (Si5351B) */
1533        drvdata->pll[1].num = 1;
1534        drvdata->pll[1].drvdata = drvdata;
1535        drvdata->pll[1].hw.init = &init;
1536        memset(&init, 0, sizeof(init));
1537        if (drvdata->variant == SI5351_VARIANT_B) {
1538                init.name = si5351_pll_names[2];
1539                init.ops = &si5351_vxco_ops;
1540                init.flags = 0;
1541                init.parent_names = NULL;
1542                init.num_parents = 0;
1543        } else {
1544                init.name = si5351_pll_names[1];
1545                init.ops = &si5351_pll_ops;
1546                init.flags = 0;
1547                init.parent_names = parent_names;
1548                init.num_parents = num_parents;
1549        }
1550        ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
1551        if (ret) {
1552                dev_err(&client->dev, "unable to register %s\n", init.name);
1553                return ret;
1554        }
1555
1556        /* register clk multisync and clk out divider */
1557        num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
1558        parent_names[0] = si5351_pll_names[0];
1559        if (drvdata->variant == SI5351_VARIANT_B)
1560                parent_names[1] = si5351_pll_names[2];
1561        else
1562                parent_names[1] = si5351_pll_names[1];
1563
1564        drvdata->msynth = devm_kcalloc(&client->dev, num_clocks,
1565                                       sizeof(*drvdata->msynth), GFP_KERNEL);
1566        drvdata->clkout = devm_kcalloc(&client->dev, num_clocks,
1567                                       sizeof(*drvdata->clkout), GFP_KERNEL);
1568        drvdata->num_clkout = num_clocks;
1569
1570        if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
1571                ret = -ENOMEM;
1572                return ret;
1573        }
1574
1575        for (n = 0; n < num_clocks; n++) {
1576                drvdata->msynth[n].num = n;
1577                drvdata->msynth[n].drvdata = drvdata;
1578                drvdata->msynth[n].hw.init = &init;
1579                memset(&init, 0, sizeof(init));
1580                init.name = si5351_msynth_names[n];
1581                init.ops = &si5351_msynth_ops;
1582                init.flags = 0;
1583                if (pdata->clkout[n].pll_master)
1584                        init.flags |= CLK_SET_RATE_PARENT;
1585                init.parent_names = parent_names;
1586                init.num_parents = 2;
1587                ret = devm_clk_hw_register(&client->dev,
1588                                           &drvdata->msynth[n].hw);
1589                if (ret) {
1590                        dev_err(&client->dev, "unable to register %s\n",
1591                                init.name);
1592                        return ret;
1593                }
1594        }
1595
1596        num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
1597        parent_names[2] = si5351_input_names[0];
1598        parent_names[3] = si5351_input_names[1];
1599        for (n = 0; n < num_clocks; n++) {
1600                parent_names[0] = si5351_msynth_names[n];
1601                parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
1602                        si5351_msynth_names[4];
1603
1604                drvdata->clkout[n].num = n;
1605                drvdata->clkout[n].drvdata = drvdata;
1606                drvdata->clkout[n].hw.init = &init;
1607                memset(&init, 0, sizeof(init));
1608                init.name = si5351_clkout_names[n];
1609                init.ops = &si5351_clkout_ops;
1610                init.flags = 0;
1611                if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
1612                        init.flags |= CLK_SET_RATE_PARENT;
1613                init.parent_names = parent_names;
1614                init.num_parents = num_parents;
1615                ret = devm_clk_hw_register(&client->dev,
1616                                           &drvdata->clkout[n].hw);
1617                if (ret) {
1618                        dev_err(&client->dev, "unable to register %s\n",
1619                                init.name);
1620                        return ret;
1621                }
1622
1623                /* set initial clkout rate */
1624                if (pdata->clkout[n].rate != 0) {
1625                        int ret;
1626                        ret = clk_set_rate(drvdata->clkout[n].hw.clk,
1627                                           pdata->clkout[n].rate);
1628                        if (ret != 0) {
1629                                dev_err(&client->dev, "Cannot set rate : %d\n",
1630                                        ret);
1631                        }
1632                }
1633        }
1634
1635        ret = of_clk_add_hw_provider(client->dev.of_node, si53351_of_clk_get,
1636                                     drvdata);
1637        if (ret) {
1638                dev_err(&client->dev, "unable to add clk provider\n");
1639                return ret;
1640        }
1641
1642        return 0;
1643}
1644
1645static int si5351_i2c_remove(struct i2c_client *client)
1646{
1647        of_clk_del_provider(client->dev.of_node);
1648
1649        return 0;
1650}
1651
1652static const struct i2c_device_id si5351_i2c_ids[] = {
1653        { "si5351a", SI5351_VARIANT_A },
1654        { "si5351a-msop", SI5351_VARIANT_A3 },
1655        { "si5351b", SI5351_VARIANT_B },
1656        { "si5351c", SI5351_VARIANT_C },
1657        { }
1658};
1659MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
1660
1661static struct i2c_driver si5351_driver = {
1662        .driver = {
1663                .name = "si5351",
1664                .of_match_table = of_match_ptr(si5351_dt_ids),
1665        },
1666        .probe = si5351_i2c_probe,
1667        .remove = si5351_i2c_remove,
1668        .id_table = si5351_i2c_ids,
1669};
1670module_i2c_driver(si5351_driver);
1671
1672MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
1673MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
1674MODULE_LICENSE("GPL");
1675