linux/drivers/clk/at91/clk-sam9x60-pll.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  Copyright (C) 2019 Microchip Technology Inc.
   4 *
   5 */
   6
   7#include <linux/bitfield.h>
   8#include <linux/clk-provider.h>
   9#include <linux/clkdev.h>
  10#include <linux/clk/at91_pmc.h>
  11#include <linux/of.h>
  12#include <linux/mfd/syscon.h>
  13#include <linux/regmap.h>
  14
  15#include "pmc.h"
  16
  17#define PMC_PLL_CTRL0_DIV_MSK   GENMASK(7, 0)
  18#define PMC_PLL_CTRL1_MUL_MSK   GENMASK(31, 24)
  19#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
  20
  21#define PLL_DIV_MAX             (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
  22#define UPLL_DIV                2
  23#define PLL_MUL_MAX             (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
  24
  25#define FCORE_MIN               (600000000)
  26#define FCORE_MAX               (1200000000)
  27
  28#define PLL_MAX_ID              7
  29
  30struct sam9x60_pll_core {
  31        struct regmap *regmap;
  32        spinlock_t *lock;
  33        const struct clk_pll_characteristics *characteristics;
  34        const struct clk_pll_layout *layout;
  35        struct clk_hw hw;
  36        u8 id;
  37};
  38
  39struct sam9x60_frac {
  40        struct sam9x60_pll_core core;
  41        u32 frac;
  42        u16 mul;
  43};
  44
  45struct sam9x60_div {
  46        struct sam9x60_pll_core core;
  47        u8 div;
  48};
  49
  50#define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
  51#define to_sam9x60_frac(core)   container_of(core, struct sam9x60_frac, core)
  52#define to_sam9x60_div(core)    container_of(core, struct sam9x60_div, core)
  53
  54static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
  55{
  56        unsigned int status;
  57
  58        regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
  59
  60        return !!(status & BIT(id));
  61}
  62
  63static bool sam9x60_frac_pll_ready(struct regmap *regmap, u8 id)
  64{
  65        return sam9x60_pll_ready(regmap, id);
  66}
  67
  68static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
  69                                                  unsigned long parent_rate)
  70{
  71        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
  72        struct sam9x60_frac *frac = to_sam9x60_frac(core);
  73
  74        return (parent_rate * (frac->mul + 1) +
  75                ((u64)parent_rate * frac->frac >> 22));
  76}
  77
  78static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
  79{
  80        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
  81        struct sam9x60_frac *frac = to_sam9x60_frac(core);
  82        struct regmap *regmap = core->regmap;
  83        unsigned int val, cfrac, cmul;
  84        unsigned long flags;
  85
  86        spin_lock_irqsave(core->lock, flags);
  87
  88        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
  89                           AT91_PMC_PLL_UPDT_ID_MSK, core->id);
  90        regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
  91        cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
  92        cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
  93
  94        if (sam9x60_frac_pll_ready(regmap, core->id) &&
  95            (cmul == frac->mul && cfrac == frac->frac))
  96                goto unlock;
  97
  98        /* Recommended value for PMC_PLL_ACR */
  99        if (core->characteristics->upll)
 100                val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
 101        else
 102                val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
 103        regmap_write(regmap, AT91_PMC_PLL_ACR, val);
 104
 105        regmap_write(regmap, AT91_PMC_PLL_CTRL1,
 106                     (frac->mul << core->layout->mul_shift) |
 107                     (frac->frac << core->layout->frac_shift));
 108
 109        if (core->characteristics->upll) {
 110                /* Enable the UTMI internal bandgap */
 111                val |= AT91_PMC_PLL_ACR_UTMIBG;
 112                regmap_write(regmap, AT91_PMC_PLL_ACR, val);
 113
 114                udelay(10);
 115
 116                /* Enable the UTMI internal regulator */
 117                val |= AT91_PMC_PLL_ACR_UTMIVR;
 118                regmap_write(regmap, AT91_PMC_PLL_ACR, val);
 119
 120                udelay(10);
 121        }
 122
 123        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 124                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 125                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 126
 127        regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 128                           AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
 129                           AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
 130
 131        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 132                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 133                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 134
 135        while (!sam9x60_pll_ready(regmap, core->id))
 136                cpu_relax();
 137
 138unlock:
 139        spin_unlock_irqrestore(core->lock, flags);
 140
 141        return 0;
 142}
 143
 144static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
 145{
 146        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 147        struct regmap *regmap = core->regmap;
 148        unsigned long flags;
 149
 150        spin_lock_irqsave(core->lock, flags);
 151
 152        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 153                           AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 154
 155        regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
 156
 157        if (core->characteristics->upll)
 158                regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
 159                                   AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
 160
 161        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 162                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 163                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 164
 165        spin_unlock_irqrestore(core->lock, flags);
 166}
 167
 168static int sam9x60_frac_pll_is_prepared(struct clk_hw *hw)
 169{
 170        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 171
 172        return sam9x60_pll_ready(core->regmap, core->id);
 173}
 174
 175static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
 176                                              unsigned long rate,
 177                                              unsigned long parent_rate,
 178                                              bool update)
 179{
 180        struct sam9x60_frac *frac = to_sam9x60_frac(core);
 181        unsigned long tmprate, remainder;
 182        unsigned long nmul = 0;
 183        unsigned long nfrac = 0;
 184
 185        if (rate < FCORE_MIN || rate > FCORE_MAX)
 186                return -ERANGE;
 187
 188        /*
 189         * Calculate the multiplier associated with the current
 190         * divider that provide the closest rate to the requested one.
 191         */
 192        nmul = mult_frac(rate, 1, parent_rate);
 193        tmprate = mult_frac(parent_rate, nmul, 1);
 194        remainder = rate - tmprate;
 195
 196        if (remainder) {
 197                nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22),
 198                                              parent_rate);
 199
 200                tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate,
 201                                                 (1 << 22));
 202        }
 203
 204        /* Check if resulted rate is a valid.  */
 205        if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
 206                return -ERANGE;
 207
 208        if (update) {
 209                frac->mul = nmul - 1;
 210                frac->frac = nfrac;
 211        }
 212
 213        return tmprate;
 214}
 215
 216static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 217                                        unsigned long *parent_rate)
 218{
 219        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 220
 221        return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);
 222}
 223
 224static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 225                                     unsigned long parent_rate)
 226{
 227        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 228
 229        return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
 230}
 231
 232static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
 233                                         unsigned long parent_rate)
 234{
 235        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 236        struct sam9x60_frac *frac = to_sam9x60_frac(core);
 237        struct regmap *regmap = core->regmap;
 238        unsigned long irqflags;
 239        unsigned int val, cfrac, cmul;
 240        long ret;
 241
 242        ret = sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
 243        if (ret <= 0)
 244                return ret;
 245
 246        spin_lock_irqsave(core->lock, irqflags);
 247
 248        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
 249                           core->id);
 250        regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
 251        cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
 252        cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
 253
 254        if (cmul == frac->mul && cfrac == frac->frac)
 255                goto unlock;
 256
 257        regmap_write(regmap, AT91_PMC_PLL_CTRL1,
 258                     (frac->mul << core->layout->mul_shift) |
 259                     (frac->frac << core->layout->frac_shift));
 260
 261        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 262                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 263                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 264
 265        regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 266                           AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
 267                           AT91_PMC_PLL_CTRL0_ENLOCK |
 268                           AT91_PMC_PLL_CTRL0_ENPLL);
 269
 270        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 271                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 272                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 273
 274        while (!sam9x60_pll_ready(regmap, core->id))
 275                cpu_relax();
 276
 277unlock:
 278        spin_unlock_irqrestore(core->lock, irqflags);
 279
 280        return ret;
 281}
 282
 283static const struct clk_ops sam9x60_frac_pll_ops = {
 284        .prepare = sam9x60_frac_pll_prepare,
 285        .unprepare = sam9x60_frac_pll_unprepare,
 286        .is_prepared = sam9x60_frac_pll_is_prepared,
 287        .recalc_rate = sam9x60_frac_pll_recalc_rate,
 288        .round_rate = sam9x60_frac_pll_round_rate,
 289        .set_rate = sam9x60_frac_pll_set_rate,
 290};
 291
 292static const struct clk_ops sam9x60_frac_pll_ops_chg = {
 293        .prepare = sam9x60_frac_pll_prepare,
 294        .unprepare = sam9x60_frac_pll_unprepare,
 295        .is_prepared = sam9x60_frac_pll_is_prepared,
 296        .recalc_rate = sam9x60_frac_pll_recalc_rate,
 297        .round_rate = sam9x60_frac_pll_round_rate,
 298        .set_rate = sam9x60_frac_pll_set_rate_chg,
 299};
 300
 301static int sam9x60_div_pll_prepare(struct clk_hw *hw)
 302{
 303        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 304        struct sam9x60_div *div = to_sam9x60_div(core);
 305        struct regmap *regmap = core->regmap;
 306        unsigned long flags;
 307        unsigned int val, cdiv;
 308
 309        spin_lock_irqsave(core->lock, flags);
 310        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 311                           AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 312        regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 313        cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
 314
 315        /* Stop if enabled an nothing changed. */
 316        if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
 317                goto unlock;
 318
 319        regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 320                           core->layout->div_mask | core->layout->endiv_mask,
 321                           (div->div << core->layout->div_shift) |
 322                           (1 << core->layout->endiv_shift));
 323
 324        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 325                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 326                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 327
 328        while (!sam9x60_pll_ready(regmap, core->id))
 329                cpu_relax();
 330
 331unlock:
 332        spin_unlock_irqrestore(core->lock, flags);
 333
 334        return 0;
 335}
 336
 337static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
 338{
 339        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 340        struct regmap *regmap = core->regmap;
 341        unsigned long flags;
 342
 343        spin_lock_irqsave(core->lock, flags);
 344
 345        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 346                           AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 347
 348        regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 349                           core->layout->endiv_mask, 0);
 350
 351        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 352                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 353                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 354
 355        spin_unlock_irqrestore(core->lock, flags);
 356}
 357
 358static int sam9x60_div_pll_is_prepared(struct clk_hw *hw)
 359{
 360        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 361        struct regmap *regmap = core->regmap;
 362        unsigned long flags;
 363        unsigned int val;
 364
 365        spin_lock_irqsave(core->lock, flags);
 366
 367        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 368                           AT91_PMC_PLL_UPDT_ID_MSK, core->id);
 369        regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 370
 371        spin_unlock_irqrestore(core->lock, flags);
 372
 373        return !!(val & core->layout->endiv_mask);
 374}
 375
 376static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
 377                                                 unsigned long parent_rate)
 378{
 379        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 380        struct sam9x60_div *div = to_sam9x60_div(core);
 381
 382        return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
 383}
 384
 385static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
 386                                        unsigned long *parent_rate,
 387                                        unsigned long rate)
 388{
 389        const struct clk_pll_characteristics *characteristics =
 390                                                        core->characteristics;
 391        struct clk_hw *parent = clk_hw_get_parent(&core->hw);
 392        unsigned long tmp_rate, tmp_parent_rate, tmp_diff;
 393        long best_diff = -1, best_rate = -EINVAL;
 394        u32 divid;
 395
 396        if (!rate)
 397                return 0;
 398
 399        if (rate < characteristics->output[0].min ||
 400            rate > characteristics->output[0].max)
 401                return -ERANGE;
 402
 403        for (divid = 1; divid < core->layout->div_mask; divid++) {
 404                tmp_parent_rate = clk_hw_round_rate(parent, rate * divid);
 405                if (!tmp_parent_rate)
 406                        continue;
 407
 408                tmp_rate = DIV_ROUND_CLOSEST_ULL(tmp_parent_rate, divid);
 409                tmp_diff = abs(rate - tmp_rate);
 410
 411                if (best_diff < 0 || best_diff > tmp_diff) {
 412                        *parent_rate = tmp_parent_rate;
 413                        best_rate = tmp_rate;
 414                        best_diff = tmp_diff;
 415                }
 416
 417                if (!best_diff)
 418                        break;
 419        }
 420
 421        if (best_rate < characteristics->output[0].min ||
 422            best_rate > characteristics->output[0].max)
 423                return -ERANGE;
 424
 425        return best_rate;
 426}
 427
 428static long sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 429                                       unsigned long *parent_rate)
 430{
 431        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 432
 433        return sam9x60_div_pll_compute_div(core, parent_rate, rate);
 434}
 435
 436static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 437                                    unsigned long parent_rate)
 438{
 439        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 440        struct sam9x60_div *div = to_sam9x60_div(core);
 441
 442        div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
 443
 444        return 0;
 445}
 446
 447static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate,
 448                                        unsigned long parent_rate)
 449{
 450        struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
 451        struct sam9x60_div *div = to_sam9x60_div(core);
 452        struct regmap *regmap = core->regmap;
 453        unsigned long irqflags;
 454        unsigned int val, cdiv;
 455
 456        div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
 457
 458        spin_lock_irqsave(core->lock, irqflags);
 459        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
 460                           core->id);
 461        regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 462        cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
 463
 464        /* Stop if nothing changed. */
 465        if (cdiv == div->div)
 466                goto unlock;
 467
 468        regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
 469                           core->layout->div_mask,
 470                           (div->div << core->layout->div_shift));
 471
 472        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 473                           AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
 474                           AT91_PMC_PLL_UPDT_UPDATE | core->id);
 475
 476        while (!sam9x60_pll_ready(regmap, core->id))
 477                cpu_relax();
 478
 479unlock:
 480        spin_unlock_irqrestore(core->lock, irqflags);
 481
 482        return 0;
 483}
 484
 485static const struct clk_ops sam9x60_div_pll_ops = {
 486        .prepare = sam9x60_div_pll_prepare,
 487        .unprepare = sam9x60_div_pll_unprepare,
 488        .is_prepared = sam9x60_div_pll_is_prepared,
 489        .recalc_rate = sam9x60_div_pll_recalc_rate,
 490        .round_rate = sam9x60_div_pll_round_rate,
 491        .set_rate = sam9x60_div_pll_set_rate,
 492};
 493
 494static const struct clk_ops sam9x60_div_pll_ops_chg = {
 495        .prepare = sam9x60_div_pll_prepare,
 496        .unprepare = sam9x60_div_pll_unprepare,
 497        .is_prepared = sam9x60_div_pll_is_prepared,
 498        .recalc_rate = sam9x60_div_pll_recalc_rate,
 499        .round_rate = sam9x60_div_pll_round_rate,
 500        .set_rate = sam9x60_div_pll_set_rate_chg,
 501};
 502
 503struct clk_hw * __init
 504sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
 505                              const char *name, const char *parent_name,
 506                              struct clk_hw *parent_hw, u8 id,
 507                              const struct clk_pll_characteristics *characteristics,
 508                              const struct clk_pll_layout *layout, u32 flags)
 509{
 510        struct sam9x60_frac *frac;
 511        struct clk_hw *hw;
 512        struct clk_init_data init;
 513        unsigned long parent_rate, irqflags;
 514        unsigned int val;
 515        int ret;
 516
 517        if (id > PLL_MAX_ID || !lock || !parent_hw)
 518                return ERR_PTR(-EINVAL);
 519
 520        frac = kzalloc(sizeof(*frac), GFP_KERNEL);
 521        if (!frac)
 522                return ERR_PTR(-ENOMEM);
 523
 524        init.name = name;
 525        init.parent_names = &parent_name;
 526        init.num_parents = 1;
 527        if (flags & CLK_SET_RATE_GATE)
 528                init.ops = &sam9x60_frac_pll_ops;
 529        else
 530                init.ops = &sam9x60_frac_pll_ops_chg;
 531
 532        init.flags = flags;
 533
 534        frac->core.id = id;
 535        frac->core.hw.init = &init;
 536        frac->core.characteristics = characteristics;
 537        frac->core.layout = layout;
 538        frac->core.regmap = regmap;
 539        frac->core.lock = lock;
 540
 541        spin_lock_irqsave(frac->core.lock, irqflags);
 542        if (sam9x60_pll_ready(regmap, id)) {
 543                regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 544                                   AT91_PMC_PLL_UPDT_ID_MSK, id);
 545                regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
 546                frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
 547                frac->frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
 548        } else {
 549                /*
 550                 * This means the PLL is not setup by bootloaders. In this
 551                 * case we need to set the minimum rate for it. Otherwise
 552                 * a clock child of this PLL may be enabled before setting
 553                 * its rate leading to enabling this PLL with unsupported
 554                 * rate. This will lead to PLL not being locked at all.
 555                 */
 556                parent_rate = clk_hw_get_rate(parent_hw);
 557                if (!parent_rate) {
 558                        hw = ERR_PTR(-EINVAL);
 559                        goto free;
 560                }
 561
 562                ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
 563                                                        parent_rate, true);
 564                if (ret <= 0) {
 565                        hw = ERR_PTR(ret);
 566                        goto free;
 567                }
 568        }
 569        spin_unlock_irqrestore(frac->core.lock, irqflags);
 570
 571        hw = &frac->core.hw;
 572        ret = clk_hw_register(NULL, hw);
 573        if (ret) {
 574                kfree(frac);
 575                hw = ERR_PTR(ret);
 576        }
 577
 578        return hw;
 579
 580free:
 581        spin_unlock_irqrestore(frac->core.lock, irqflags);
 582        kfree(frac);
 583        return hw;
 584}
 585
 586struct clk_hw * __init
 587sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
 588                             const char *name, const char *parent_name, u8 id,
 589                             const struct clk_pll_characteristics *characteristics,
 590                             const struct clk_pll_layout *layout, u32 flags)
 591{
 592        struct sam9x60_div *div;
 593        struct clk_hw *hw;
 594        struct clk_init_data init;
 595        unsigned long irqflags;
 596        unsigned int val;
 597        int ret;
 598
 599        if (id > PLL_MAX_ID || !lock)
 600                return ERR_PTR(-EINVAL);
 601
 602        div = kzalloc(sizeof(*div), GFP_KERNEL);
 603        if (!div)
 604                return ERR_PTR(-ENOMEM);
 605
 606        init.name = name;
 607        init.parent_names = &parent_name;
 608        init.num_parents = 1;
 609        if (flags & CLK_SET_RATE_GATE)
 610                init.ops = &sam9x60_div_pll_ops;
 611        else
 612                init.ops = &sam9x60_div_pll_ops_chg;
 613        init.flags = flags;
 614
 615        div->core.id = id;
 616        div->core.hw.init = &init;
 617        div->core.characteristics = characteristics;
 618        div->core.layout = layout;
 619        div->core.regmap = regmap;
 620        div->core.lock = lock;
 621
 622        spin_lock_irqsave(div->core.lock, irqflags);
 623
 624        regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
 625                           AT91_PMC_PLL_UPDT_ID_MSK, id);
 626        regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
 627        div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
 628
 629        spin_unlock_irqrestore(div->core.lock, irqflags);
 630
 631        hw = &div->core.hw;
 632        ret = clk_hw_register(NULL, hw);
 633        if (ret) {
 634                kfree(div);
 635                hw = ERR_PTR(ret);
 636        }
 637
 638        return hw;
 639}
 640
 641