linux/drivers/acpi/cppc_acpi.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * CPPC (Collaborative Processor Performance Control) methods used by CPUfreq drivers.
   4 *
   5 * (C) Copyright 2014, 2015 Linaro Ltd.
   6 * Author: Ashwin Chaugule <ashwin.chaugule@linaro.org>
   7 *
   8 * CPPC describes a few methods for controlling CPU performance using
   9 * information from a per CPU table called CPC. This table is described in
  10 * the ACPI v5.0+ specification. The table consists of a list of
  11 * registers which may be memory mapped or hardware registers and also may
  12 * include some static integer values.
  13 *
  14 * CPU performance is on an abstract continuous scale as against a discretized
  15 * P-state scale which is tied to CPU frequency only. In brief, the basic
  16 * operation involves:
  17 *
  18 * - OS makes a CPU performance request. (Can provide min and max bounds)
  19 *
  20 * - Platform (such as BMC) is free to optimize request within requested bounds
  21 *   depending on power/thermal budgets etc.
  22 *
  23 * - Platform conveys its decision back to OS
  24 *
  25 * The communication between OS and platform occurs through another medium
  26 * called (PCC) Platform Communication Channel. This is a generic mailbox like
  27 * mechanism which includes doorbell semantics to indicate register updates.
  28 * See drivers/mailbox/pcc.c for details on PCC.
  29 *
  30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and
  31 * above specifications.
  32 */
  33
  34#define pr_fmt(fmt)     "ACPI CPPC: " fmt
  35
  36#include <linux/delay.h>
  37#include <linux/iopoll.h>
  38#include <linux/ktime.h>
  39#include <linux/rwsem.h>
  40#include <linux/wait.h>
  41#include <linux/topology.h>
  42
  43#include <acpi/cppc_acpi.h>
  44
  45struct cppc_pcc_data {
  46        struct mbox_chan *pcc_channel;
  47        void __iomem *pcc_comm_addr;
  48        bool pcc_channel_acquired;
  49        unsigned int deadline_us;
  50        unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
  51
  52        bool pending_pcc_write_cmd;     /* Any pending/batched PCC write cmds? */
  53        bool platform_owns_pcc;         /* Ownership of PCC subspace */
  54        unsigned int pcc_write_cnt;     /* Running count of PCC write commands */
  55
  56        /*
  57         * Lock to provide controlled access to the PCC channel.
  58         *
  59         * For performance critical usecases(currently cppc_set_perf)
  60         *      We need to take read_lock and check if channel belongs to OSPM
  61         * before reading or writing to PCC subspace
  62         *      We need to take write_lock before transferring the channel
  63         * ownership to the platform via a Doorbell
  64         *      This allows us to batch a number of CPPC requests if they happen
  65         * to originate in about the same time
  66         *
  67         * For non-performance critical usecases(init)
  68         *      Take write_lock for all purposes which gives exclusive access
  69         */
  70        struct rw_semaphore pcc_lock;
  71
  72        /* Wait queue for CPUs whose requests were batched */
  73        wait_queue_head_t pcc_write_wait_q;
  74        ktime_t last_cmd_cmpl_time;
  75        ktime_t last_mpar_reset;
  76        int mpar_count;
  77        int refcount;
  78};
  79
  80/* Array to represent the PCC channel per subspace ID */
  81static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
  82/* The cpu_pcc_subspace_idx contains per CPU subspace ID */
  83static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
  84
  85/*
  86 * The cpc_desc structure contains the ACPI register details
  87 * as described in the per CPU _CPC tables. The details
  88 * include the type of register (e.g. PCC, System IO, FFH etc.)
  89 * and destination addresses which lets us READ/WRITE CPU performance
  90 * information using the appropriate I/O methods.
  91 */
  92static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
  93
  94/* pcc mapped address + header size + offset within PCC subspace */
  95#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
  96                                                0x8 + (offs))
  97
  98/* Check if a CPC register is in PCC */
  99#define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER &&             \
 100                                (cpc)->cpc_entry.reg.space_id ==        \
 101                                ACPI_ADR_SPACE_PLATFORM_COMM)
 102
 103/* Evaluates to True if reg is a NULL register descriptor */
 104#define IS_NULL_REG(reg) ((reg)->space_id ==  ACPI_ADR_SPACE_SYSTEM_MEMORY && \
 105                                (reg)->address == 0 &&                  \
 106                                (reg)->bit_width == 0 &&                \
 107                                (reg)->bit_offset == 0 &&               \
 108                                (reg)->access_width == 0)
 109
 110/* Evaluates to True if an optional cpc field is supported */
 111#define CPC_SUPPORTED(cpc) ((cpc)->type == ACPI_TYPE_INTEGER ?          \
 112                                !!(cpc)->cpc_entry.int_value :          \
 113                                !IS_NULL_REG(&(cpc)->cpc_entry.reg))
 114/*
 115 * Arbitrary Retries in case the remote processor is slow to respond
 116 * to PCC commands. Keeping it high enough to cover emulators where
 117 * the processors run painfully slow.
 118 */
 119#define NUM_RETRIES 500ULL
 120
 121#define define_one_cppc_ro(_name)               \
 122static struct kobj_attribute _name =            \
 123__ATTR(_name, 0444, show_##_name, NULL)
 124
 125#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
 126
 127#define show_cppc_data(access_fn, struct_name, member_name)             \
 128        static ssize_t show_##member_name(struct kobject *kobj,         \
 129                                struct kobj_attribute *attr, char *buf) \
 130        {                                                               \
 131                struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);           \
 132                struct struct_name st_name = {0};                       \
 133                int ret;                                                \
 134                                                                        \
 135                ret = access_fn(cpc_ptr->cpu_id, &st_name);             \
 136                if (ret)                                                \
 137                        return ret;                                     \
 138                                                                        \
 139                return scnprintf(buf, PAGE_SIZE, "%llu\n",              \
 140                                (u64)st_name.member_name);              \
 141        }                                                               \
 142        define_one_cppc_ro(member_name)
 143
 144show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, highest_perf);
 145show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_perf);
 146show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_perf);
 147show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_nonlinear_perf);
 148show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq);
 149show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq);
 150
 151show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
 152show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
 153
 154static ssize_t show_feedback_ctrs(struct kobject *kobj,
 155                struct kobj_attribute *attr, char *buf)
 156{
 157        struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
 158        struct cppc_perf_fb_ctrs fb_ctrs = {0};
 159        int ret;
 160
 161        ret = cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs);
 162        if (ret)
 163                return ret;
 164
 165        return scnprintf(buf, PAGE_SIZE, "ref:%llu del:%llu\n",
 166                        fb_ctrs.reference, fb_ctrs.delivered);
 167}
 168define_one_cppc_ro(feedback_ctrs);
 169
 170static struct attribute *cppc_attrs[] = {
 171        &feedback_ctrs.attr,
 172        &reference_perf.attr,
 173        &wraparound_time.attr,
 174        &highest_perf.attr,
 175        &lowest_perf.attr,
 176        &lowest_nonlinear_perf.attr,
 177        &nominal_perf.attr,
 178        &nominal_freq.attr,
 179        &lowest_freq.attr,
 180        NULL
 181};
 182
 183static struct kobj_type cppc_ktype = {
 184        .sysfs_ops = &kobj_sysfs_ops,
 185        .default_attrs = cppc_attrs,
 186};
 187
 188static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
 189{
 190        int ret, status;
 191        struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 192        struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 193                pcc_ss_data->pcc_comm_addr;
 194
 195        if (!pcc_ss_data->platform_owns_pcc)
 196                return 0;
 197
 198        /*
 199         * Poll PCC status register every 3us(delay_us) for maximum of
 200         * deadline_us(timeout_us) until PCC command complete bit is set(cond)
 201         */
 202        ret = readw_relaxed_poll_timeout(&generic_comm_base->status, status,
 203                                        status & PCC_CMD_COMPLETE_MASK, 3,
 204                                        pcc_ss_data->deadline_us);
 205
 206        if (likely(!ret)) {
 207                pcc_ss_data->platform_owns_pcc = false;
 208                if (chk_err_bit && (status & PCC_ERROR_MASK))
 209                        ret = -EIO;
 210        }
 211
 212        if (unlikely(ret))
 213                pr_err("PCC check channel failed for ss: %d. ret=%d\n",
 214                       pcc_ss_id, ret);
 215
 216        return ret;
 217}
 218
 219/*
 220 * This function transfers the ownership of the PCC to the platform
 221 * So it must be called while holding write_lock(pcc_lock)
 222 */
 223static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
 224{
 225        int ret = -EIO, i;
 226        struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
 227        struct acpi_pcct_shared_memory __iomem *generic_comm_base =
 228                pcc_ss_data->pcc_comm_addr;
 229        unsigned int time_delta;
 230
 231        /*
 232         * For CMD_WRITE we know for a fact the caller should have checked
 233         * the channel before writing to PCC space
 234         */
 235        if (cmd == CMD_READ) {
 236                /*
 237                 * If there are pending cpc_writes, then we stole the channel
 238                 * before write completion, so first send a WRITE command to
 239                 * platform
 240                 */
 241                if (pcc_ss_data->pending_pcc_write_cmd)
 242                        send_pcc_cmd(pcc_ss_id, CMD_WRITE);
 243
 244                ret = check_pcc_chan(pcc_ss_id, false);
 245                if (ret)
 246                        goto end;
 247        } else /* CMD_WRITE */
 248                pcc_ss_data->pending_pcc_write_cmd = FALSE;
 249
 250        /*
 251         * Handle the Minimum Request Turnaround Time(MRTT)
 252         * "The minimum amount of time that OSPM must wait after the completion
 253         * of a command before issuing the next command, in microseconds"
 254         */
 255        if (pcc_ss_data->pcc_mrtt) {
 256                time_delta = ktime_us_delta(ktime_get(),
 257                                            pcc_ss_data->last_cmd_cmpl_time);
 258                if (pcc_ss_data->pcc_mrtt > time_delta)
 259                        udelay(pcc_ss_data->pcc_mrtt - time_delta);
 260        }
 261
 262        /*
 263         * Handle the non-zero Maximum Periodic Access Rate(MPAR)
 264         * "The maximum number of periodic requests that the subspace channel can
 265         * support, reported in commands per minute. 0 indicates no limitation."
 266         *
 267         * This parameter should be ideally zero or large enough so that it can
 268         * handle maximum number of requests that all the cores in the system can
 269         * collectively generate. If it is not, we will follow the spec and just
 270         * not send the request to the platform after hitting the MPAR limit in
 271         * any 60s window
 272         */
 273        if (pcc_ss_data->pcc_mpar) {
 274                if (pcc_ss_data->mpar_count == 0) {
 275                        time_delta = ktime_ms_delta(ktime_get(),
 276                                                    pcc_ss_data->last_mpar_reset);
 277                        if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
 278                                pr_debug("PCC cmd for subspace %d not sent due to MPAR limit",
 279                                         pcc_ss_id);
 280                                ret = -EIO;
 281                                goto end;
 282                        }
 283                        pcc_ss_data->last_mpar_reset = ktime_get();
 284                        pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
 285                }
 286                pcc_ss_data->mpar_count--;
 287        }
 288
 289        /* Write to the shared comm region. */
 290        writew_relaxed(cmd, &generic_comm_base->command);
 291
 292        /* Flip CMD COMPLETE bit */
 293        writew_relaxed(0, &generic_comm_base->status);
 294
 295        pcc_ss_data->platform_owns_pcc = true;
 296
 297        /* Ring doorbell */
 298        ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd);
 299        if (ret < 0) {
 300                pr_err("Err sending PCC mbox message. ss: %d cmd:%d, ret:%d\n",
 301                       pcc_ss_id, cmd, ret);
 302                goto end;
 303        }
 304
 305        /* wait for completion and check for PCC errro bit */
 306        ret = check_pcc_chan(pcc_ss_id, true);
 307
 308        if (pcc_ss_data->pcc_mrtt)
 309                pcc_ss_data->last_cmd_cmpl_time = ktime_get();
 310
 311        if (pcc_ss_data->pcc_channel->mbox->txdone_irq)
 312                mbox_chan_txdone(pcc_ss_data->pcc_channel, ret);
 313        else
 314                mbox_client_txdone(pcc_ss_data->pcc_channel, ret);
 315
 316end:
 317        if (cmd == CMD_WRITE) {
 318                if (unlikely(ret)) {
 319                        for_each_possible_cpu(i) {
 320                                struct cpc_desc *desc = per_cpu(cpc_desc_ptr, i);
 321
 322                                if (!desc)
 323                                        continue;
 324
 325                                if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
 326                                        desc->write_cmd_status = ret;
 327                        }
 328                }
 329                pcc_ss_data->pcc_write_cnt++;
 330                wake_up_all(&pcc_ss_data->pcc_write_wait_q);
 331        }
 332
 333        return ret;
 334}
 335
 336static void cppc_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
 337{
 338        if (ret < 0)
 339                pr_debug("TX did not complete: CMD sent:%x, ret:%d\n",
 340                                *(u16 *)msg, ret);
 341        else
 342                pr_debug("TX completed. CMD sent:%x, ret:%d\n",
 343                                *(u16 *)msg, ret);
 344}
 345
 346static struct mbox_client cppc_mbox_cl = {
 347        .tx_done = cppc_chan_tx_done,
 348        .knows_txdone = true,
 349};
 350
 351static int acpi_get_psd(struct cpc_desc *cpc_ptr, acpi_handle handle)
 352{
 353        int result = -EFAULT;
 354        acpi_status status = AE_OK;
 355        struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 356        struct acpi_buffer format = {sizeof("NNNNN"), "NNNNN"};
 357        struct acpi_buffer state = {0, NULL};
 358        union acpi_object  *psd = NULL;
 359        struct acpi_psd_package *pdomain;
 360
 361        status = acpi_evaluate_object_typed(handle, "_PSD", NULL,
 362                                            &buffer, ACPI_TYPE_PACKAGE);
 363        if (status == AE_NOT_FOUND)     /* _PSD is optional */
 364                return 0;
 365        if (ACPI_FAILURE(status))
 366                return -ENODEV;
 367
 368        psd = buffer.pointer;
 369        if (!psd || psd->package.count != 1) {
 370                pr_debug("Invalid _PSD data\n");
 371                goto end;
 372        }
 373
 374        pdomain = &(cpc_ptr->domain_info);
 375
 376        state.length = sizeof(struct acpi_psd_package);
 377        state.pointer = pdomain;
 378
 379        status = acpi_extract_package(&(psd->package.elements[0]),
 380                &format, &state);
 381        if (ACPI_FAILURE(status)) {
 382                pr_debug("Invalid _PSD data for CPU:%d\n", cpc_ptr->cpu_id);
 383                goto end;
 384        }
 385
 386        if (pdomain->num_entries != ACPI_PSD_REV0_ENTRIES) {
 387                pr_debug("Unknown _PSD:num_entries for CPU:%d\n", cpc_ptr->cpu_id);
 388                goto end;
 389        }
 390
 391        if (pdomain->revision != ACPI_PSD_REV0_REVISION) {
 392                pr_debug("Unknown _PSD:revision for CPU: %d\n", cpc_ptr->cpu_id);
 393                goto end;
 394        }
 395
 396        if (pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ALL &&
 397            pdomain->coord_type != DOMAIN_COORD_TYPE_SW_ANY &&
 398            pdomain->coord_type != DOMAIN_COORD_TYPE_HW_ALL) {
 399                pr_debug("Invalid _PSD:coord_type for CPU:%d\n", cpc_ptr->cpu_id);
 400                goto end;
 401        }
 402
 403        result = 0;
 404end:
 405        kfree(buffer.pointer);
 406        return result;
 407}
 408
 409bool acpi_cpc_valid(void)
 410{
 411        struct cpc_desc *cpc_ptr;
 412        int cpu;
 413
 414        for_each_possible_cpu(cpu) {
 415                cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 416                if (!cpc_ptr)
 417                        return false;
 418        }
 419
 420        return true;
 421}
 422EXPORT_SYMBOL_GPL(acpi_cpc_valid);
 423
 424/**
 425 * acpi_get_psd_map - Map the CPUs in the freq domain of a given cpu
 426 * @cpu: Find all CPUs that share a domain with cpu.
 427 * @cpu_data: Pointer to CPU specific CPPC data including PSD info.
 428 *
 429 *      Return: 0 for success or negative value for err.
 430 */
 431int acpi_get_psd_map(unsigned int cpu, struct cppc_cpudata *cpu_data)
 432{
 433        struct cpc_desc *cpc_ptr, *match_cpc_ptr;
 434        struct acpi_psd_package *match_pdomain;
 435        struct acpi_psd_package *pdomain;
 436        int count_target, i;
 437
 438        /*
 439         * Now that we have _PSD data from all CPUs, let's setup P-state
 440         * domain info.
 441         */
 442        cpc_ptr = per_cpu(cpc_desc_ptr, cpu);
 443        if (!cpc_ptr)
 444                return -EFAULT;
 445
 446        pdomain = &(cpc_ptr->domain_info);
 447        cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 448        if (pdomain->num_processors <= 1)
 449                return 0;
 450
 451        /* Validate the Domain info */
 452        count_target = pdomain->num_processors;
 453        if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ALL)
 454                cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ALL;
 455        else if (pdomain->coord_type == DOMAIN_COORD_TYPE_HW_ALL)
 456                cpu_data->shared_type = CPUFREQ_SHARED_TYPE_HW;
 457        else if (pdomain->coord_type == DOMAIN_COORD_TYPE_SW_ANY)
 458                cpu_data->shared_type = CPUFREQ_SHARED_TYPE_ANY;
 459
 460        for_each_possible_cpu(i) {
 461                if (i == cpu)
 462                        continue;
 463
 464                match_cpc_ptr = per_cpu(cpc_desc_ptr, i);
 465                if (!match_cpc_ptr)
 466                        goto err_fault;
 467
 468                match_pdomain = &(match_cpc_ptr->domain_info);
 469                if (match_pdomain->domain != pdomain->domain)
 470                        continue;
 471
 472                /* Here i and cpu are in the same domain */
 473                if (match_pdomain->num_processors != count_target)
 474                        goto err_fault;
 475
 476                if (pdomain->coord_type != match_pdomain->coord_type)
 477                        goto err_fault;
 478
 479                cpumask_set_cpu(i, cpu_data->shared_cpu_map);
 480        }
 481
 482        return 0;
 483
 484err_fault:
 485        /* Assume no coordination on any error parsing domain info */
 486        cpumask_clear(cpu_data->shared_cpu_map);
 487        cpumask_set_cpu(cpu, cpu_data->shared_cpu_map);
 488        cpu_data->shared_type = CPUFREQ_SHARED_TYPE_NONE;
 489
 490        return -EFAULT;
 491}
 492EXPORT_SYMBOL_GPL(acpi_get_psd_map);
 493
 494static int register_pcc_channel(int pcc_ss_idx)
 495{
 496        struct acpi_pcct_hw_reduced *cppc_ss;
 497        u64 usecs_lat;
 498
 499        if (pcc_ss_idx >= 0) {
 500                pcc_data[pcc_ss_idx]->pcc_channel =
 501                        pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
 502
 503                if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) {
 504                        pr_err("Failed to find PCC channel for subspace %d\n",
 505                               pcc_ss_idx);
 506                        return -ENODEV;
 507                }
 508
 509                /*
 510                 * The PCC mailbox controller driver should
 511                 * have parsed the PCCT (global table of all
 512                 * PCC channels) and stored pointers to the
 513                 * subspace communication region in con_priv.
 514                 */
 515                cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv;
 516
 517                if (!cppc_ss) {
 518                        pr_err("No PCC subspace found for %d CPPC\n",
 519                               pcc_ss_idx);
 520                        return -ENODEV;
 521                }
 522
 523                /*
 524                 * cppc_ss->latency is just a Nominal value. In reality
 525                 * the remote processor could be much slower to reply.
 526                 * So add an arbitrary amount of wait on top of Nominal.
 527                 */
 528                usecs_lat = NUM_RETRIES * cppc_ss->latency;
 529                pcc_data[pcc_ss_idx]->deadline_us = usecs_lat;
 530                pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time;
 531                pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate;
 532                pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency;
 533
 534                pcc_data[pcc_ss_idx]->pcc_comm_addr =
 535                        acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
 536                if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
 537                        pr_err("Failed to ioremap PCC comm region mem for %d\n",
 538                               pcc_ss_idx);
 539                        return -ENOMEM;
 540                }
 541
 542                /* Set flag so that we don't come here for each CPU. */
 543                pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
 544        }
 545
 546        return 0;
 547}
 548
 549/**
 550 * cpc_ffh_supported() - check if FFH reading supported
 551 *
 552 * Check if the architecture has support for functional fixed hardware
 553 * read/write capability.
 554 *
 555 * Return: true for supported, false for not supported
 556 */
 557bool __weak cpc_ffh_supported(void)
 558{
 559        return false;
 560}
 561
 562/**
 563 * pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
 564 *
 565 * Check and allocate the cppc_pcc_data memory.
 566 * In some processor configurations it is possible that same subspace
 567 * is shared between multiple CPUs. This is seen especially in CPUs
 568 * with hardware multi-threading support.
 569 *
 570 * Return: 0 for success, errno for failure
 571 */
 572static int pcc_data_alloc(int pcc_ss_id)
 573{
 574        if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
 575                return -EINVAL;
 576
 577        if (pcc_data[pcc_ss_id]) {
 578                pcc_data[pcc_ss_id]->refcount++;
 579        } else {
 580                pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
 581                                              GFP_KERNEL);
 582                if (!pcc_data[pcc_ss_id])
 583                        return -ENOMEM;
 584                pcc_data[pcc_ss_id]->refcount++;
 585        }
 586
 587        return 0;
 588}
 589
 590/* Check if CPPC revision + num_ent combination is supported */
 591static bool is_cppc_supported(int revision, int num_ent)
 592{
 593        int expected_num_ent;
 594
 595        switch (revision) {
 596        case CPPC_V2_REV:
 597                expected_num_ent = CPPC_V2_NUM_ENT;
 598                break;
 599        case CPPC_V3_REV:
 600                expected_num_ent = CPPC_V3_NUM_ENT;
 601                break;
 602        default:
 603                pr_debug("Firmware exports unsupported CPPC revision: %d\n",
 604                        revision);
 605                return false;
 606        }
 607
 608        if (expected_num_ent != num_ent) {
 609                pr_debug("Firmware exports %d entries. Expected: %d for CPPC rev:%d\n",
 610                        num_ent, expected_num_ent, revision);
 611                return false;
 612        }
 613
 614        return true;
 615}
 616
 617/*
 618 * An example CPC table looks like the following.
 619 *
 620 *      Name(_CPC, Package()
 621 *                      {
 622 *                      17,
 623 *                      NumEntries
 624 *                      1,
 625 *                      // Revision
 626 *                      ResourceTemplate(){Register(PCC, 32, 0, 0x120, 2)},
 627 *                      // Highest Performance
 628 *                      ResourceTemplate(){Register(PCC, 32, 0, 0x124, 2)},
 629 *                      // Nominal Performance
 630 *                      ResourceTemplate(){Register(PCC, 32, 0, 0x128, 2)},
 631 *                      // Lowest Nonlinear Performance
 632 *                      ResourceTemplate(){Register(PCC, 32, 0, 0x12C, 2)},
 633 *                      // Lowest Performance
 634 *                      ResourceTemplate(){Register(PCC, 32, 0, 0x130, 2)},
 635 *                      // Guaranteed Performance Register
 636 *                      ResourceTemplate(){Register(PCC, 32, 0, 0x110, 2)},
 637 *                      // Desired Performance Register
 638 *                      ResourceTemplate(){Register(SystemMemory, 0, 0, 0, 0)},
 639 *                      ..
 640 *                      ..
 641 *                      ..
 642 *
 643 *              }
 644 * Each Register() encodes how to access that specific register.
 645 * e.g. a sample PCC entry has the following encoding:
 646 *
 647 *      Register (
 648 *              PCC,
 649 *              AddressSpaceKeyword
 650 *              8,
 651 *              //RegisterBitWidth
 652 *              8,
 653 *              //RegisterBitOffset
 654 *              0x30,
 655 *              //RegisterAddress
 656 *              9
 657 *              //AccessSize (subspace ID)
 658 *              0
 659 *              )
 660 *      }
 661 */
 662
 663#ifndef init_freq_invariance_cppc
 664static inline void init_freq_invariance_cppc(void) { }
 665#endif
 666
 667/**
 668 * acpi_cppc_processor_probe - Search for per CPU _CPC objects.
 669 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 670 *
 671 *      Return: 0 for success or negative value for err.
 672 */
 673int acpi_cppc_processor_probe(struct acpi_processor *pr)
 674{
 675        struct acpi_buffer output = {ACPI_ALLOCATE_BUFFER, NULL};
 676        union acpi_object *out_obj, *cpc_obj;
 677        struct cpc_desc *cpc_ptr;
 678        struct cpc_reg *gas_t;
 679        struct device *cpu_dev;
 680        acpi_handle handle = pr->handle;
 681        unsigned int num_ent, i, cpc_rev;
 682        int pcc_subspace_id = -1;
 683        acpi_status status;
 684        int ret = -EFAULT;
 685
 686        /* Parse the ACPI _CPC table for this CPU. */
 687        status = acpi_evaluate_object_typed(handle, "_CPC", NULL, &output,
 688                        ACPI_TYPE_PACKAGE);
 689        if (ACPI_FAILURE(status)) {
 690                ret = -ENODEV;
 691                goto out_buf_free;
 692        }
 693
 694        out_obj = (union acpi_object *) output.pointer;
 695
 696        cpc_ptr = kzalloc(sizeof(struct cpc_desc), GFP_KERNEL);
 697        if (!cpc_ptr) {
 698                ret = -ENOMEM;
 699                goto out_buf_free;
 700        }
 701
 702        /* First entry is NumEntries. */
 703        cpc_obj = &out_obj->package.elements[0];
 704        if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 705                num_ent = cpc_obj->integer.value;
 706        } else {
 707                pr_debug("Unexpected entry type(%d) for NumEntries\n",
 708                                cpc_obj->type);
 709                goto out_free;
 710        }
 711        cpc_ptr->num_entries = num_ent;
 712
 713        /* Second entry should be revision. */
 714        cpc_obj = &out_obj->package.elements[1];
 715        if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 716                cpc_rev = cpc_obj->integer.value;
 717        } else {
 718                pr_debug("Unexpected entry type(%d) for Revision\n",
 719                                cpc_obj->type);
 720                goto out_free;
 721        }
 722        cpc_ptr->version = cpc_rev;
 723
 724        if (!is_cppc_supported(cpc_rev, num_ent))
 725                goto out_free;
 726
 727        /* Iterate through remaining entries in _CPC */
 728        for (i = 2; i < num_ent; i++) {
 729                cpc_obj = &out_obj->package.elements[i];
 730
 731                if (cpc_obj->type == ACPI_TYPE_INTEGER) {
 732                        cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_INTEGER;
 733                        cpc_ptr->cpc_regs[i-2].cpc_entry.int_value = cpc_obj->integer.value;
 734                } else if (cpc_obj->type == ACPI_TYPE_BUFFER) {
 735                        gas_t = (struct cpc_reg *)
 736                                cpc_obj->buffer.pointer;
 737
 738                        /*
 739                         * The PCC Subspace index is encoded inside
 740                         * the CPC table entries. The same PCC index
 741                         * will be used for all the PCC entries,
 742                         * so extract it only once.
 743                         */
 744                        if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
 745                                if (pcc_subspace_id < 0) {
 746                                        pcc_subspace_id = gas_t->access_width;
 747                                        if (pcc_data_alloc(pcc_subspace_id))
 748                                                goto out_free;
 749                                } else if (pcc_subspace_id != gas_t->access_width) {
 750                                        pr_debug("Mismatched PCC ids.\n");
 751                                        goto out_free;
 752                                }
 753                        } else if (gas_t->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY) {
 754                                if (gas_t->address) {
 755                                        void __iomem *addr;
 756
 757                                        addr = ioremap(gas_t->address, gas_t->bit_width/8);
 758                                        if (!addr)
 759                                                goto out_free;
 760                                        cpc_ptr->cpc_regs[i-2].sys_mem_vaddr = addr;
 761                                }
 762                        } else {
 763                                if (gas_t->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE || !cpc_ffh_supported()) {
 764                                        /* Support only PCC ,SYS MEM and FFH type regs */
 765                                        pr_debug("Unsupported register type: %d\n", gas_t->space_id);
 766                                        goto out_free;
 767                                }
 768                        }
 769
 770                        cpc_ptr->cpc_regs[i-2].type = ACPI_TYPE_BUFFER;
 771                        memcpy(&cpc_ptr->cpc_regs[i-2].cpc_entry.reg, gas_t, sizeof(*gas_t));
 772                } else {
 773                        pr_debug("Err in entry:%d in CPC table of CPU:%d\n", i, pr->id);
 774                        goto out_free;
 775                }
 776        }
 777        per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
 778
 779        /*
 780         * Initialize the remaining cpc_regs as unsupported.
 781         * Example: In case FW exposes CPPC v2, the below loop will initialize
 782         * LOWEST_FREQ and NOMINAL_FREQ regs as unsupported
 783         */
 784        for (i = num_ent - 2; i < MAX_CPC_REG_ENT; i++) {
 785                cpc_ptr->cpc_regs[i].type = ACPI_TYPE_INTEGER;
 786                cpc_ptr->cpc_regs[i].cpc_entry.int_value = 0;
 787        }
 788
 789
 790        /* Store CPU Logical ID */
 791        cpc_ptr->cpu_id = pr->id;
 792
 793        /* Parse PSD data for this CPU */
 794        ret = acpi_get_psd(cpc_ptr, handle);
 795        if (ret)
 796                goto out_free;
 797
 798        /* Register PCC channel once for all PCC subspace ID. */
 799        if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
 800                ret = register_pcc_channel(pcc_subspace_id);
 801                if (ret)
 802                        goto out_free;
 803
 804                init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
 805                init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
 806        }
 807
 808        /* Everything looks okay */
 809        pr_debug("Parsed CPC struct for CPU: %d\n", pr->id);
 810
 811        /* Add per logical CPU nodes for reading its feedback counters. */
 812        cpu_dev = get_cpu_device(pr->id);
 813        if (!cpu_dev) {
 814                ret = -EINVAL;
 815                goto out_free;
 816        }
 817
 818        /* Plug PSD data into this CPU's CPC descriptor. */
 819        per_cpu(cpc_desc_ptr, pr->id) = cpc_ptr;
 820
 821        ret = kobject_init_and_add(&cpc_ptr->kobj, &cppc_ktype, &cpu_dev->kobj,
 822                        "acpi_cppc");
 823        if (ret) {
 824                per_cpu(cpc_desc_ptr, pr->id) = NULL;
 825                kobject_put(&cpc_ptr->kobj);
 826                goto out_free;
 827        }
 828
 829        init_freq_invariance_cppc();
 830
 831        kfree(output.pointer);
 832        return 0;
 833
 834out_free:
 835        /* Free all the mapped sys mem areas for this CPU */
 836        for (i = 2; i < cpc_ptr->num_entries; i++) {
 837                void __iomem *addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 838
 839                if (addr)
 840                        iounmap(addr);
 841        }
 842        kfree(cpc_ptr);
 843
 844out_buf_free:
 845        kfree(output.pointer);
 846        return ret;
 847}
 848EXPORT_SYMBOL_GPL(acpi_cppc_processor_probe);
 849
 850/**
 851 * acpi_cppc_processor_exit - Cleanup CPC structs.
 852 * @pr: Ptr to acpi_processor containing this CPU's logical ID.
 853 *
 854 * Return: Void
 855 */
 856void acpi_cppc_processor_exit(struct acpi_processor *pr)
 857{
 858        struct cpc_desc *cpc_ptr;
 859        unsigned int i;
 860        void __iomem *addr;
 861        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
 862
 863        if (pcc_ss_id >= 0 && pcc_data[pcc_ss_id]) {
 864                if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
 865                        pcc_data[pcc_ss_id]->refcount--;
 866                        if (!pcc_data[pcc_ss_id]->refcount) {
 867                                pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
 868                                kfree(pcc_data[pcc_ss_id]);
 869                                pcc_data[pcc_ss_id] = NULL;
 870                        }
 871                }
 872        }
 873
 874        cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
 875        if (!cpc_ptr)
 876                return;
 877
 878        /* Free all the mapped sys mem areas for this CPU */
 879        for (i = 2; i < cpc_ptr->num_entries; i++) {
 880                addr = cpc_ptr->cpc_regs[i-2].sys_mem_vaddr;
 881                if (addr)
 882                        iounmap(addr);
 883        }
 884
 885        kobject_put(&cpc_ptr->kobj);
 886        kfree(cpc_ptr);
 887}
 888EXPORT_SYMBOL_GPL(acpi_cppc_processor_exit);
 889
 890/**
 891 * cpc_read_ffh() - Read FFH register
 892 * @cpunum:     CPU number to read
 893 * @reg:        cppc register information
 894 * @val:        place holder for return value
 895 *
 896 * Read bit_width bits from a specified address and bit_offset
 897 *
 898 * Return: 0 for success and error code
 899 */
 900int __weak cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val)
 901{
 902        return -ENOTSUPP;
 903}
 904
 905/**
 906 * cpc_write_ffh() - Write FFH register
 907 * @cpunum:     CPU number to write
 908 * @reg:        cppc register information
 909 * @val:        value to write
 910 *
 911 * Write value of bit_width bits to a specified address and bit_offset
 912 *
 913 * Return: 0 for success and error code
 914 */
 915int __weak cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
 916{
 917        return -ENOTSUPP;
 918}
 919
 920/*
 921 * Since cpc_read and cpc_write are called while holding pcc_lock, it should be
 922 * as fast as possible. We have already mapped the PCC subspace during init, so
 923 * we can directly write to it.
 924 */
 925
 926static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
 927{
 928        int ret_val = 0;
 929        void __iomem *vaddr = NULL;
 930        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 931        struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 932
 933        if (reg_res->type == ACPI_TYPE_INTEGER) {
 934                *val = reg_res->cpc_entry.int_value;
 935                return ret_val;
 936        }
 937
 938        *val = 0;
 939        if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 940                vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 941        else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 942                vaddr = reg_res->sys_mem_vaddr;
 943        else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 944                return cpc_read_ffh(cpu, reg, val);
 945        else
 946                return acpi_os_read_memory((acpi_physical_address)reg->address,
 947                                val, reg->bit_width);
 948
 949        switch (reg->bit_width) {
 950        case 8:
 951                *val = readb_relaxed(vaddr);
 952                break;
 953        case 16:
 954                *val = readw_relaxed(vaddr);
 955                break;
 956        case 32:
 957                *val = readl_relaxed(vaddr);
 958                break;
 959        case 64:
 960                *val = readq_relaxed(vaddr);
 961                break;
 962        default:
 963                pr_debug("Error: Cannot read %u bit width from PCC for ss: %d\n",
 964                         reg->bit_width, pcc_ss_id);
 965                ret_val = -EFAULT;
 966        }
 967
 968        return ret_val;
 969}
 970
 971static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
 972{
 973        int ret_val = 0;
 974        void __iomem *vaddr = NULL;
 975        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
 976        struct cpc_reg *reg = &reg_res->cpc_entry.reg;
 977
 978        if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM && pcc_ss_id >= 0)
 979                vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
 980        else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
 981                vaddr = reg_res->sys_mem_vaddr;
 982        else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
 983                return cpc_write_ffh(cpu, reg, val);
 984        else
 985                return acpi_os_write_memory((acpi_physical_address)reg->address,
 986                                val, reg->bit_width);
 987
 988        switch (reg->bit_width) {
 989        case 8:
 990                writeb_relaxed(val, vaddr);
 991                break;
 992        case 16:
 993                writew_relaxed(val, vaddr);
 994                break;
 995        case 32:
 996                writel_relaxed(val, vaddr);
 997                break;
 998        case 64:
 999                writeq_relaxed(val, vaddr);
1000                break;
1001        default:
1002                pr_debug("Error: Cannot write %u bit width to PCC for ss: %d\n",
1003                         reg->bit_width, pcc_ss_id);
1004                ret_val = -EFAULT;
1005                break;
1006        }
1007
1008        return ret_val;
1009}
1010
1011/**
1012 * cppc_get_desired_perf - Get the value of desired performance register.
1013 * @cpunum: CPU from which to get desired performance.
1014 * @desired_perf: address of a variable to store the returned desired performance
1015 *
1016 * Return: 0 for success, -EIO otherwise.
1017 */
1018int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
1019{
1020        struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1021        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1022        struct cpc_register_resource *desired_reg;
1023        struct cppc_pcc_data *pcc_ss_data = NULL;
1024
1025        desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1026
1027        if (CPC_IN_PCC(desired_reg)) {
1028                int ret = 0;
1029
1030                if (pcc_ss_id < 0)
1031                        return -EIO;
1032
1033                pcc_ss_data = pcc_data[pcc_ss_id];
1034
1035                down_write(&pcc_ss_data->pcc_lock);
1036
1037                if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0)
1038                        cpc_read(cpunum, desired_reg, desired_perf);
1039                else
1040                        ret = -EIO;
1041
1042                up_write(&pcc_ss_data->pcc_lock);
1043
1044                return ret;
1045        }
1046
1047        cpc_read(cpunum, desired_reg, desired_perf);
1048
1049        return 0;
1050}
1051EXPORT_SYMBOL_GPL(cppc_get_desired_perf);
1052
1053/**
1054 * cppc_get_perf_caps - Get a CPU's performance capabilities.
1055 * @cpunum: CPU from which to get capabilities info.
1056 * @perf_caps: ptr to cppc_perf_caps. See cppc_acpi.h
1057 *
1058 * Return: 0 for success with perf_caps populated else -ERRNO.
1059 */
1060int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
1061{
1062        struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1063        struct cpc_register_resource *highest_reg, *lowest_reg,
1064                *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg,
1065                *low_freq_reg = NULL, *nom_freq_reg = NULL;
1066        u64 high, low, guaranteed, nom, min_nonlinear, low_f = 0, nom_f = 0;
1067        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1068        struct cppc_pcc_data *pcc_ss_data = NULL;
1069        int ret = 0, regs_in_pcc = 0;
1070
1071        if (!cpc_desc) {
1072                pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1073                return -ENODEV;
1074        }
1075
1076        highest_reg = &cpc_desc->cpc_regs[HIGHEST_PERF];
1077        lowest_reg = &cpc_desc->cpc_regs[LOWEST_PERF];
1078        lowest_non_linear_reg = &cpc_desc->cpc_regs[LOW_NON_LINEAR_PERF];
1079        nominal_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1080        low_freq_reg = &cpc_desc->cpc_regs[LOWEST_FREQ];
1081        nom_freq_reg = &cpc_desc->cpc_regs[NOMINAL_FREQ];
1082        guaranteed_reg = &cpc_desc->cpc_regs[GUARANTEED_PERF];
1083
1084        /* Are any of the regs PCC ?*/
1085        if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
1086                CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) ||
1087                CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) {
1088                if (pcc_ss_id < 0) {
1089                        pr_debug("Invalid pcc_ss_id\n");
1090                        return -ENODEV;
1091                }
1092                pcc_ss_data = pcc_data[pcc_ss_id];
1093                regs_in_pcc = 1;
1094                down_write(&pcc_ss_data->pcc_lock);
1095                /* Ring doorbell once to update PCC subspace */
1096                if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1097                        ret = -EIO;
1098                        goto out_err;
1099                }
1100        }
1101
1102        cpc_read(cpunum, highest_reg, &high);
1103        perf_caps->highest_perf = high;
1104
1105        cpc_read(cpunum, lowest_reg, &low);
1106        perf_caps->lowest_perf = low;
1107
1108        cpc_read(cpunum, nominal_reg, &nom);
1109        perf_caps->nominal_perf = nom;
1110
1111        if (guaranteed_reg->type != ACPI_TYPE_BUFFER  ||
1112            IS_NULL_REG(&guaranteed_reg->cpc_entry.reg)) {
1113                perf_caps->guaranteed_perf = 0;
1114        } else {
1115                cpc_read(cpunum, guaranteed_reg, &guaranteed);
1116                perf_caps->guaranteed_perf = guaranteed;
1117        }
1118
1119        cpc_read(cpunum, lowest_non_linear_reg, &min_nonlinear);
1120        perf_caps->lowest_nonlinear_perf = min_nonlinear;
1121
1122        if (!high || !low || !nom || !min_nonlinear)
1123                ret = -EFAULT;
1124
1125        /* Read optional lowest and nominal frequencies if present */
1126        if (CPC_SUPPORTED(low_freq_reg))
1127                cpc_read(cpunum, low_freq_reg, &low_f);
1128
1129        if (CPC_SUPPORTED(nom_freq_reg))
1130                cpc_read(cpunum, nom_freq_reg, &nom_f);
1131
1132        perf_caps->lowest_freq = low_f;
1133        perf_caps->nominal_freq = nom_f;
1134
1135
1136out_err:
1137        if (regs_in_pcc)
1138                up_write(&pcc_ss_data->pcc_lock);
1139        return ret;
1140}
1141EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
1142
1143/**
1144 * cppc_get_perf_ctrs - Read a CPU's performance feedback counters.
1145 * @cpunum: CPU from which to read counters.
1146 * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h
1147 *
1148 * Return: 0 for success with perf_fb_ctrs populated else -ERRNO.
1149 */
1150int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
1151{
1152        struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
1153        struct cpc_register_resource *delivered_reg, *reference_reg,
1154                *ref_perf_reg, *ctr_wrap_reg;
1155        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
1156        struct cppc_pcc_data *pcc_ss_data = NULL;
1157        u64 delivered, reference, ref_perf, ctr_wrap_time;
1158        int ret = 0, regs_in_pcc = 0;
1159
1160        if (!cpc_desc) {
1161                pr_debug("No CPC descriptor for CPU:%d\n", cpunum);
1162                return -ENODEV;
1163        }
1164
1165        delivered_reg = &cpc_desc->cpc_regs[DELIVERED_CTR];
1166        reference_reg = &cpc_desc->cpc_regs[REFERENCE_CTR];
1167        ref_perf_reg = &cpc_desc->cpc_regs[REFERENCE_PERF];
1168        ctr_wrap_reg = &cpc_desc->cpc_regs[CTR_WRAP_TIME];
1169
1170        /*
1171         * If reference perf register is not supported then we should
1172         * use the nominal perf value
1173         */
1174        if (!CPC_SUPPORTED(ref_perf_reg))
1175                ref_perf_reg = &cpc_desc->cpc_regs[NOMINAL_PERF];
1176
1177        /* Are any of the regs PCC ?*/
1178        if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
1179                CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
1180                if (pcc_ss_id < 0) {
1181                        pr_debug("Invalid pcc_ss_id\n");
1182                        return -ENODEV;
1183                }
1184                pcc_ss_data = pcc_data[pcc_ss_id];
1185                down_write(&pcc_ss_data->pcc_lock);
1186                regs_in_pcc = 1;
1187                /* Ring doorbell once to update PCC subspace */
1188                if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
1189                        ret = -EIO;
1190                        goto out_err;
1191                }
1192        }
1193
1194        cpc_read(cpunum, delivered_reg, &delivered);
1195        cpc_read(cpunum, reference_reg, &reference);
1196        cpc_read(cpunum, ref_perf_reg, &ref_perf);
1197
1198        /*
1199         * Per spec, if ctr_wrap_time optional register is unsupported, then the
1200         * performance counters are assumed to never wrap during the lifetime of
1201         * platform
1202         */
1203        ctr_wrap_time = (u64)(~((u64)0));
1204        if (CPC_SUPPORTED(ctr_wrap_reg))
1205                cpc_read(cpunum, ctr_wrap_reg, &ctr_wrap_time);
1206
1207        if (!delivered || !reference || !ref_perf) {
1208                ret = -EFAULT;
1209                goto out_err;
1210        }
1211
1212        perf_fb_ctrs->delivered = delivered;
1213        perf_fb_ctrs->reference = reference;
1214        perf_fb_ctrs->reference_perf = ref_perf;
1215        perf_fb_ctrs->wraparound_time = ctr_wrap_time;
1216out_err:
1217        if (regs_in_pcc)
1218                up_write(&pcc_ss_data->pcc_lock);
1219        return ret;
1220}
1221EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
1222
1223/**
1224 * cppc_set_perf - Set a CPU's performance controls.
1225 * @cpu: CPU for which to set performance controls.
1226 * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h
1227 *
1228 * Return: 0 for success, -ERRNO otherwise.
1229 */
1230int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
1231{
1232        struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
1233        struct cpc_register_resource *desired_reg;
1234        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
1235        struct cppc_pcc_data *pcc_ss_data = NULL;
1236        int ret = 0;
1237
1238        if (!cpc_desc) {
1239                pr_debug("No CPC descriptor for CPU:%d\n", cpu);
1240                return -ENODEV;
1241        }
1242
1243        desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1244
1245        /*
1246         * This is Phase-I where we want to write to CPC registers
1247         * -> We want all CPUs to be able to execute this phase in parallel
1248         *
1249         * Since read_lock can be acquired by multiple CPUs simultaneously we
1250         * achieve that goal here
1251         */
1252        if (CPC_IN_PCC(desired_reg)) {
1253                if (pcc_ss_id < 0) {
1254                        pr_debug("Invalid pcc_ss_id\n");
1255                        return -ENODEV;
1256                }
1257                pcc_ss_data = pcc_data[pcc_ss_id];
1258                down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
1259                if (pcc_ss_data->platform_owns_pcc) {
1260                        ret = check_pcc_chan(pcc_ss_id, false);
1261                        if (ret) {
1262                                up_read(&pcc_ss_data->pcc_lock);
1263                                return ret;
1264                        }
1265                }
1266                /*
1267                 * Update the pending_write to make sure a PCC CMD_READ will not
1268                 * arrive and steal the channel during the switch to write lock
1269                 */
1270                pcc_ss_data->pending_pcc_write_cmd = true;
1271                cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
1272                cpc_desc->write_cmd_status = 0;
1273        }
1274
1275        /*
1276         * Skip writing MIN/MAX until Linux knows how to come up with
1277         * useful values.
1278         */
1279        cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
1280
1281        if (CPC_IN_PCC(desired_reg))
1282                up_read(&pcc_ss_data->pcc_lock);        /* END Phase-I */
1283        /*
1284         * This is Phase-II where we transfer the ownership of PCC to Platform
1285         *
1286         * Short Summary: Basically if we think of a group of cppc_set_perf
1287         * requests that happened in short overlapping interval. The last CPU to
1288         * come out of Phase-I will enter Phase-II and ring the doorbell.
1289         *
1290         * We have the following requirements for Phase-II:
1291         *     1. We want to execute Phase-II only when there are no CPUs
1292         * currently executing in Phase-I
1293         *     2. Once we start Phase-II we want to avoid all other CPUs from
1294         * entering Phase-I.
1295         *     3. We want only one CPU among all those who went through Phase-I
1296         * to run phase-II
1297         *
1298         * If write_trylock fails to get the lock and doesn't transfer the
1299         * PCC ownership to the platform, then one of the following will be TRUE
1300         *     1. There is at-least one CPU in Phase-I which will later execute
1301         * write_trylock, so the CPUs in Phase-I will be responsible for
1302         * executing the Phase-II.
1303         *     2. Some other CPU has beaten this CPU to successfully execute the
1304         * write_trylock and has already acquired the write_lock. We know for a
1305         * fact it (other CPU acquiring the write_lock) couldn't have happened
1306         * before this CPU's Phase-I as we held the read_lock.
1307         *     3. Some other CPU executing pcc CMD_READ has stolen the
1308         * down_write, in which case, send_pcc_cmd will check for pending
1309         * CMD_WRITE commands by checking the pending_pcc_write_cmd.
1310         * So this CPU can be certain that its request will be delivered
1311         *    So in all cases, this CPU knows that its request will be delivered
1312         * by another CPU and can return
1313         *
1314         * After getting the down_write we still need to check for
1315         * pending_pcc_write_cmd to take care of the following scenario
1316         *    The thread running this code could be scheduled out between
1317         * Phase-I and Phase-II. Before it is scheduled back on, another CPU
1318         * could have delivered the request to Platform by triggering the
1319         * doorbell and transferred the ownership of PCC to platform. So this
1320         * avoids triggering an unnecessary doorbell and more importantly before
1321         * triggering the doorbell it makes sure that the PCC channel ownership
1322         * is still with OSPM.
1323         *   pending_pcc_write_cmd can also be cleared by a different CPU, if
1324         * there was a pcc CMD_READ waiting on down_write and it steals the lock
1325         * before the pcc CMD_WRITE is completed. send_pcc_cmd checks for this
1326         * case during a CMD_READ and if there are pending writes it delivers
1327         * the write command before servicing the read command
1328         */
1329        if (CPC_IN_PCC(desired_reg)) {
1330                if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
1331                        /* Update only if there are pending write commands */
1332                        if (pcc_ss_data->pending_pcc_write_cmd)
1333                                send_pcc_cmd(pcc_ss_id, CMD_WRITE);
1334                        up_write(&pcc_ss_data->pcc_lock);       /* END Phase-II */
1335                } else
1336                        /* Wait until pcc_write_cnt is updated by send_pcc_cmd */
1337                        wait_event(pcc_ss_data->pcc_write_wait_q,
1338                                   cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
1339
1340                /* send_pcc_cmd updates the status in case of failure */
1341                ret = cpc_desc->write_cmd_status;
1342        }
1343        return ret;
1344}
1345EXPORT_SYMBOL_GPL(cppc_set_perf);
1346
1347/**
1348 * cppc_get_transition_latency - returns frequency transition latency in ns
1349 *
1350 * ACPI CPPC does not explicitly specify how a platform can specify the
1351 * transition latency for performance change requests. The closest we have
1352 * is the timing information from the PCCT tables which provides the info
1353 * on the number and frequency of PCC commands the platform can handle.
1354 */
1355unsigned int cppc_get_transition_latency(int cpu_num)
1356{
1357        /*
1358         * Expected transition latency is based on the PCCT timing values
1359         * Below are definition from ACPI spec:
1360         * pcc_nominal- Expected latency to process a command, in microseconds
1361         * pcc_mpar   - The maximum number of periodic requests that the subspace
1362         *              channel can support, reported in commands per minute. 0
1363         *              indicates no limitation.
1364         * pcc_mrtt   - The minimum amount of time that OSPM must wait after the
1365         *              completion of a command before issuing the next command,
1366         *              in microseconds.
1367         */
1368        unsigned int latency_ns = 0;
1369        struct cpc_desc *cpc_desc;
1370        struct cpc_register_resource *desired_reg;
1371        int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
1372        struct cppc_pcc_data *pcc_ss_data;
1373
1374        cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
1375        if (!cpc_desc)
1376                return CPUFREQ_ETERNAL;
1377
1378        desired_reg = &cpc_desc->cpc_regs[DESIRED_PERF];
1379        if (!CPC_IN_PCC(desired_reg))
1380                return CPUFREQ_ETERNAL;
1381
1382        if (pcc_ss_id < 0)
1383                return CPUFREQ_ETERNAL;
1384
1385        pcc_ss_data = pcc_data[pcc_ss_id];
1386        if (pcc_ss_data->pcc_mpar)
1387                latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
1388
1389        latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
1390        latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
1391
1392        return latency_ns;
1393}
1394EXPORT_SYMBOL_GPL(cppc_get_transition_latency);
1395