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15#include <linux/cpu.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/smp.h>
19#include <linux/preempt.h>
20#include <linux/hardirq.h>
21#include <linux/percpu.h>
22#include <linux/delay.h>
23#include <linux/start_kernel.h>
24#include <linux/sched.h>
25#include <linux/kprobes.h>
26#include <linux/memblock.h>
27#include <linux/export.h>
28#include <linux/mm.h>
29#include <linux/page-flags.h>
30#include <linux/highmem.h>
31#include <linux/console.h>
32#include <linux/pci.h>
33#include <linux/gfp.h>
34#include <linux/edd.h>
35#include <linux/objtool.h>
36
37#include <xen/xen.h>
38#include <xen/events.h>
39#include <xen/interface/xen.h>
40#include <xen/interface/version.h>
41#include <xen/interface/physdev.h>
42#include <xen/interface/vcpu.h>
43#include <xen/interface/memory.h>
44#include <xen/interface/nmi.h>
45#include <xen/interface/xen-mca.h>
46#include <xen/features.h>
47#include <xen/page.h>
48#include <xen/hvc-console.h>
49#include <xen/acpi.h>
50
51#include <asm/paravirt.h>
52#include <asm/apic.h>
53#include <asm/page.h>
54#include <asm/xen/pci.h>
55#include <asm/xen/hypercall.h>
56#include <asm/xen/hypervisor.h>
57#include <asm/xen/cpuid.h>
58#include <asm/fixmap.h>
59#include <asm/processor.h>
60#include <asm/proto.h>
61#include <asm/msr-index.h>
62#include <asm/traps.h>
63#include <asm/setup.h>
64#include <asm/desc.h>
65#include <asm/pgalloc.h>
66#include <asm/tlbflush.h>
67#include <asm/reboot.h>
68#include <asm/stackprotector.h>
69#include <asm/hypervisor.h>
70#include <asm/mach_traps.h>
71#include <asm/mwait.h>
72#include <asm/pci_x86.h>
73#include <asm/cpu.h>
74#ifdef CONFIG_X86_IOPL_IOPERM
75#include <asm/io_bitmap.h>
76#endif
77
78#ifdef CONFIG_ACPI
79#include <linux/acpi.h>
80#include <asm/acpi.h>
81#include <acpi/pdc_intel.h>
82#include <acpi/processor.h>
83#include <xen/interface/platform.h>
84#endif
85
86#include "xen-ops.h"
87#include "mmu.h"
88#include "smp.h"
89#include "multicalls.h"
90#include "pmu.h"
91
92#include "../kernel/cpu/cpu.h"
93
94void *xen_initial_gdt;
95
96static int xen_cpu_up_prepare_pv(unsigned int cpu);
97static int xen_cpu_dead_pv(unsigned int cpu);
98
99struct tls_descs {
100 struct desc_struct desc[3];
101};
102
103
104
105
106
107
108
109
110static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc);
111
112static void __init xen_banner(void)
113{
114 unsigned version = HYPERVISOR_xen_version(XENVER_version, NULL);
115 struct xen_extraversion extra;
116 HYPERVISOR_xen_version(XENVER_extraversion, &extra);
117
118 pr_info("Booting paravirtualized kernel on %s\n", pv_info.name);
119 printk(KERN_INFO "Xen version: %d.%d%s%s\n",
120 version >> 16, version & 0xffff, extra.extraversion,
121 xen_feature(XENFEAT_mmu_pt_update_preserve_ad) ? " (preserve-AD)" : "");
122}
123
124static void __init xen_pv_init_platform(void)
125{
126 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP));
127
128 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info);
129 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP);
130
131
132 xen_vcpu_info_reset(0);
133
134
135 xen_init_time_ops();
136}
137
138static void __init xen_pv_guest_late_init(void)
139{
140#ifndef CONFIG_SMP
141
142 xen_setup_vcpu_info_placement();
143#endif
144}
145
146
147bool
148xen_running_on_version_or_later(unsigned int major, unsigned int minor)
149{
150 unsigned int version;
151
152 if (!xen_domain())
153 return false;
154
155 version = HYPERVISOR_xen_version(XENVER_version, NULL);
156 if ((((version >> 16) == major) && ((version & 0xffff) >= minor)) ||
157 ((version >> 16) > major))
158 return true;
159 return false;
160}
161
162static __read_mostly unsigned int cpuid_leaf5_ecx_val;
163static __read_mostly unsigned int cpuid_leaf5_edx_val;
164
165static void xen_cpuid(unsigned int *ax, unsigned int *bx,
166 unsigned int *cx, unsigned int *dx)
167{
168 unsigned maskebx = ~0;
169
170
171
172
173
174 switch (*ax) {
175 case CPUID_MWAIT_LEAF:
176
177 *ax = 0;
178 *bx = 0;
179 *cx = cpuid_leaf5_ecx_val;
180 *dx = cpuid_leaf5_edx_val;
181 return;
182
183 case 0xb:
184
185 maskebx = 0;
186 break;
187 }
188
189 asm(XEN_EMULATE_PREFIX "cpuid"
190 : "=a" (*ax),
191 "=b" (*bx),
192 "=c" (*cx),
193 "=d" (*dx)
194 : "0" (*ax), "2" (*cx));
195
196 *bx &= maskebx;
197}
198STACK_FRAME_NON_STANDARD(xen_cpuid);
199
200static bool __init xen_check_mwait(void)
201{
202#ifdef CONFIG_ACPI
203 struct xen_platform_op op = {
204 .cmd = XENPF_set_processor_pminfo,
205 .u.set_pminfo.id = -1,
206 .u.set_pminfo.type = XEN_PM_PDC,
207 };
208 uint32_t buf[3];
209 unsigned int ax, bx, cx, dx;
210 unsigned int mwait_mask;
211
212
213
214
215
216
217
218
219
220 if (!xen_initial_domain())
221 return false;
222
223
224
225
226
227 if (!xen_running_on_version_or_later(4, 2))
228 return false;
229
230 ax = 1;
231 cx = 0;
232
233 native_cpuid(&ax, &bx, &cx, &dx);
234
235 mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
236 (1 << (X86_FEATURE_MWAIT % 32));
237
238 if ((cx & mwait_mask) != mwait_mask)
239 return false;
240
241
242
243
244
245 ax = CPUID_MWAIT_LEAF;
246 bx = 0;
247 cx = 0;
248 dx = 0;
249
250 native_cpuid(&ax, &bx, &cx, &dx);
251
252
253
254
255 buf[0] = ACPI_PDC_REVISION_ID;
256 buf[1] = 1;
257 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP);
258
259 set_xen_guest_handle(op.u.set_pminfo.pdc, buf);
260
261 if ((HYPERVISOR_platform_op(&op) == 0) &&
262 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) {
263 cpuid_leaf5_ecx_val = cx;
264 cpuid_leaf5_edx_val = dx;
265 }
266 return true;
267#else
268 return false;
269#endif
270}
271
272static bool __init xen_check_xsave(void)
273{
274 unsigned int cx, xsave_mask;
275
276 cx = cpuid_ecx(1);
277
278 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) |
279 (1 << (X86_FEATURE_OSXSAVE % 32));
280
281
282 return (cx & xsave_mask) == xsave_mask;
283}
284
285static void __init xen_init_capabilities(void)
286{
287 setup_force_cpu_cap(X86_FEATURE_XENPV);
288 setup_clear_cpu_cap(X86_FEATURE_DCA);
289 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF);
290 setup_clear_cpu_cap(X86_FEATURE_MTRR);
291 setup_clear_cpu_cap(X86_FEATURE_ACC);
292 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
293 setup_clear_cpu_cap(X86_FEATURE_SME);
294
295
296
297
298
299 setup_clear_cpu_cap(X86_FEATURE_PCID);
300
301 if (!xen_initial_domain())
302 setup_clear_cpu_cap(X86_FEATURE_ACPI);
303
304 if (xen_check_mwait())
305 setup_force_cpu_cap(X86_FEATURE_MWAIT);
306 else
307 setup_clear_cpu_cap(X86_FEATURE_MWAIT);
308
309 if (!xen_check_xsave()) {
310 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
311 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE);
312 }
313}
314
315static void xen_set_debugreg(int reg, unsigned long val)
316{
317 HYPERVISOR_set_debugreg(reg, val);
318}
319
320static unsigned long xen_get_debugreg(int reg)
321{
322 return HYPERVISOR_get_debugreg(reg);
323}
324
325static void xen_end_context_switch(struct task_struct *next)
326{
327 xen_mc_flush();
328 paravirt_end_context_switch(next);
329}
330
331static unsigned long xen_store_tr(void)
332{
333 return 0;
334}
335
336
337
338
339
340
341
342static void set_aliased_prot(void *v, pgprot_t prot)
343{
344 int level;
345 pte_t *ptep;
346 pte_t pte;
347 unsigned long pfn;
348 unsigned char dummy;
349 void *va;
350
351 ptep = lookup_address((unsigned long)v, &level);
352 BUG_ON(ptep == NULL);
353
354 pfn = pte_pfn(*ptep);
355 pte = pfn_pte(pfn, prot);
356
357
358
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361
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363
364
365
366
367
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369
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371
372
373
374
375
376
377 preempt_disable();
378
379 copy_from_kernel_nofault(&dummy, v, 1);
380
381 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0))
382 BUG();
383
384 va = __va(PFN_PHYS(pfn));
385
386 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
387 BUG();
388
389 preempt_enable();
390}
391
392static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries)
393{
394 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
395 int i;
396
397
398
399
400
401
402
403
404
405
406
407
408 for (i = 0; i < entries; i += entries_per_page)
409 set_aliased_prot(ldt + i, PAGE_KERNEL_RO);
410}
411
412static void xen_free_ldt(struct desc_struct *ldt, unsigned entries)
413{
414 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE;
415 int i;
416
417 for (i = 0; i < entries; i += entries_per_page)
418 set_aliased_prot(ldt + i, PAGE_KERNEL);
419}
420
421static void xen_set_ldt(const void *addr, unsigned entries)
422{
423 struct mmuext_op *op;
424 struct multicall_space mcs = xen_mc_entry(sizeof(*op));
425
426 trace_xen_cpu_set_ldt(addr, entries);
427
428 op = mcs.args;
429 op->cmd = MMUEXT_SET_LDT;
430 op->arg1.linear_addr = (unsigned long)addr;
431 op->arg2.nr_ents = entries;
432
433 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF);
434
435 xen_mc_issue(PARAVIRT_LAZY_CPU);
436}
437
438static void xen_load_gdt(const struct desc_ptr *dtr)
439{
440 unsigned long va = dtr->address;
441 unsigned int size = dtr->size + 1;
442 unsigned long pfn, mfn;
443 int level;
444 pte_t *ptep;
445 void *virt;
446
447
448 BUG_ON(size > PAGE_SIZE);
449 BUG_ON(va & ~PAGE_MASK);
450
451
452
453
454
455
456
457
458 ptep = lookup_address(va, &level);
459 BUG_ON(ptep == NULL);
460
461 pfn = pte_pfn(*ptep);
462 mfn = pfn_to_mfn(pfn);
463 virt = __va(PFN_PHYS(pfn));
464
465 make_lowmem_page_readonly((void *)va);
466 make_lowmem_page_readonly(virt);
467
468 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
469 BUG();
470}
471
472
473
474
475static void __init xen_load_gdt_boot(const struct desc_ptr *dtr)
476{
477 unsigned long va = dtr->address;
478 unsigned int size = dtr->size + 1;
479 unsigned long pfn, mfn;
480 pte_t pte;
481
482
483 BUG_ON(size > PAGE_SIZE);
484 BUG_ON(va & ~PAGE_MASK);
485
486 pfn = virt_to_pfn(va);
487 mfn = pfn_to_mfn(pfn);
488
489 pte = pfn_pte(pfn, PAGE_KERNEL_RO);
490
491 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
492 BUG();
493
494 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct)))
495 BUG();
496}
497
498static inline bool desc_equal(const struct desc_struct *d1,
499 const struct desc_struct *d2)
500{
501 return !memcmp(d1, d2, sizeof(*d1));
502}
503
504static void load_TLS_descriptor(struct thread_struct *t,
505 unsigned int cpu, unsigned int i)
506{
507 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i];
508 struct desc_struct *gdt;
509 xmaddr_t maddr;
510 struct multicall_space mc;
511
512 if (desc_equal(shadow, &t->tls_array[i]))
513 return;
514
515 *shadow = t->tls_array[i];
516
517 gdt = get_cpu_gdt_rw(cpu);
518 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
519 mc = __xen_mc_entry(0);
520
521 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
522}
523
524static void xen_load_tls(struct thread_struct *t, unsigned int cpu)
525{
526
527
528
529
530
531 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)
532 loadsegment(fs, 0);
533
534 xen_mc_batch();
535
536 load_TLS_descriptor(t, cpu, 0);
537 load_TLS_descriptor(t, cpu, 1);
538 load_TLS_descriptor(t, cpu, 2);
539
540 xen_mc_issue(PARAVIRT_LAZY_CPU);
541}
542
543static void xen_load_gs_index(unsigned int idx)
544{
545 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx))
546 BUG();
547}
548
549static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum,
550 const void *ptr)
551{
552 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]);
553 u64 entry = *(u64 *)ptr;
554
555 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry);
556
557 preempt_disable();
558
559 xen_mc_flush();
560 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry))
561 BUG();
562
563 preempt_enable();
564}
565
566void noist_exc_debug(struct pt_regs *regs);
567
568DEFINE_IDTENTRY_RAW(xenpv_exc_nmi)
569{
570
571 exc_nmi(regs);
572}
573
574DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault)
575{
576
577 exc_double_fault(regs, error_code);
578}
579
580DEFINE_IDTENTRY_RAW(xenpv_exc_debug)
581{
582
583
584
585
586 if (user_mode(regs))
587 noist_exc_debug(regs);
588 else
589 exc_debug(regs);
590}
591
592DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap)
593{
594
595 instrumentation_begin();
596 pr_err("Unknown trap in Xen PV mode.");
597 BUG();
598 instrumentation_end();
599}
600
601#ifdef CONFIG_X86_MCE
602DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check)
603{
604
605
606
607
608 if (user_mode(regs))
609 noist_exc_machine_check(regs);
610 else
611 exc_machine_check(regs);
612}
613#endif
614
615struct trap_array_entry {
616 void (*orig)(void);
617 void (*xen)(void);
618 bool ist_okay;
619};
620
621#define TRAP_ENTRY(func, ist_ok) { \
622 .orig = asm_##func, \
623 .xen = xen_asm_##func, \
624 .ist_okay = ist_ok }
625
626#define TRAP_ENTRY_REDIR(func, ist_ok) { \
627 .orig = asm_##func, \
628 .xen = xen_asm_xenpv_##func, \
629 .ist_okay = ist_ok }
630
631static struct trap_array_entry trap_array[] = {
632 TRAP_ENTRY_REDIR(exc_debug, true ),
633 TRAP_ENTRY_REDIR(exc_double_fault, true ),
634#ifdef CONFIG_X86_MCE
635 TRAP_ENTRY_REDIR(exc_machine_check, true ),
636#endif
637 TRAP_ENTRY_REDIR(exc_nmi, true ),
638 TRAP_ENTRY(exc_int3, false ),
639 TRAP_ENTRY(exc_overflow, false ),
640#ifdef CONFIG_IA32_EMULATION
641 { entry_INT80_compat, xen_entry_INT80_compat, false },
642#endif
643 TRAP_ENTRY(exc_page_fault, false ),
644 TRAP_ENTRY(exc_divide_error, false ),
645 TRAP_ENTRY(exc_bounds, false ),
646 TRAP_ENTRY(exc_invalid_op, false ),
647 TRAP_ENTRY(exc_device_not_available, false ),
648 TRAP_ENTRY(exc_coproc_segment_overrun, false ),
649 TRAP_ENTRY(exc_invalid_tss, false ),
650 TRAP_ENTRY(exc_segment_not_present, false ),
651 TRAP_ENTRY(exc_stack_segment, false ),
652 TRAP_ENTRY(exc_general_protection, false ),
653 TRAP_ENTRY(exc_spurious_interrupt_bug, false ),
654 TRAP_ENTRY(exc_coprocessor_error, false ),
655 TRAP_ENTRY(exc_alignment_check, false ),
656 TRAP_ENTRY(exc_simd_coprocessor_error, false ),
657};
658
659static bool __ref get_trap_addr(void **addr, unsigned int ist)
660{
661 unsigned int nr;
662 bool ist_okay = false;
663 bool found = false;
664
665
666
667
668
669
670
671
672 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) {
673 struct trap_array_entry *entry = trap_array + nr;
674
675 if (*addr == entry->orig) {
676 *addr = entry->xen;
677 ist_okay = entry->ist_okay;
678 found = true;
679 break;
680 }
681 }
682
683 if (nr == ARRAY_SIZE(trap_array) &&
684 *addr >= (void *)early_idt_handler_array[0] &&
685 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) {
686 nr = (*addr - (void *)early_idt_handler_array[0]) /
687 EARLY_IDT_HANDLER_SIZE;
688 *addr = (void *)xen_early_idt_handler_array[nr];
689 found = true;
690 }
691
692 if (!found)
693 *addr = (void *)xen_asm_exc_xen_unknown_trap;
694
695 if (WARN_ON(found && ist != 0 && !ist_okay))
696 return false;
697
698 return true;
699}
700
701static int cvt_gate_to_trap(int vector, const gate_desc *val,
702 struct trap_info *info)
703{
704 unsigned long addr;
705
706 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT)
707 return 0;
708
709 info->vector = vector;
710
711 addr = gate_offset(val);
712 if (!get_trap_addr((void **)&addr, val->bits.ist))
713 return 0;
714 info->address = addr;
715
716 info->cs = gate_segment(val);
717 info->flags = val->bits.dpl;
718
719 if (val->bits.type == GATE_INTERRUPT)
720 info->flags |= 1 << 2;
721
722 return 1;
723}
724
725
726static DEFINE_PER_CPU(struct desc_ptr, idt_desc);
727
728
729
730static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g)
731{
732 unsigned long p = (unsigned long)&dt[entrynum];
733 unsigned long start, end;
734
735 trace_xen_cpu_write_idt_entry(dt, entrynum, g);
736
737 preempt_disable();
738
739 start = __this_cpu_read(idt_desc.address);
740 end = start + __this_cpu_read(idt_desc.size) + 1;
741
742 xen_mc_flush();
743
744 native_write_idt_entry(dt, entrynum, g);
745
746 if (p >= start && (p + 8) <= end) {
747 struct trap_info info[2];
748
749 info[1].address = 0;
750
751 if (cvt_gate_to_trap(entrynum, g, &info[0]))
752 if (HYPERVISOR_set_trap_table(info))
753 BUG();
754 }
755
756 preempt_enable();
757}
758
759static void xen_convert_trap_info(const struct desc_ptr *desc,
760 struct trap_info *traps)
761{
762 unsigned in, out, count;
763
764 count = (desc->size+1) / sizeof(gate_desc);
765 BUG_ON(count > 256);
766
767 for (in = out = 0; in < count; in++) {
768 gate_desc *entry = (gate_desc *)(desc->address) + in;
769
770 if (cvt_gate_to_trap(in, entry, &traps[out]))
771 out++;
772 }
773 traps[out].address = 0;
774}
775
776void xen_copy_trap_info(struct trap_info *traps)
777{
778 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc);
779
780 xen_convert_trap_info(desc, traps);
781}
782
783
784
785
786static void xen_load_idt(const struct desc_ptr *desc)
787{
788 static DEFINE_SPINLOCK(lock);
789 static struct trap_info traps[257];
790
791 trace_xen_cpu_load_idt(desc);
792
793 spin_lock(&lock);
794
795 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc));
796
797 xen_convert_trap_info(desc, traps);
798
799 xen_mc_flush();
800 if (HYPERVISOR_set_trap_table(traps))
801 BUG();
802
803 spin_unlock(&lock);
804}
805
806
807
808static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
809 const void *desc, int type)
810{
811 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
812
813 preempt_disable();
814
815 switch (type) {
816 case DESC_LDT:
817 case DESC_TSS:
818
819 break;
820
821 default: {
822 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]);
823
824 xen_mc_flush();
825 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
826 BUG();
827 }
828
829 }
830
831 preempt_enable();
832}
833
834
835
836
837
838static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
839 const void *desc, int type)
840{
841 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type);
842
843 switch (type) {
844 case DESC_LDT:
845 case DESC_TSS:
846
847 break;
848
849 default: {
850 xmaddr_t maddr = virt_to_machine(&dt[entry]);
851
852 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
853 dt[entry] = *(struct desc_struct *)desc;
854 }
855
856 }
857}
858
859static void xen_load_sp0(unsigned long sp0)
860{
861 struct multicall_space mcs;
862
863 mcs = xen_mc_entry(0);
864 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0);
865 xen_mc_issue(PARAVIRT_LAZY_CPU);
866 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
867}
868
869#ifdef CONFIG_X86_IOPL_IOPERM
870static void xen_invalidate_io_bitmap(void)
871{
872 struct physdev_set_iobitmap iobitmap = {
873 .bitmap = NULL,
874 .nr_ports = 0,
875 };
876
877 native_tss_invalidate_io_bitmap();
878 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
879}
880
881static void xen_update_io_bitmap(void)
882{
883 struct physdev_set_iobitmap iobitmap;
884 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
885
886 native_tss_update_io_bitmap();
887
888 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) +
889 tss->x86_tss.io_bitmap_base;
890 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID)
891 iobitmap.nr_ports = 0;
892 else
893 iobitmap.nr_ports = IO_BITMAP_BITS;
894
895 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap);
896}
897#endif
898
899static void xen_io_delay(void)
900{
901}
902
903static DEFINE_PER_CPU(unsigned long, xen_cr0_value);
904
905static unsigned long xen_read_cr0(void)
906{
907 unsigned long cr0 = this_cpu_read(xen_cr0_value);
908
909 if (unlikely(cr0 == 0)) {
910 cr0 = native_read_cr0();
911 this_cpu_write(xen_cr0_value, cr0);
912 }
913
914 return cr0;
915}
916
917static void xen_write_cr0(unsigned long cr0)
918{
919 struct multicall_space mcs;
920
921 this_cpu_write(xen_cr0_value, cr0);
922
923
924
925 mcs = xen_mc_entry(0);
926
927 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0);
928
929 xen_mc_issue(PARAVIRT_LAZY_CPU);
930}
931
932static void xen_write_cr4(unsigned long cr4)
933{
934 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE);
935
936 native_write_cr4(cr4);
937}
938
939static u64 xen_read_msr_safe(unsigned int msr, int *err)
940{
941 u64 val;
942
943 if (pmu_msr_read(msr, &val, err))
944 return val;
945
946 val = native_read_msr_safe(msr, err);
947 switch (msr) {
948 case MSR_IA32_APICBASE:
949 val &= ~X2APIC_ENABLE;
950 break;
951 }
952 return val;
953}
954
955static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
956{
957 int ret;
958 unsigned int which;
959 u64 base;
960
961 ret = 0;
962
963 switch (msr) {
964 case MSR_FS_BASE: which = SEGBASE_FS; goto set;
965 case MSR_KERNEL_GS_BASE: which = SEGBASE_GS_USER; goto set;
966 case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set;
967
968 set:
969 base = ((u64)high << 32) | low;
970 if (HYPERVISOR_set_segment_base(which, base) != 0)
971 ret = -EIO;
972 break;
973
974 case MSR_STAR:
975 case MSR_CSTAR:
976 case MSR_LSTAR:
977 case MSR_SYSCALL_MASK:
978 case MSR_IA32_SYSENTER_CS:
979 case MSR_IA32_SYSENTER_ESP:
980 case MSR_IA32_SYSENTER_EIP:
981
982
983
984 break;
985
986 default:
987 if (!pmu_msr_write(msr, low, high, &ret))
988 ret = native_write_msr_safe(msr, low, high);
989 }
990
991 return ret;
992}
993
994static u64 xen_read_msr(unsigned int msr)
995{
996
997
998
999
1000 int err;
1001
1002 return xen_read_msr_safe(msr, &err);
1003}
1004
1005static void xen_write_msr(unsigned int msr, unsigned low, unsigned high)
1006{
1007
1008
1009
1010
1011 xen_write_msr_safe(msr, low, high);
1012}
1013
1014
1015void __init xen_setup_vcpu_info_placement(void)
1016{
1017 int cpu;
1018
1019 for_each_possible_cpu(cpu) {
1020
1021 per_cpu(xen_vcpu_id, cpu) = cpu;
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031 (void) xen_vcpu_setup(cpu);
1032 }
1033
1034
1035
1036
1037
1038 if (xen_have_vcpu_info_placement) {
1039 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct);
1040 pv_ops.irq.irq_disable =
1041 __PV_IS_CALLEE_SAVE(xen_irq_disable_direct);
1042 pv_ops.irq.irq_enable =
1043 __PV_IS_CALLEE_SAVE(xen_irq_enable_direct);
1044 pv_ops.mmu.read_cr2 =
1045 __PV_IS_CALLEE_SAVE(xen_read_cr2_direct);
1046 }
1047}
1048
1049static const struct pv_info xen_info __initconst = {
1050 .extra_user_64bit_cs = FLAT_USER_CS64,
1051 .name = "Xen",
1052};
1053
1054static const struct pv_cpu_ops xen_cpu_ops __initconst = {
1055 .cpuid = xen_cpuid,
1056
1057 .set_debugreg = xen_set_debugreg,
1058 .get_debugreg = xen_get_debugreg,
1059
1060 .read_cr0 = xen_read_cr0,
1061 .write_cr0 = xen_write_cr0,
1062
1063 .write_cr4 = xen_write_cr4,
1064
1065 .wbinvd = native_wbinvd,
1066
1067 .read_msr = xen_read_msr,
1068 .write_msr = xen_write_msr,
1069
1070 .read_msr_safe = xen_read_msr_safe,
1071 .write_msr_safe = xen_write_msr_safe,
1072
1073 .read_pmc = xen_read_pmc,
1074
1075 .load_tr_desc = paravirt_nop,
1076 .set_ldt = xen_set_ldt,
1077 .load_gdt = xen_load_gdt,
1078 .load_idt = xen_load_idt,
1079 .load_tls = xen_load_tls,
1080 .load_gs_index = xen_load_gs_index,
1081
1082 .alloc_ldt = xen_alloc_ldt,
1083 .free_ldt = xen_free_ldt,
1084
1085 .store_tr = xen_store_tr,
1086
1087 .write_ldt_entry = xen_write_ldt_entry,
1088 .write_gdt_entry = xen_write_gdt_entry,
1089 .write_idt_entry = xen_write_idt_entry,
1090 .load_sp0 = xen_load_sp0,
1091
1092#ifdef CONFIG_X86_IOPL_IOPERM
1093 .invalidate_io_bitmap = xen_invalidate_io_bitmap,
1094 .update_io_bitmap = xen_update_io_bitmap,
1095#endif
1096 .io_delay = xen_io_delay,
1097
1098 .start_context_switch = paravirt_start_context_switch,
1099 .end_context_switch = xen_end_context_switch,
1100};
1101
1102static void xen_restart(char *msg)
1103{
1104 xen_reboot(SHUTDOWN_reboot);
1105}
1106
1107static void xen_machine_halt(void)
1108{
1109 xen_reboot(SHUTDOWN_poweroff);
1110}
1111
1112static void xen_machine_power_off(void)
1113{
1114 if (pm_power_off)
1115 pm_power_off();
1116 xen_reboot(SHUTDOWN_poweroff);
1117}
1118
1119static void xen_crash_shutdown(struct pt_regs *regs)
1120{
1121 xen_reboot(SHUTDOWN_crash);
1122}
1123
1124static const struct machine_ops xen_machine_ops __initconst = {
1125 .restart = xen_restart,
1126 .halt = xen_machine_halt,
1127 .power_off = xen_machine_power_off,
1128 .shutdown = xen_machine_halt,
1129 .crash_shutdown = xen_crash_shutdown,
1130 .emergency_restart = xen_emergency_restart,
1131};
1132
1133static unsigned char xen_get_nmi_reason(void)
1134{
1135 unsigned char reason = 0;
1136
1137
1138 if (test_bit(_XEN_NMIREASON_io_error,
1139 &HYPERVISOR_shared_info->arch.nmi_reason))
1140 reason |= NMI_REASON_IOCHK;
1141 if (test_bit(_XEN_NMIREASON_pci_serr,
1142 &HYPERVISOR_shared_info->arch.nmi_reason))
1143 reason |= NMI_REASON_SERR;
1144
1145 return reason;
1146}
1147
1148static void __init xen_boot_params_init_edd(void)
1149{
1150#if IS_ENABLED(CONFIG_EDD)
1151 struct xen_platform_op op;
1152 struct edd_info *edd_info;
1153 u32 *mbr_signature;
1154 unsigned nr;
1155 int ret;
1156
1157 edd_info = boot_params.eddbuf;
1158 mbr_signature = boot_params.edd_mbr_sig_buffer;
1159
1160 op.cmd = XENPF_firmware_info;
1161
1162 op.u.firmware_info.type = XEN_FW_DISK_INFO;
1163 for (nr = 0; nr < EDDMAXNR; nr++) {
1164 struct edd_info *info = edd_info + nr;
1165
1166 op.u.firmware_info.index = nr;
1167 info->params.length = sizeof(info->params);
1168 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params,
1169 &info->params);
1170 ret = HYPERVISOR_platform_op(&op);
1171 if (ret)
1172 break;
1173
1174#define C(x) info->x = op.u.firmware_info.u.disk_info.x
1175 C(device);
1176 C(version);
1177 C(interface_support);
1178 C(legacy_max_cylinder);
1179 C(legacy_max_head);
1180 C(legacy_sectors_per_track);
1181#undef C
1182 }
1183 boot_params.eddbuf_entries = nr;
1184
1185 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE;
1186 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) {
1187 op.u.firmware_info.index = nr;
1188 ret = HYPERVISOR_platform_op(&op);
1189 if (ret)
1190 break;
1191 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature;
1192 }
1193 boot_params.edd_mbr_sig_buf_entries = nr;
1194#endif
1195}
1196
1197
1198
1199
1200
1201
1202static void __init xen_setup_gdt(int cpu)
1203{
1204 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot;
1205 pv_ops.cpu.load_gdt = xen_load_gdt_boot;
1206
1207 switch_to_new_gdt(cpu);
1208
1209 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry;
1210 pv_ops.cpu.load_gdt = xen_load_gdt;
1211}
1212
1213static void __init xen_dom0_set_legacy_features(void)
1214{
1215 x86_platform.legacy.rtc = 1;
1216}
1217
1218
1219asmlinkage __visible void __init xen_start_kernel(void)
1220{
1221 struct physdev_set_iopl set_iopl;
1222 unsigned long initrd_start = 0;
1223 int rc;
1224
1225 if (!xen_start_info)
1226 return;
1227
1228 xen_domain_type = XEN_PV_DOMAIN;
1229 xen_start_flags = xen_start_info->flags;
1230
1231 xen_setup_features();
1232
1233
1234 pv_info = xen_info;
1235 pv_ops.cpu = xen_cpu_ops;
1236 paravirt_iret = xen_iret;
1237 xen_init_irq_ops();
1238
1239
1240
1241
1242
1243
1244
1245
1246 xen_vcpu_info_reset(0);
1247
1248 x86_platform.get_nmi_reason = xen_get_nmi_reason;
1249
1250 x86_init.resources.memory_setup = xen_memory_setup;
1251 x86_init.irqs.intr_mode_select = x86_init_noop;
1252 x86_init.irqs.intr_mode_init = x86_init_noop;
1253 x86_init.oem.arch_setup = xen_arch_setup;
1254 x86_init.oem.banner = xen_banner;
1255 x86_init.hyper.init_platform = xen_pv_init_platform;
1256 x86_init.hyper.guest_late_init = xen_pv_guest_late_init;
1257
1258
1259
1260
1261
1262 xen_setup_machphys_mapping();
1263 xen_init_mmu_ops();
1264
1265
1266 __supported_pte_mask &= ~_PAGE_GLOBAL;
1267 __default_kernel_pte_mask &= ~_PAGE_GLOBAL;
1268
1269
1270
1271
1272
1273 __userpte_alloc_gfp &= ~__GFP_HIGHMEM;
1274
1275
1276 xen_build_dynamic_phys_to_machine();
1277
1278
1279 get_cpu_cap(&boot_cpu_data);
1280 x86_configure_nx();
1281
1282
1283
1284
1285
1286 xen_setup_gdt(0);
1287
1288
1289 get_cpu_address_sizes(&boot_cpu_data);
1290
1291
1292 per_cpu(xen_vcpu_id, 0) = 0;
1293
1294 idt_setup_early_handler();
1295
1296 xen_init_capabilities();
1297
1298#ifdef CONFIG_X86_LOCAL_APIC
1299
1300
1301
1302 xen_init_apic();
1303#endif
1304
1305 if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) {
1306 pv_ops.mmu.ptep_modify_prot_start =
1307 xen_ptep_modify_prot_start;
1308 pv_ops.mmu.ptep_modify_prot_commit =
1309 xen_ptep_modify_prot_commit;
1310 }
1311
1312 machine_ops = xen_machine_ops;
1313
1314
1315
1316
1317
1318
1319 xen_initial_gdt = &per_cpu(gdt_page, 0);
1320
1321 xen_smp_init();
1322
1323#ifdef CONFIG_ACPI_NUMA
1324
1325
1326
1327
1328
1329 disable_srat();
1330#endif
1331 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv));
1332
1333 local_irq_disable();
1334 early_boot_irqs_disabled = true;
1335
1336 xen_raw_console_write("mapping kernel into physical memory\n");
1337 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base,
1338 xen_start_info->nr_pages);
1339 xen_reserve_special_pages();
1340
1341
1342
1343
1344
1345
1346 set_iopl.iopl = 1;
1347 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl);
1348 if (rc != 0)
1349 xen_raw_printk("physdev_op failed %d\n", rc);
1350
1351
1352 if (xen_start_info->mod_start) {
1353 if (xen_start_info->flags & SIF_MOD_START_PFN)
1354 initrd_start = PFN_PHYS(xen_start_info->mod_start);
1355 else
1356 initrd_start = __pa(xen_start_info->mod_start);
1357 }
1358
1359
1360 boot_params.hdr.type_of_loader = (9 << 4) | 0;
1361 boot_params.hdr.ramdisk_image = initrd_start;
1362 boot_params.hdr.ramdisk_size = xen_start_info->mod_len;
1363 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line);
1364 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN;
1365
1366 if (!xen_initial_domain()) {
1367 add_preferred_console("xenboot", 0, NULL);
1368 if (pci_xen)
1369 x86_init.pci.arch_init = pci_xen_init;
1370 } else {
1371 const struct dom0_vga_console_info *info =
1372 (void *)((char *)xen_start_info +
1373 xen_start_info->console.dom0.info_off);
1374 struct xen_platform_op op = {
1375 .cmd = XENPF_firmware_info,
1376 .interface_version = XENPF_INTERFACE_VERSION,
1377 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS,
1378 };
1379
1380 x86_platform.set_legacy_features =
1381 xen_dom0_set_legacy_features;
1382 xen_init_vga(info, xen_start_info->console.dom0.info_size);
1383 xen_start_info->console.domU.mfn = 0;
1384 xen_start_info->console.domU.evtchn = 0;
1385
1386 if (HYPERVISOR_platform_op(&op) == 0)
1387 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags;
1388
1389
1390 pci_request_acs();
1391
1392 xen_acpi_sleep_register();
1393
1394
1395 x86_init.mpparse.find_smp_config = x86_init_noop;
1396 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
1397
1398 xen_boot_params_init_edd();
1399
1400#ifdef CONFIG_ACPI
1401
1402
1403
1404
1405
1406 acpi_disable_cmcff = 1;
1407#endif
1408 }
1409
1410 if (!boot_params.screen_info.orig_video_isVGA)
1411 add_preferred_console("tty", 0, NULL);
1412 add_preferred_console("hvc", 0, NULL);
1413 if (boot_params.screen_info.orig_video_isVGA)
1414 add_preferred_console("tty", 0, NULL);
1415
1416#ifdef CONFIG_PCI
1417
1418 pci_probe &= ~PCI_PROBE_BIOS;
1419#endif
1420 xen_raw_console_write("about to get started...\n");
1421
1422
1423 xen_setup_runstate_info(0);
1424
1425 xen_efi_init(&boot_params);
1426
1427
1428 cr4_init_shadow();
1429 x86_64_start_reservations((char *)__pa_symbol(&boot_params));
1430}
1431
1432static int xen_cpu_up_prepare_pv(unsigned int cpu)
1433{
1434 int rc;
1435
1436 if (per_cpu(xen_vcpu, cpu) == NULL)
1437 return -ENODEV;
1438
1439 xen_setup_timer(cpu);
1440
1441 rc = xen_smp_intr_init(cpu);
1442 if (rc) {
1443 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n",
1444 cpu, rc);
1445 return rc;
1446 }
1447
1448 rc = xen_smp_intr_init_pv(cpu);
1449 if (rc) {
1450 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n",
1451 cpu, rc);
1452 return rc;
1453 }
1454
1455 return 0;
1456}
1457
1458static int xen_cpu_dead_pv(unsigned int cpu)
1459{
1460 xen_smp_intr_free(cpu);
1461 xen_smp_intr_free_pv(cpu);
1462
1463 xen_teardown_timer(cpu);
1464
1465 return 0;
1466}
1467
1468static uint32_t __init xen_platform_pv(void)
1469{
1470 if (xen_pv_domain())
1471 return xen_cpuid_base();
1472
1473 return 0;
1474}
1475
1476const __initconst struct hypervisor_x86 x86_hyper_xen_pv = {
1477 .name = "Xen PV",
1478 .detect = xen_platform_pv,
1479 .type = X86_HYPER_XEN_PV,
1480 .runtime.pin_vcpu = xen_pin_vcpu,
1481 .ignore_nopv = true,
1482};
1483