linux/arch/x86/kernel/process.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0
   2#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   3
   4#include <linux/errno.h>
   5#include <linux/kernel.h>
   6#include <linux/mm.h>
   7#include <linux/smp.h>
   8#include <linux/prctl.h>
   9#include <linux/slab.h>
  10#include <linux/sched.h>
  11#include <linux/sched/idle.h>
  12#include <linux/sched/debug.h>
  13#include <linux/sched/task.h>
  14#include <linux/sched/task_stack.h>
  15#include <linux/init.h>
  16#include <linux/export.h>
  17#include <linux/pm.h>
  18#include <linux/tick.h>
  19#include <linux/random.h>
  20#include <linux/user-return-notifier.h>
  21#include <linux/dmi.h>
  22#include <linux/utsname.h>
  23#include <linux/stackprotector.h>
  24#include <linux/cpuidle.h>
  25#include <linux/acpi.h>
  26#include <linux/elf-randomize.h>
  27#include <trace/events/power.h>
  28#include <linux/hw_breakpoint.h>
  29#include <asm/cpu.h>
  30#include <asm/apic.h>
  31#include <linux/uaccess.h>
  32#include <asm/mwait.h>
  33#include <asm/fpu/internal.h>
  34#include <asm/debugreg.h>
  35#include <asm/nmi.h>
  36#include <asm/tlbflush.h>
  37#include <asm/mce.h>
  38#include <asm/vm86.h>
  39#include <asm/switch_to.h>
  40#include <asm/desc.h>
  41#include <asm/prctl.h>
  42#include <asm/spec-ctrl.h>
  43#include <asm/io_bitmap.h>
  44#include <asm/proto.h>
  45#include <asm/frame.h>
  46
  47#include "process.h"
  48
  49/*
  50 * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  51 * no more per-task TSS's. The TSS size is kept cacheline-aligned
  52 * so they are allowed to end up in the .data..cacheline_aligned
  53 * section. Since TSS's are completely CPU-local, we want them
  54 * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  55 */
  56__visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
  57        .x86_tss = {
  58                /*
  59                 * .sp0 is only used when entering ring 0 from a lower
  60                 * privilege level.  Since the init task never runs anything
  61                 * but ring 0 code, there is no need for a valid value here.
  62                 * Poison it.
  63                 */
  64                .sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
  65
  66#ifdef CONFIG_X86_32
  67                .sp1 = TOP_OF_INIT_STACK,
  68
  69                .ss0 = __KERNEL_DS,
  70                .ss1 = __KERNEL_CS,
  71#endif
  72                .io_bitmap_base = IO_BITMAP_OFFSET_INVALID,
  73         },
  74};
  75EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
  76
  77DEFINE_PER_CPU(bool, __tss_limit_invalid);
  78EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
  79
  80/*
  81 * this gets called so that we can store lazy state into memory and copy the
  82 * current task into the new thread.
  83 */
  84int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  85{
  86        memcpy(dst, src, arch_task_struct_size);
  87#ifdef CONFIG_VM86
  88        dst->thread.vm86 = NULL;
  89#endif
  90        return fpu_clone(dst);
  91}
  92
  93/*
  94 * Free thread data structures etc..
  95 */
  96void exit_thread(struct task_struct *tsk)
  97{
  98        struct thread_struct *t = &tsk->thread;
  99        struct fpu *fpu = &t->fpu;
 100
 101        if (test_thread_flag(TIF_IO_BITMAP))
 102                io_bitmap_exit(tsk);
 103
 104        free_vm86(t);
 105
 106        fpu__drop(fpu);
 107}
 108
 109static int set_new_tls(struct task_struct *p, unsigned long tls)
 110{
 111        struct user_desc __user *utls = (struct user_desc __user *)tls;
 112
 113        if (in_ia32_syscall())
 114                return do_set_thread_area(p, -1, utls, 0);
 115        else
 116                return do_set_thread_area_64(p, ARCH_SET_FS, tls);
 117}
 118
 119int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
 120                struct task_struct *p, unsigned long tls)
 121{
 122        struct inactive_task_frame *frame;
 123        struct fork_frame *fork_frame;
 124        struct pt_regs *childregs;
 125        int ret = 0;
 126
 127        childregs = task_pt_regs(p);
 128        fork_frame = container_of(childregs, struct fork_frame, regs);
 129        frame = &fork_frame->frame;
 130
 131        frame->bp = encode_frame_pointer(childregs);
 132        frame->ret_addr = (unsigned long) ret_from_fork;
 133        p->thread.sp = (unsigned long) fork_frame;
 134        p->thread.io_bitmap = NULL;
 135        memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
 136
 137#ifdef CONFIG_X86_64
 138        current_save_fsgs();
 139        p->thread.fsindex = current->thread.fsindex;
 140        p->thread.fsbase = current->thread.fsbase;
 141        p->thread.gsindex = current->thread.gsindex;
 142        p->thread.gsbase = current->thread.gsbase;
 143
 144        savesegment(es, p->thread.es);
 145        savesegment(ds, p->thread.ds);
 146#else
 147        p->thread.sp0 = (unsigned long) (childregs + 1);
 148        /*
 149         * Clear all status flags including IF and set fixed bit. 64bit
 150         * does not have this initialization as the frame does not contain
 151         * flags. The flags consistency (especially vs. AC) is there
 152         * ensured via objtool, which lacks 32bit support.
 153         */
 154        frame->flags = X86_EFLAGS_FIXED;
 155#endif
 156
 157        /* Kernel thread ? */
 158        if (unlikely(p->flags & PF_KTHREAD)) {
 159                p->thread.pkru = pkru_get_init_value();
 160                memset(childregs, 0, sizeof(struct pt_regs));
 161                kthread_frame_init(frame, sp, arg);
 162                return 0;
 163        }
 164
 165        /*
 166         * Clone current's PKRU value from hardware. tsk->thread.pkru
 167         * is only valid when scheduled out.
 168         */
 169        p->thread.pkru = read_pkru();
 170
 171        frame->bx = 0;
 172        *childregs = *current_pt_regs();
 173        childregs->ax = 0;
 174        if (sp)
 175                childregs->sp = sp;
 176
 177#ifdef CONFIG_X86_32
 178        task_user_gs(p) = get_user_gs(current_pt_regs());
 179#endif
 180
 181        if (unlikely(p->flags & PF_IO_WORKER)) {
 182                /*
 183                 * An IO thread is a user space thread, but it doesn't
 184                 * return to ret_after_fork().
 185                 *
 186                 * In order to indicate that to tools like gdb,
 187                 * we reset the stack and instruction pointers.
 188                 *
 189                 * It does the same kernel frame setup to return to a kernel
 190                 * function that a kernel thread does.
 191                 */
 192                childregs->sp = 0;
 193                childregs->ip = 0;
 194                kthread_frame_init(frame, sp, arg);
 195                return 0;
 196        }
 197
 198        /* Set a new TLS for the child thread? */
 199        if (clone_flags & CLONE_SETTLS)
 200                ret = set_new_tls(p, tls);
 201
 202        if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
 203                io_bitmap_share(p);
 204
 205        return ret;
 206}
 207
 208static void pkru_flush_thread(void)
 209{
 210        /*
 211         * If PKRU is enabled the default PKRU value has to be loaded into
 212         * the hardware right here (similar to context switch).
 213         */
 214        pkru_write_default();
 215}
 216
 217void flush_thread(void)
 218{
 219        struct task_struct *tsk = current;
 220
 221        flush_ptrace_hw_breakpoint(tsk);
 222        memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 223
 224        fpu_flush_thread();
 225        pkru_flush_thread();
 226}
 227
 228void disable_TSC(void)
 229{
 230        preempt_disable();
 231        if (!test_and_set_thread_flag(TIF_NOTSC))
 232                /*
 233                 * Must flip the CPU state synchronously with
 234                 * TIF_NOTSC in the current running context.
 235                 */
 236                cr4_set_bits(X86_CR4_TSD);
 237        preempt_enable();
 238}
 239
 240static void enable_TSC(void)
 241{
 242        preempt_disable();
 243        if (test_and_clear_thread_flag(TIF_NOTSC))
 244                /*
 245                 * Must flip the CPU state synchronously with
 246                 * TIF_NOTSC in the current running context.
 247                 */
 248                cr4_clear_bits(X86_CR4_TSD);
 249        preempt_enable();
 250}
 251
 252int get_tsc_mode(unsigned long adr)
 253{
 254        unsigned int val;
 255
 256        if (test_thread_flag(TIF_NOTSC))
 257                val = PR_TSC_SIGSEGV;
 258        else
 259                val = PR_TSC_ENABLE;
 260
 261        return put_user(val, (unsigned int __user *)adr);
 262}
 263
 264int set_tsc_mode(unsigned int val)
 265{
 266        if (val == PR_TSC_SIGSEGV)
 267                disable_TSC();
 268        else if (val == PR_TSC_ENABLE)
 269                enable_TSC();
 270        else
 271                return -EINVAL;
 272
 273        return 0;
 274}
 275
 276DEFINE_PER_CPU(u64, msr_misc_features_shadow);
 277
 278static void set_cpuid_faulting(bool on)
 279{
 280        u64 msrval;
 281
 282        msrval = this_cpu_read(msr_misc_features_shadow);
 283        msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
 284        msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
 285        this_cpu_write(msr_misc_features_shadow, msrval);
 286        wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
 287}
 288
 289static void disable_cpuid(void)
 290{
 291        preempt_disable();
 292        if (!test_and_set_thread_flag(TIF_NOCPUID)) {
 293                /*
 294                 * Must flip the CPU state synchronously with
 295                 * TIF_NOCPUID in the current running context.
 296                 */
 297                set_cpuid_faulting(true);
 298        }
 299        preempt_enable();
 300}
 301
 302static void enable_cpuid(void)
 303{
 304        preempt_disable();
 305        if (test_and_clear_thread_flag(TIF_NOCPUID)) {
 306                /*
 307                 * Must flip the CPU state synchronously with
 308                 * TIF_NOCPUID in the current running context.
 309                 */
 310                set_cpuid_faulting(false);
 311        }
 312        preempt_enable();
 313}
 314
 315static int get_cpuid_mode(void)
 316{
 317        return !test_thread_flag(TIF_NOCPUID);
 318}
 319
 320static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
 321{
 322        if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
 323                return -ENODEV;
 324
 325        if (cpuid_enabled)
 326                enable_cpuid();
 327        else
 328                disable_cpuid();
 329
 330        return 0;
 331}
 332
 333/*
 334 * Called immediately after a successful exec.
 335 */
 336void arch_setup_new_exec(void)
 337{
 338        /* If cpuid was previously disabled for this task, re-enable it. */
 339        if (test_thread_flag(TIF_NOCPUID))
 340                enable_cpuid();
 341
 342        /*
 343         * Don't inherit TIF_SSBD across exec boundary when
 344         * PR_SPEC_DISABLE_NOEXEC is used.
 345         */
 346        if (test_thread_flag(TIF_SSBD) &&
 347            task_spec_ssb_noexec(current)) {
 348                clear_thread_flag(TIF_SSBD);
 349                task_clear_spec_ssb_disable(current);
 350                task_clear_spec_ssb_noexec(current);
 351                speculation_ctrl_update(task_thread_info(current)->flags);
 352        }
 353}
 354
 355#ifdef CONFIG_X86_IOPL_IOPERM
 356static inline void switch_to_bitmap(unsigned long tifp)
 357{
 358        /*
 359         * Invalidate I/O bitmap if the previous task used it. This prevents
 360         * any possible leakage of an active I/O bitmap.
 361         *
 362         * If the next task has an I/O bitmap it will handle it on exit to
 363         * user mode.
 364         */
 365        if (tifp & _TIF_IO_BITMAP)
 366                tss_invalidate_io_bitmap();
 367}
 368
 369static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
 370{
 371        /*
 372         * Copy at least the byte range of the incoming tasks bitmap which
 373         * covers the permitted I/O ports.
 374         *
 375         * If the previous task which used an I/O bitmap had more bits
 376         * permitted, then the copy needs to cover those as well so they
 377         * get turned off.
 378         */
 379        memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
 380               max(tss->io_bitmap.prev_max, iobm->max));
 381
 382        /*
 383         * Store the new max and the sequence number of this bitmap
 384         * and a pointer to the bitmap itself.
 385         */
 386        tss->io_bitmap.prev_max = iobm->max;
 387        tss->io_bitmap.prev_sequence = iobm->sequence;
 388}
 389
 390/**
 391 * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
 392 */
 393void native_tss_update_io_bitmap(void)
 394{
 395        struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
 396        struct thread_struct *t = &current->thread;
 397        u16 *base = &tss->x86_tss.io_bitmap_base;
 398
 399        if (!test_thread_flag(TIF_IO_BITMAP)) {
 400                native_tss_invalidate_io_bitmap();
 401                return;
 402        }
 403
 404        if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
 405                *base = IO_BITMAP_OFFSET_VALID_ALL;
 406        } else {
 407                struct io_bitmap *iobm = t->io_bitmap;
 408
 409                /*
 410                 * Only copy bitmap data when the sequence number differs. The
 411                 * update time is accounted to the incoming task.
 412                 */
 413                if (tss->io_bitmap.prev_sequence != iobm->sequence)
 414                        tss_copy_io_bitmap(tss, iobm);
 415
 416                /* Enable the bitmap */
 417                *base = IO_BITMAP_OFFSET_VALID_MAP;
 418        }
 419
 420        /*
 421         * Make sure that the TSS limit is covering the IO bitmap. It might have
 422         * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
 423         * access from user space to trigger a #GP because tbe bitmap is outside
 424         * the TSS limit.
 425         */
 426        refresh_tss_limit();
 427}
 428#else /* CONFIG_X86_IOPL_IOPERM */
 429static inline void switch_to_bitmap(unsigned long tifp) { }
 430#endif
 431
 432#ifdef CONFIG_SMP
 433
 434struct ssb_state {
 435        struct ssb_state        *shared_state;
 436        raw_spinlock_t          lock;
 437        unsigned int            disable_state;
 438        unsigned long           local_state;
 439};
 440
 441#define LSTATE_SSB      0
 442
 443static DEFINE_PER_CPU(struct ssb_state, ssb_state);
 444
 445void speculative_store_bypass_ht_init(void)
 446{
 447        struct ssb_state *st = this_cpu_ptr(&ssb_state);
 448        unsigned int this_cpu = smp_processor_id();
 449        unsigned int cpu;
 450
 451        st->local_state = 0;
 452
 453        /*
 454         * Shared state setup happens once on the first bringup
 455         * of the CPU. It's not destroyed on CPU hotunplug.
 456         */
 457        if (st->shared_state)
 458                return;
 459
 460        raw_spin_lock_init(&st->lock);
 461
 462        /*
 463         * Go over HT siblings and check whether one of them has set up the
 464         * shared state pointer already.
 465         */
 466        for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
 467                if (cpu == this_cpu)
 468                        continue;
 469
 470                if (!per_cpu(ssb_state, cpu).shared_state)
 471                        continue;
 472
 473                /* Link it to the state of the sibling: */
 474                st->shared_state = per_cpu(ssb_state, cpu).shared_state;
 475                return;
 476        }
 477
 478        /*
 479         * First HT sibling to come up on the core.  Link shared state of
 480         * the first HT sibling to itself. The siblings on the same core
 481         * which come up later will see the shared state pointer and link
 482         * themselves to the state of this CPU.
 483         */
 484        st->shared_state = st;
 485}
 486
 487/*
 488 * Logic is: First HT sibling enables SSBD for both siblings in the core
 489 * and last sibling to disable it, disables it for the whole core. This how
 490 * MSR_SPEC_CTRL works in "hardware":
 491 *
 492 *  CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
 493 */
 494static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
 495{
 496        struct ssb_state *st = this_cpu_ptr(&ssb_state);
 497        u64 msr = x86_amd_ls_cfg_base;
 498
 499        if (!static_cpu_has(X86_FEATURE_ZEN)) {
 500                msr |= ssbd_tif_to_amd_ls_cfg(tifn);
 501                wrmsrl(MSR_AMD64_LS_CFG, msr);
 502                return;
 503        }
 504
 505        if (tifn & _TIF_SSBD) {
 506                /*
 507                 * Since this can race with prctl(), block reentry on the
 508                 * same CPU.
 509                 */
 510                if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
 511                        return;
 512
 513                msr |= x86_amd_ls_cfg_ssbd_mask;
 514
 515                raw_spin_lock(&st->shared_state->lock);
 516                /* First sibling enables SSBD: */
 517                if (!st->shared_state->disable_state)
 518                        wrmsrl(MSR_AMD64_LS_CFG, msr);
 519                st->shared_state->disable_state++;
 520                raw_spin_unlock(&st->shared_state->lock);
 521        } else {
 522                if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
 523                        return;
 524
 525                raw_spin_lock(&st->shared_state->lock);
 526                st->shared_state->disable_state--;
 527                if (!st->shared_state->disable_state)
 528                        wrmsrl(MSR_AMD64_LS_CFG, msr);
 529                raw_spin_unlock(&st->shared_state->lock);
 530        }
 531}
 532#else
 533static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
 534{
 535        u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
 536
 537        wrmsrl(MSR_AMD64_LS_CFG, msr);
 538}
 539#endif
 540
 541static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
 542{
 543        /*
 544         * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
 545         * so ssbd_tif_to_spec_ctrl() just works.
 546         */
 547        wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
 548}
 549
 550/*
 551 * Update the MSRs managing speculation control, during context switch.
 552 *
 553 * tifp: Previous task's thread flags
 554 * tifn: Next task's thread flags
 555 */
 556static __always_inline void __speculation_ctrl_update(unsigned long tifp,
 557                                                      unsigned long tifn)
 558{
 559        unsigned long tif_diff = tifp ^ tifn;
 560        u64 msr = x86_spec_ctrl_base;
 561        bool updmsr = false;
 562
 563        lockdep_assert_irqs_disabled();
 564
 565        /* Handle change of TIF_SSBD depending on the mitigation method. */
 566        if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
 567                if (tif_diff & _TIF_SSBD)
 568                        amd_set_ssb_virt_state(tifn);
 569        } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
 570                if (tif_diff & _TIF_SSBD)
 571                        amd_set_core_ssb_state(tifn);
 572        } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
 573                   static_cpu_has(X86_FEATURE_AMD_SSBD)) {
 574                updmsr |= !!(tif_diff & _TIF_SSBD);
 575                msr |= ssbd_tif_to_spec_ctrl(tifn);
 576        }
 577
 578        /* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
 579        if (IS_ENABLED(CONFIG_SMP) &&
 580            static_branch_unlikely(&switch_to_cond_stibp)) {
 581                updmsr |= !!(tif_diff & _TIF_SPEC_IB);
 582                msr |= stibp_tif_to_spec_ctrl(tifn);
 583        }
 584
 585        if (updmsr)
 586                wrmsrl(MSR_IA32_SPEC_CTRL, msr);
 587}
 588
 589static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
 590{
 591        if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
 592                if (task_spec_ssb_disable(tsk))
 593                        set_tsk_thread_flag(tsk, TIF_SSBD);
 594                else
 595                        clear_tsk_thread_flag(tsk, TIF_SSBD);
 596
 597                if (task_spec_ib_disable(tsk))
 598                        set_tsk_thread_flag(tsk, TIF_SPEC_IB);
 599                else
 600                        clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
 601        }
 602        /* Return the updated threadinfo flags*/
 603        return task_thread_info(tsk)->flags;
 604}
 605
 606void speculation_ctrl_update(unsigned long tif)
 607{
 608        unsigned long flags;
 609
 610        /* Forced update. Make sure all relevant TIF flags are different */
 611        local_irq_save(flags);
 612        __speculation_ctrl_update(~tif, tif);
 613        local_irq_restore(flags);
 614}
 615
 616/* Called from seccomp/prctl update */
 617void speculation_ctrl_update_current(void)
 618{
 619        preempt_disable();
 620        speculation_ctrl_update(speculation_ctrl_update_tif(current));
 621        preempt_enable();
 622}
 623
 624static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
 625{
 626        unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
 627
 628        newval = cr4 ^ mask;
 629        if (newval != cr4) {
 630                this_cpu_write(cpu_tlbstate.cr4, newval);
 631                __write_cr4(newval);
 632        }
 633}
 634
 635void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
 636{
 637        unsigned long tifp, tifn;
 638
 639        tifn = READ_ONCE(task_thread_info(next_p)->flags);
 640        tifp = READ_ONCE(task_thread_info(prev_p)->flags);
 641
 642        switch_to_bitmap(tifp);
 643
 644        propagate_user_return_notify(prev_p, next_p);
 645
 646        if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
 647            arch_has_block_step()) {
 648                unsigned long debugctl, msk;
 649
 650                rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 651                debugctl &= ~DEBUGCTLMSR_BTF;
 652                msk = tifn & _TIF_BLOCKSTEP;
 653                debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
 654                wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
 655        }
 656
 657        if ((tifp ^ tifn) & _TIF_NOTSC)
 658                cr4_toggle_bits_irqsoff(X86_CR4_TSD);
 659
 660        if ((tifp ^ tifn) & _TIF_NOCPUID)
 661                set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
 662
 663        if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
 664                __speculation_ctrl_update(tifp, tifn);
 665        } else {
 666                speculation_ctrl_update_tif(prev_p);
 667                tifn = speculation_ctrl_update_tif(next_p);
 668
 669                /* Enforce MSR update to ensure consistent state */
 670                __speculation_ctrl_update(~tifn, tifn);
 671        }
 672
 673        if ((tifp ^ tifn) & _TIF_SLD)
 674                switch_to_sld(tifn);
 675}
 676
 677/*
 678 * Idle related variables and functions
 679 */
 680unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 681EXPORT_SYMBOL(boot_option_idle_override);
 682
 683static void (*x86_idle)(void);
 684
 685#ifndef CONFIG_SMP
 686static inline void play_dead(void)
 687{
 688        BUG();
 689}
 690#endif
 691
 692void arch_cpu_idle_enter(void)
 693{
 694        tsc_verify_tsc_adjust(false);
 695        local_touch_nmi();
 696}
 697
 698void arch_cpu_idle_dead(void)
 699{
 700        play_dead();
 701}
 702
 703/*
 704 * Called from the generic idle code.
 705 */
 706void arch_cpu_idle(void)
 707{
 708        x86_idle();
 709}
 710
 711/*
 712 * We use this if we don't have any better idle routine..
 713 */
 714void __cpuidle default_idle(void)
 715{
 716        raw_safe_halt();
 717}
 718#if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
 719EXPORT_SYMBOL(default_idle);
 720#endif
 721
 722#ifdef CONFIG_XEN
 723bool xen_set_default_idle(void)
 724{
 725        bool ret = !!x86_idle;
 726
 727        x86_idle = default_idle;
 728
 729        return ret;
 730}
 731#endif
 732
 733void stop_this_cpu(void *dummy)
 734{
 735        local_irq_disable();
 736        /*
 737         * Remove this CPU:
 738         */
 739        set_cpu_online(smp_processor_id(), false);
 740        disable_local_APIC();
 741        mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
 742
 743        /*
 744         * Use wbinvd on processors that support SME. This provides support
 745         * for performing a successful kexec when going from SME inactive
 746         * to SME active (or vice-versa). The cache must be cleared so that
 747         * if there are entries with the same physical address, both with and
 748         * without the encryption bit, they don't race each other when flushed
 749         * and potentially end up with the wrong entry being committed to
 750         * memory.
 751         */
 752        if (boot_cpu_has(X86_FEATURE_SME))
 753                native_wbinvd();
 754        for (;;) {
 755                /*
 756                 * Use native_halt() so that memory contents don't change
 757                 * (stack usage and variables) after possibly issuing the
 758                 * native_wbinvd() above.
 759                 */
 760                native_halt();
 761        }
 762}
 763
 764/*
 765 * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
 766 * states (local apic timer and TSC stop).
 767 *
 768 * XXX this function is completely buggered vs RCU and tracing.
 769 */
 770static void amd_e400_idle(void)
 771{
 772        /*
 773         * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
 774         * gets set after static_cpu_has() places have been converted via
 775         * alternatives.
 776         */
 777        if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 778                default_idle();
 779                return;
 780        }
 781
 782        tick_broadcast_enter();
 783
 784        default_idle();
 785
 786        /*
 787         * The switch back from broadcast mode needs to be called with
 788         * interrupts disabled.
 789         */
 790        raw_local_irq_disable();
 791        tick_broadcast_exit();
 792        raw_local_irq_enable();
 793}
 794
 795/*
 796 * Intel Core2 and older machines prefer MWAIT over HALT for C1.
 797 * We can't rely on cpuidle installing MWAIT, because it will not load
 798 * on systems that support only C1 -- so the boot default must be MWAIT.
 799 *
 800 * Some AMD machines are the opposite, they depend on using HALT.
 801 *
 802 * So for default C1, which is used during boot until cpuidle loads,
 803 * use MWAIT-C1 on Intel HW that has it, else use HALT.
 804 */
 805static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
 806{
 807        if (c->x86_vendor != X86_VENDOR_INTEL)
 808                return 0;
 809
 810        if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
 811                return 0;
 812
 813        return 1;
 814}
 815
 816/*
 817 * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
 818 * with interrupts enabled and no flags, which is backwards compatible with the
 819 * original MWAIT implementation.
 820 */
 821static __cpuidle void mwait_idle(void)
 822{
 823        if (!current_set_polling_and_test()) {
 824                if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
 825                        mb(); /* quirk */
 826                        clflush((void *)&current_thread_info()->flags);
 827                        mb(); /* quirk */
 828                }
 829
 830                __monitor((void *)&current_thread_info()->flags, 0, 0);
 831                if (!need_resched())
 832                        __sti_mwait(0, 0);
 833                else
 834                        raw_local_irq_enable();
 835        } else {
 836                raw_local_irq_enable();
 837        }
 838        __current_clr_polling();
 839}
 840
 841void select_idle_routine(const struct cpuinfo_x86 *c)
 842{
 843#ifdef CONFIG_SMP
 844        if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 845                pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 846#endif
 847        if (x86_idle || boot_option_idle_override == IDLE_POLL)
 848                return;
 849
 850        if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
 851                pr_info("using AMD E400 aware idle routine\n");
 852                x86_idle = amd_e400_idle;
 853        } else if (prefer_mwait_c1_over_halt(c)) {
 854                pr_info("using mwait in idle threads\n");
 855                x86_idle = mwait_idle;
 856        } else
 857                x86_idle = default_idle;
 858}
 859
 860void amd_e400_c1e_apic_setup(void)
 861{
 862        if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
 863                pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
 864                local_irq_disable();
 865                tick_broadcast_force();
 866                local_irq_enable();
 867        }
 868}
 869
 870void __init arch_post_acpi_subsys_init(void)
 871{
 872        u32 lo, hi;
 873
 874        if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
 875                return;
 876
 877        /*
 878         * AMD E400 detection needs to happen after ACPI has been enabled. If
 879         * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
 880         * MSR_K8_INT_PENDING_MSG.
 881         */
 882        rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 883        if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
 884                return;
 885
 886        boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
 887
 888        if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 889                mark_tsc_unstable("TSC halt in AMD C1E");
 890        pr_info("System has AMD C1E enabled\n");
 891}
 892
 893static int __init idle_setup(char *str)
 894{
 895        if (!str)
 896                return -EINVAL;
 897
 898        if (!strcmp(str, "poll")) {
 899                pr_info("using polling idle threads\n");
 900                boot_option_idle_override = IDLE_POLL;
 901                cpu_idle_poll_ctrl(true);
 902        } else if (!strcmp(str, "halt")) {
 903                /*
 904                 * When the boot option of idle=halt is added, halt is
 905                 * forced to be used for CPU idle. In such case CPU C2/C3
 906                 * won't be used again.
 907                 * To continue to load the CPU idle driver, don't touch
 908                 * the boot_option_idle_override.
 909                 */
 910                x86_idle = default_idle;
 911                boot_option_idle_override = IDLE_HALT;
 912        } else if (!strcmp(str, "nomwait")) {
 913                /*
 914                 * If the boot option of "idle=nomwait" is added,
 915                 * it means that mwait will be disabled for CPU C2/C3
 916                 * states. In such case it won't touch the variable
 917                 * of boot_option_idle_override.
 918                 */
 919                boot_option_idle_override = IDLE_NOMWAIT;
 920        } else
 921                return -1;
 922
 923        return 0;
 924}
 925early_param("idle", idle_setup);
 926
 927unsigned long arch_align_stack(unsigned long sp)
 928{
 929        if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 930                sp -= get_random_int() % 8192;
 931        return sp & ~0xf;
 932}
 933
 934unsigned long arch_randomize_brk(struct mm_struct *mm)
 935{
 936        return randomize_page(mm->brk, 0x02000000);
 937}
 938
 939/*
 940 * Called from fs/proc with a reference on @p to find the function
 941 * which called into schedule(). This needs to be done carefully
 942 * because the task might wake up and we might look at a stack
 943 * changing under us.
 944 */
 945unsigned long get_wchan(struct task_struct *p)
 946{
 947        unsigned long start, bottom, top, sp, fp, ip, ret = 0;
 948        int count = 0;
 949
 950        if (p == current || task_is_running(p))
 951                return 0;
 952
 953        if (!try_get_task_stack(p))
 954                return 0;
 955
 956        start = (unsigned long)task_stack_page(p);
 957        if (!start)
 958                goto out;
 959
 960        /*
 961         * Layout of the stack page:
 962         *
 963         * ----------- topmax = start + THREAD_SIZE - sizeof(unsigned long)
 964         * PADDING
 965         * ----------- top = topmax - TOP_OF_KERNEL_STACK_PADDING
 966         * stack
 967         * ----------- bottom = start
 968         *
 969         * The tasks stack pointer points at the location where the
 970         * framepointer is stored. The data on the stack is:
 971         * ... IP FP ... IP FP
 972         *
 973         * We need to read FP and IP, so we need to adjust the upper
 974         * bound by another unsigned long.
 975         */
 976        top = start + THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;
 977        top -= 2 * sizeof(unsigned long);
 978        bottom = start;
 979
 980        sp = READ_ONCE(p->thread.sp);
 981        if (sp < bottom || sp > top)
 982                goto out;
 983
 984        fp = READ_ONCE_NOCHECK(((struct inactive_task_frame *)sp)->bp);
 985        do {
 986                if (fp < bottom || fp > top)
 987                        goto out;
 988                ip = READ_ONCE_NOCHECK(*(unsigned long *)(fp + sizeof(unsigned long)));
 989                if (!in_sched_functions(ip)) {
 990                        ret = ip;
 991                        goto out;
 992                }
 993                fp = READ_ONCE_NOCHECK(*(unsigned long *)fp);
 994        } while (count++ < 16 && !task_is_running(p));
 995
 996out:
 997        put_task_stack(p);
 998        return ret;
 999}
1000
1001long do_arch_prctl_common(struct task_struct *task, int option,
1002                          unsigned long cpuid_enabled)
1003{
1004        switch (option) {
1005        case ARCH_GET_CPUID:
1006                return get_cpuid_mode();
1007        case ARCH_SET_CPUID:
1008                return set_cpuid_mode(task, cpuid_enabled);
1009        }
1010
1011        return -EINVAL;
1012}
1013