linux/arch/powerpc/platforms/83xx/mpc836x_mds.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
   4 *
   5 * Author: Li Yang <LeoLi@freescale.com>
   6 *         Yin Olivia <Hong-hua.Yin@freescale.com>
   7 *
   8 * Description:
   9 * MPC8360E MDS board specific routines.
  10 *
  11 * Changelog:
  12 * Jun 21, 2006 Initial version
  13 */
  14
  15#include <linux/stddef.h>
  16#include <linux/kernel.h>
  17#include <linux/compiler.h>
  18#include <linux/init.h>
  19#include <linux/errno.h>
  20#include <linux/reboot.h>
  21#include <linux/pci.h>
  22#include <linux/kdev_t.h>
  23#include <linux/major.h>
  24#include <linux/console.h>
  25#include <linux/delay.h>
  26#include <linux/seq_file.h>
  27#include <linux/root_dev.h>
  28#include <linux/initrd.h>
  29#include <linux/of_platform.h>
  30#include <linux/of_device.h>
  31
  32#include <linux/atomic.h>
  33#include <asm/time.h>
  34#include <asm/io.h>
  35#include <asm/machdep.h>
  36#include <asm/ipic.h>
  37#include <asm/irq.h>
  38#include <asm/prom.h>
  39#include <asm/udbg.h>
  40#include <sysdev/fsl_soc.h>
  41#include <sysdev/fsl_pci.h>
  42#include <soc/fsl/qe/qe.h>
  43
  44#include "mpc83xx.h"
  45
  46#undef DEBUG
  47#ifdef DEBUG
  48#define DBG(fmt...) udbg_printf(fmt)
  49#else
  50#define DBG(fmt...)
  51#endif
  52
  53/* ************************************************************************
  54 *
  55 * Setup the architecture
  56 *
  57 */
  58static void __init mpc836x_mds_setup_arch(void)
  59{
  60        struct device_node *np;
  61        u8 __iomem *bcsr_regs = NULL;
  62
  63        mpc83xx_setup_arch();
  64
  65        /* Map BCSR area */
  66        np = of_find_node_by_name(NULL, "bcsr");
  67        if (np) {
  68                struct resource res;
  69
  70                of_address_to_resource(np, 0, &res);
  71                bcsr_regs = ioremap(res.start, resource_size(&res));
  72                of_node_put(np);
  73        }
  74
  75#ifdef CONFIG_QUICC_ENGINE
  76        if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
  77                par_io_init(np);
  78                of_node_put(np);
  79
  80                for_each_node_by_name(np, "ucc")
  81                        par_io_of_config(np);
  82#ifdef CONFIG_QE_USB
  83                /* Must fixup Par IO before QE GPIO chips are registered. */
  84                par_io_config_pin(1,  2, 1, 0, 3, 0); /* USBOE  */
  85                par_io_config_pin(1,  3, 1, 0, 3, 0); /* USBTP  */
  86                par_io_config_pin(1,  8, 1, 0, 1, 0); /* USBTN  */
  87                par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
  88                par_io_config_pin(1,  9, 2, 1, 3, 0); /* USBRP  */
  89                par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN  */
  90                par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21  */
  91#endif /* CONFIG_QE_USB */
  92        }
  93
  94        if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
  95                        != NULL){
  96                uint svid;
  97
  98                /* Reset the Ethernet PHY */
  99#define BCSR9_GETHRST 0x20
 100                clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
 101                udelay(1000);
 102                setbits8(&bcsr_regs[9], BCSR9_GETHRST);
 103
 104                /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
 105                svid = mfspr(SPRN_SVR);
 106                if (svid == 0x80480021) {
 107                        void __iomem *immap;
 108
 109                        immap = ioremap(get_immrbase() + 0x14a8, 8);
 110
 111                        /*
 112                         * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
 113                         * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
 114                         */
 115                        setbits32(immap, 0x0c003000);
 116
 117                        /*
 118                         * IMMR + 0x14AC[20:27] = 10101010
 119                         * (data delay for both UCC's)
 120                         */
 121                        clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
 122
 123                        iounmap(immap);
 124                }
 125
 126                iounmap(bcsr_regs);
 127                of_node_put(np);
 128        }
 129#endif                          /* CONFIG_QUICC_ENGINE */
 130}
 131
 132machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
 133
 134#ifdef CONFIG_QE_USB
 135static int __init mpc836x_usb_cfg(void)
 136{
 137        u8 __iomem *bcsr;
 138        struct device_node *np;
 139        const char *mode;
 140        int ret = 0;
 141
 142        np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
 143        if (!np)
 144                return -ENODEV;
 145
 146        bcsr = of_iomap(np, 0);
 147        of_node_put(np);
 148        if (!bcsr)
 149                return -ENOMEM;
 150
 151        np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
 152        if (!np) {
 153                ret = -ENODEV;
 154                goto err;
 155        }
 156
 157#define BCSR8_TSEC1M_MASK       (0x3 << 6)
 158#define BCSR8_TSEC1M_RGMII      (0x0 << 6)
 159#define BCSR8_TSEC2M_MASK       (0x3 << 4)
 160#define BCSR8_TSEC2M_RGMII      (0x0 << 4)
 161        /*
 162         * Default is GMII (2), but we should set it to RGMII (0) if we use
 163         * USB (Eth PHY is in RGMII mode anyway).
 164         */
 165        clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
 166                               BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
 167
 168#define BCSR13_USBMASK  0x0f
 169#define BCSR13_nUSBEN   0x08 /* 1 - Disable, 0 - Enable                 */
 170#define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low                       */
 171#define BCSR13_USBMODE  0x02 /* 1 - Host, 0 - Function                  */
 172#define BCSR13_nUSBVCC  0x01 /* 1 - gets VBUS, 0 - supplies VBUS        */
 173
 174        clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
 175
 176        mode = of_get_property(np, "mode", NULL);
 177        if (mode && !strcmp(mode, "peripheral")) {
 178                setbits8(&bcsr[13], BCSR13_nUSBVCC);
 179                qe_usb_clock_set(QE_CLK21, 48000000);
 180        } else {
 181                setbits8(&bcsr[13], BCSR13_USBMODE);
 182        }
 183
 184        of_node_put(np);
 185err:
 186        iounmap(bcsr);
 187        return ret;
 188}
 189machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
 190#endif /* CONFIG_QE_USB */
 191
 192/*
 193 * Called very early, MMU is off, device-tree isn't unflattened
 194 */
 195static int __init mpc836x_mds_probe(void)
 196{
 197        return of_machine_is_compatible("MPC836xMDS");
 198}
 199
 200define_machine(mpc836x_mds) {
 201        .name           = "MPC836x MDS",
 202        .probe          = mpc836x_mds_probe,
 203        .setup_arch     = mpc836x_mds_setup_arch,
 204        .discover_phbs  = mpc83xx_setup_pci,
 205        .init_IRQ       = mpc83xx_ipic_init_IRQ,
 206        .get_irq        = ipic_get_irq,
 207        .restart        = mpc83xx_restart,
 208        .time_init      = mpc83xx_time_init,
 209        .calibrate_decr = generic_calibrate_decr,
 210        .progress       = udbg_progress,
 211};
 212