1
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7
8
9#include <linux/perf_event.h>
10#include <linux/slab.h>
11#include <asm/opal.h>
12#include <asm/imc-pmu.h>
13#include <asm/cputhreads.h>
14#include <asm/smp.h>
15#include <linux/string.h>
16
17
18
19
20
21
22
23static DEFINE_MUTEX(nest_init_lock);
24static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
25static struct imc_pmu **per_nest_pmu_arr;
26static cpumask_t nest_imc_cpumask;
27static struct imc_pmu_ref *nest_imc_refc;
28static int nest_pmus;
29
30
31
32static cpumask_t core_imc_cpumask;
33static struct imc_pmu_ref *core_imc_refc;
34static struct imc_pmu *core_imc_pmu;
35
36
37
38static DEFINE_PER_CPU(u64 *, thread_imc_mem);
39static struct imc_pmu *thread_imc_pmu;
40static int thread_imc_mem_size;
41
42
43static DEFINE_PER_CPU(u64 *, trace_imc_mem);
44static struct imc_pmu_ref *trace_imc_refc;
45static int trace_imc_mem_size;
46
47
48
49
50
51static struct imc_pmu_ref imc_global_refc = {
52 .lock = __MUTEX_INITIALIZER(imc_global_refc.lock),
53 .id = 0,
54 .refc = 0,
55};
56
57static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
58{
59 return container_of(event->pmu, struct imc_pmu, pmu);
60}
61
62PMU_FORMAT_ATTR(event, "config:0-61");
63PMU_FORMAT_ATTR(offset, "config:0-31");
64PMU_FORMAT_ATTR(rvalue, "config:32");
65PMU_FORMAT_ATTR(mode, "config:33-40");
66static struct attribute *imc_format_attrs[] = {
67 &format_attr_event.attr,
68 &format_attr_offset.attr,
69 &format_attr_rvalue.attr,
70 &format_attr_mode.attr,
71 NULL,
72};
73
74static struct attribute_group imc_format_group = {
75 .name = "format",
76 .attrs = imc_format_attrs,
77};
78
79
80PMU_FORMAT_ATTR(cpmc_reserved, "config:0-19");
81PMU_FORMAT_ATTR(cpmc_event, "config:20-27");
82PMU_FORMAT_ATTR(cpmc_samplesel, "config:28-29");
83PMU_FORMAT_ATTR(cpmc_load, "config:30-61");
84static struct attribute *trace_imc_format_attrs[] = {
85 &format_attr_event.attr,
86 &format_attr_cpmc_reserved.attr,
87 &format_attr_cpmc_event.attr,
88 &format_attr_cpmc_samplesel.attr,
89 &format_attr_cpmc_load.attr,
90 NULL,
91};
92
93static struct attribute_group trace_imc_format_group = {
94.name = "format",
95.attrs = trace_imc_format_attrs,
96};
97
98
99static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
100 struct device_attribute *attr,
101 char *buf)
102{
103 struct pmu *pmu = dev_get_drvdata(dev);
104 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
105 cpumask_t *active_mask;
106
107 switch(imc_pmu->domain){
108 case IMC_DOMAIN_NEST:
109 active_mask = &nest_imc_cpumask;
110 break;
111 case IMC_DOMAIN_CORE:
112 active_mask = &core_imc_cpumask;
113 break;
114 default:
115 return 0;
116 }
117
118 return cpumap_print_to_pagebuf(true, buf, active_mask);
119}
120
121static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
122
123static struct attribute *imc_pmu_cpumask_attrs[] = {
124 &dev_attr_cpumask.attr,
125 NULL,
126};
127
128static struct attribute_group imc_pmu_cpumask_attr_group = {
129 .attrs = imc_pmu_cpumask_attrs,
130};
131
132
133static struct attribute *device_str_attr_create(const char *name, const char *str)
134{
135 struct perf_pmu_events_attr *attr;
136
137 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
138 if (!attr)
139 return NULL;
140 sysfs_attr_init(&attr->attr.attr);
141
142 attr->event_str = str;
143 attr->attr.attr.name = name;
144 attr->attr.attr.mode = 0444;
145 attr->attr.show = perf_event_sysfs_show;
146
147 return &attr->attr.attr;
148}
149
150static int imc_parse_event(struct device_node *np, const char *scale,
151 const char *unit, const char *prefix,
152 u32 base, struct imc_events *event)
153{
154 const char *s;
155 u32 reg;
156
157 if (of_property_read_u32(np, "reg", ®))
158 goto error;
159
160 event->value = base + reg;
161
162 if (of_property_read_string(np, "event-name", &s))
163 goto error;
164
165 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
166 if (!event->name)
167 goto error;
168
169 if (of_property_read_string(np, "scale", &s))
170 s = scale;
171
172 if (s) {
173 event->scale = kstrdup(s, GFP_KERNEL);
174 if (!event->scale)
175 goto error;
176 }
177
178 if (of_property_read_string(np, "unit", &s))
179 s = unit;
180
181 if (s) {
182 event->unit = kstrdup(s, GFP_KERNEL);
183 if (!event->unit)
184 goto error;
185 }
186
187 return 0;
188error:
189 kfree(event->unit);
190 kfree(event->scale);
191 kfree(event->name);
192 return -EINVAL;
193}
194
195
196
197
198
199static void imc_free_events(struct imc_events *events, int nr_entries)
200{
201 int i;
202
203
204 if (!events)
205 return;
206 for (i = 0; i < nr_entries; i++) {
207 kfree(events[i].unit);
208 kfree(events[i].scale);
209 kfree(events[i].name);
210 }
211
212 kfree(events);
213}
214
215
216
217
218
219static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
220{
221 struct attribute_group *attr_group;
222 struct attribute **attrs, *dev_str;
223 struct device_node *np, *pmu_events;
224 u32 handle, base_reg;
225 int i = 0, j = 0, ct, ret;
226 const char *prefix, *g_scale, *g_unit;
227 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
228
229 if (!of_property_read_u32(node, "events", &handle))
230 pmu_events = of_find_node_by_phandle(handle);
231 else
232 return 0;
233
234
235 if (!pmu_events)
236 return 0;
237
238
239 ct = of_get_child_count(pmu_events);
240
241
242 if (of_property_read_string(node, "events-prefix", &prefix))
243 return 0;
244
245
246 if (of_property_read_string(node, "scale", &g_scale))
247 g_scale = NULL;
248
249 if (of_property_read_string(node, "unit", &g_unit))
250 g_unit = NULL;
251
252
253 of_property_read_u32(node, "reg", &base_reg);
254
255
256 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
257 if (!pmu->events)
258 return -ENOMEM;
259
260 ct = 0;
261
262 for_each_child_of_node(pmu_events, np) {
263 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
264 if (!ret)
265 ct++;
266 }
267
268
269 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
270 if (!attr_group) {
271 imc_free_events(pmu->events, ct);
272 return -ENOMEM;
273 }
274
275
276
277
278
279
280
281
282
283 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
284 if (!attrs) {
285 kfree(attr_group);
286 imc_free_events(pmu->events, ct);
287 return -ENOMEM;
288 }
289
290 attr_group->name = "events";
291 attr_group->attrs = attrs;
292 do {
293 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
294 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
295 if (!dev_str)
296 continue;
297
298 attrs[j++] = dev_str;
299 if (pmu->events[i].scale) {
300 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
301 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
302 if (!dev_str)
303 continue;
304
305 attrs[j++] = dev_str;
306 }
307
308 if (pmu->events[i].unit) {
309 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
310 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
311 if (!dev_str)
312 continue;
313
314 attrs[j++] = dev_str;
315 }
316 } while (++i < ct);
317
318
319 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
320
321 return 0;
322}
323
324
325static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
326{
327 return per_cpu(local_nest_imc_refc, cpu);
328}
329
330static void nest_change_cpu_context(int old_cpu, int new_cpu)
331{
332 struct imc_pmu **pn = per_nest_pmu_arr;
333
334 if (old_cpu < 0 || new_cpu < 0)
335 return;
336
337 while (*pn) {
338 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
339 pn++;
340 }
341}
342
343static int ppc_nest_imc_cpu_offline(unsigned int cpu)
344{
345 int nid, target = -1;
346 const struct cpumask *l_cpumask;
347 struct imc_pmu_ref *ref;
348
349
350
351
352
353 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
354 return 0;
355
356
357
358
359
360
361
362
363
364
365
366 if (!nest_pmus)
367 return 0;
368
369
370
371
372
373 nid = cpu_to_node(cpu);
374 l_cpumask = cpumask_of_node(nid);
375 target = cpumask_last(l_cpumask);
376
377
378
379
380
381 if (unlikely(target == cpu))
382 target = cpumask_any_but(l_cpumask, cpu);
383
384
385
386
387
388 if (target >= 0 && target < nr_cpu_ids) {
389 cpumask_set_cpu(target, &nest_imc_cpumask);
390 nest_change_cpu_context(cpu, target);
391 } else {
392 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
393 get_hard_smp_processor_id(cpu));
394
395
396
397
398 ref = get_nest_pmu_ref(cpu);
399 if (!ref)
400 return -EINVAL;
401
402 ref->refc = 0;
403 }
404 return 0;
405}
406
407static int ppc_nest_imc_cpu_online(unsigned int cpu)
408{
409 const struct cpumask *l_cpumask;
410 static struct cpumask tmp_mask;
411 int res;
412
413
414 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
415
416
417
418
419
420 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
421 return 0;
422
423
424
425
426
427 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
428 get_hard_smp_processor_id(cpu));
429 if (res)
430 return res;
431
432
433 cpumask_set_cpu(cpu, &nest_imc_cpumask);
434 return 0;
435}
436
437static int nest_pmu_cpumask_init(void)
438{
439 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
440 "perf/powerpc/imc:online",
441 ppc_nest_imc_cpu_online,
442 ppc_nest_imc_cpu_offline);
443}
444
445static void nest_imc_counters_release(struct perf_event *event)
446{
447 int rc, node_id;
448 struct imc_pmu_ref *ref;
449
450 if (event->cpu < 0)
451 return;
452
453 node_id = cpu_to_node(event->cpu);
454
455
456
457
458
459
460
461 ref = get_nest_pmu_ref(event->cpu);
462 if (!ref)
463 return;
464
465
466 mutex_lock(&ref->lock);
467 if (ref->refc == 0) {
468
469
470
471
472
473
474
475
476
477
478 mutex_unlock(&ref->lock);
479 return;
480 }
481 ref->refc--;
482 if (ref->refc == 0) {
483 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
484 get_hard_smp_processor_id(event->cpu));
485 if (rc) {
486 mutex_unlock(&ref->lock);
487 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
488 return;
489 }
490 } else if (ref->refc < 0) {
491 WARN(1, "nest-imc: Invalid event reference count\n");
492 ref->refc = 0;
493 }
494 mutex_unlock(&ref->lock);
495}
496
497static int nest_imc_event_init(struct perf_event *event)
498{
499 int chip_id, rc, node_id;
500 u32 l_config, config = event->attr.config;
501 struct imc_mem_info *pcni;
502 struct imc_pmu *pmu;
503 struct imc_pmu_ref *ref;
504 bool flag = false;
505
506 if (event->attr.type != event->pmu->type)
507 return -ENOENT;
508
509
510 if (event->hw.sample_period)
511 return -EINVAL;
512
513 if (event->cpu < 0)
514 return -EINVAL;
515
516 pmu = imc_event_to_pmu(event);
517
518
519 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
520 return -EINVAL;
521
522
523
524
525
526 chip_id = cpu_to_chip_id(event->cpu);
527
528
529 if (chip_id < 0)
530 return -ENODEV;
531
532 pcni = pmu->mem_info;
533 do {
534 if (pcni->id == chip_id) {
535 flag = true;
536 break;
537 }
538 pcni++;
539 } while (pcni->vbase != 0);
540
541 if (!flag)
542 return -ENODEV;
543
544
545
546
547 l_config = config & IMC_EVENT_OFFSET_MASK;
548 event->hw.event_base = (u64)pcni->vbase + l_config;
549 node_id = cpu_to_node(event->cpu);
550
551
552
553
554
555
556 ref = get_nest_pmu_ref(event->cpu);
557 if (!ref)
558 return -EINVAL;
559
560 mutex_lock(&ref->lock);
561 if (ref->refc == 0) {
562 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
563 get_hard_smp_processor_id(event->cpu));
564 if (rc) {
565 mutex_unlock(&ref->lock);
566 pr_err("nest-imc: Unable to start the counters for node %d\n",
567 node_id);
568 return rc;
569 }
570 }
571 ++ref->refc;
572 mutex_unlock(&ref->lock);
573
574 event->destroy = nest_imc_counters_release;
575 return 0;
576}
577
578
579
580
581
582
583
584
585
586static int core_imc_mem_init(int cpu, int size)
587{
588 int nid, rc = 0, core_id = (cpu / threads_per_core);
589 struct imc_mem_info *mem_info;
590 struct page *page;
591
592
593
594
595
596 nid = cpu_to_node(cpu);
597 mem_info = &core_imc_pmu->mem_info[core_id];
598 mem_info->id = core_id;
599
600
601 page = alloc_pages_node(nid,
602 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
603 __GFP_NOWARN, get_order(size));
604 if (!page)
605 return -ENOMEM;
606 mem_info->vbase = page_address(page);
607
608
609 core_imc_refc[core_id].id = core_id;
610 mutex_init(&core_imc_refc[core_id].lock);
611
612 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
613 __pa((void *)mem_info->vbase),
614 get_hard_smp_processor_id(cpu));
615 if (rc) {
616 free_pages((u64)mem_info->vbase, get_order(size));
617 mem_info->vbase = NULL;
618 }
619
620 return rc;
621}
622
623static bool is_core_imc_mem_inited(int cpu)
624{
625 struct imc_mem_info *mem_info;
626 int core_id = (cpu / threads_per_core);
627
628 mem_info = &core_imc_pmu->mem_info[core_id];
629 if (!mem_info->vbase)
630 return false;
631
632 return true;
633}
634
635static int ppc_core_imc_cpu_online(unsigned int cpu)
636{
637 const struct cpumask *l_cpumask;
638 static struct cpumask tmp_mask;
639 int ret = 0;
640
641
642 l_cpumask = cpu_sibling_mask(cpu);
643
644
645 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
646 return 0;
647
648 if (!is_core_imc_mem_inited(cpu)) {
649 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
650 if (ret) {
651 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
652 return ret;
653 }
654 }
655
656
657 cpumask_set_cpu(cpu, &core_imc_cpumask);
658 return 0;
659}
660
661static int ppc_core_imc_cpu_offline(unsigned int cpu)
662{
663 unsigned int core_id;
664 int ncpu;
665 struct imc_pmu_ref *ref;
666
667
668
669
670
671 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
672 return 0;
673
674
675
676
677
678
679
680
681
682
683
684
685 if (!core_imc_pmu->pmu.event_init)
686 return 0;
687
688
689 ncpu = cpumask_last(cpu_sibling_mask(cpu));
690
691 if (unlikely(ncpu == cpu))
692 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
693
694 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
695 cpumask_set_cpu(ncpu, &core_imc_cpumask);
696 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
697 } else {
698
699
700
701
702
703 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
704 get_hard_smp_processor_id(cpu));
705 core_id = cpu / threads_per_core;
706 ref = &core_imc_refc[core_id];
707 if (!ref)
708 return -EINVAL;
709
710 ref->refc = 0;
711
712
713
714
715
716 mutex_lock(&imc_global_refc.lock);
717 if (imc_global_refc.id == IMC_DOMAIN_CORE)
718 imc_global_refc.refc--;
719
720 mutex_unlock(&imc_global_refc.lock);
721 }
722 return 0;
723}
724
725static int core_imc_pmu_cpumask_init(void)
726{
727 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
728 "perf/powerpc/imc_core:online",
729 ppc_core_imc_cpu_online,
730 ppc_core_imc_cpu_offline);
731}
732
733static void reset_global_refc(struct perf_event *event)
734{
735 mutex_lock(&imc_global_refc.lock);
736 imc_global_refc.refc--;
737
738
739
740
741
742
743 if (imc_global_refc.refc <= 0) {
744 imc_global_refc.refc = 0;
745 imc_global_refc.id = 0;
746 }
747 mutex_unlock(&imc_global_refc.lock);
748}
749
750static void core_imc_counters_release(struct perf_event *event)
751{
752 int rc, core_id;
753 struct imc_pmu_ref *ref;
754
755 if (event->cpu < 0)
756 return;
757
758
759
760
761
762
763 core_id = event->cpu / threads_per_core;
764
765
766 ref = &core_imc_refc[core_id];
767 if (!ref)
768 return;
769
770 mutex_lock(&ref->lock);
771 if (ref->refc == 0) {
772
773
774
775
776
777
778
779
780
781
782 mutex_unlock(&ref->lock);
783 return;
784 }
785 ref->refc--;
786 if (ref->refc == 0) {
787 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
788 get_hard_smp_processor_id(event->cpu));
789 if (rc) {
790 mutex_unlock(&ref->lock);
791 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
792 return;
793 }
794 } else if (ref->refc < 0) {
795 WARN(1, "core-imc: Invalid event reference count\n");
796 ref->refc = 0;
797 }
798 mutex_unlock(&ref->lock);
799
800 reset_global_refc(event);
801}
802
803static int core_imc_event_init(struct perf_event *event)
804{
805 int core_id, rc;
806 u64 config = event->attr.config;
807 struct imc_mem_info *pcmi;
808 struct imc_pmu *pmu;
809 struct imc_pmu_ref *ref;
810
811 if (event->attr.type != event->pmu->type)
812 return -ENOENT;
813
814
815 if (event->hw.sample_period)
816 return -EINVAL;
817
818 if (event->cpu < 0)
819 return -EINVAL;
820
821 event->hw.idx = -1;
822 pmu = imc_event_to_pmu(event);
823
824
825 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
826 return -EINVAL;
827
828 if (!is_core_imc_mem_inited(event->cpu))
829 return -ENODEV;
830
831 core_id = event->cpu / threads_per_core;
832 pcmi = &core_imc_pmu->mem_info[core_id];
833 if ((!pcmi->vbase))
834 return -ENODEV;
835
836
837 ref = &core_imc_refc[core_id];
838 if (!ref)
839 return -EINVAL;
840
841
842
843
844
845
846
847 mutex_lock(&ref->lock);
848 if (ref->refc == 0) {
849 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
850 get_hard_smp_processor_id(event->cpu));
851 if (rc) {
852 mutex_unlock(&ref->lock);
853 pr_err("core-imc: Unable to start the counters for core %d\n",
854 core_id);
855 return rc;
856 }
857 }
858 ++ref->refc;
859 mutex_unlock(&ref->lock);
860
861
862
863
864
865
866
867
868
869
870 mutex_lock(&imc_global_refc.lock);
871 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_CORE) {
872
873
874
875
876 imc_global_refc.id = IMC_DOMAIN_CORE;
877 imc_global_refc.refc++;
878 } else {
879 mutex_unlock(&imc_global_refc.lock);
880 return -EBUSY;
881 }
882 mutex_unlock(&imc_global_refc.lock);
883
884 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
885 event->destroy = core_imc_counters_release;
886 return 0;
887}
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910static int thread_imc_mem_alloc(int cpu_id, int size)
911{
912 u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
913 int nid = cpu_to_node(cpu_id);
914
915 if (!local_mem) {
916 struct page *page;
917
918
919
920
921 page = alloc_pages_node(nid,
922 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
923 __GFP_NOWARN, get_order(size));
924 if (!page)
925 return -ENOMEM;
926 local_mem = page_address(page);
927
928 per_cpu(thread_imc_mem, cpu_id) = local_mem;
929 }
930
931 mtspr(SPRN_LDBAR, 0);
932 return 0;
933}
934
935static int ppc_thread_imc_cpu_online(unsigned int cpu)
936{
937 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
938}
939
940static int ppc_thread_imc_cpu_offline(unsigned int cpu)
941{
942
943
944
945
946
947
948
949
950
951 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
952
953
954 mutex_lock(&imc_global_refc.lock);
955 if (imc_global_refc.id == IMC_DOMAIN_THREAD)
956 imc_global_refc.refc--;
957 mutex_unlock(&imc_global_refc.lock);
958
959 return 0;
960}
961
962static int thread_imc_cpu_init(void)
963{
964 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
965 "perf/powerpc/imc_thread:online",
966 ppc_thread_imc_cpu_online,
967 ppc_thread_imc_cpu_offline);
968}
969
970static int thread_imc_event_init(struct perf_event *event)
971{
972 u32 config = event->attr.config;
973 struct task_struct *target;
974 struct imc_pmu *pmu;
975
976 if (event->attr.type != event->pmu->type)
977 return -ENOENT;
978
979 if (!perfmon_capable())
980 return -EACCES;
981
982
983 if (event->hw.sample_period)
984 return -EINVAL;
985
986 event->hw.idx = -1;
987 pmu = imc_event_to_pmu(event);
988
989
990 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
991 return -EINVAL;
992
993 target = event->hw.target;
994 if (!target)
995 return -EINVAL;
996
997 mutex_lock(&imc_global_refc.lock);
998
999
1000
1001
1002 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_THREAD) {
1003 imc_global_refc.id = IMC_DOMAIN_THREAD;
1004 imc_global_refc.refc++;
1005 } else {
1006 mutex_unlock(&imc_global_refc.lock);
1007 return -EBUSY;
1008 }
1009 mutex_unlock(&imc_global_refc.lock);
1010
1011 event->pmu->task_ctx_nr = perf_sw_context;
1012 event->destroy = reset_global_refc;
1013 return 0;
1014}
1015
1016static bool is_thread_imc_pmu(struct perf_event *event)
1017{
1018 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
1019 return true;
1020
1021 return false;
1022}
1023
1024static u64 * get_event_base_addr(struct perf_event *event)
1025{
1026 u64 addr;
1027
1028 if (is_thread_imc_pmu(event)) {
1029 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
1030 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
1031 }
1032
1033 return (u64 *)event->hw.event_base;
1034}
1035
1036static void thread_imc_pmu_start_txn(struct pmu *pmu,
1037 unsigned int txn_flags)
1038{
1039 if (txn_flags & ~PERF_PMU_TXN_ADD)
1040 return;
1041 perf_pmu_disable(pmu);
1042}
1043
1044static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
1045{
1046 perf_pmu_enable(pmu);
1047}
1048
1049static int thread_imc_pmu_commit_txn(struct pmu *pmu)
1050{
1051 perf_pmu_enable(pmu);
1052 return 0;
1053}
1054
1055static u64 imc_read_counter(struct perf_event *event)
1056{
1057 u64 *addr, data;
1058
1059
1060
1061
1062
1063
1064
1065 addr = get_event_base_addr(event);
1066 data = be64_to_cpu(READ_ONCE(*addr));
1067 local64_set(&event->hw.prev_count, data);
1068
1069 return data;
1070}
1071
1072static void imc_event_update(struct perf_event *event)
1073{
1074 u64 counter_prev, counter_new, final_count;
1075
1076 counter_prev = local64_read(&event->hw.prev_count);
1077 counter_new = imc_read_counter(event);
1078 final_count = counter_new - counter_prev;
1079
1080
1081 local64_add(final_count, &event->count);
1082}
1083
1084static void imc_event_start(struct perf_event *event, int flags)
1085{
1086
1087
1088
1089
1090
1091
1092 imc_read_counter(event);
1093}
1094
1095static void imc_event_stop(struct perf_event *event, int flags)
1096{
1097
1098
1099
1100
1101 imc_event_update(event);
1102}
1103
1104static int imc_event_add(struct perf_event *event, int flags)
1105{
1106 if (flags & PERF_EF_START)
1107 imc_event_start(event, flags);
1108
1109 return 0;
1110}
1111
1112static int thread_imc_event_add(struct perf_event *event, int flags)
1113{
1114 int core_id;
1115 struct imc_pmu_ref *ref;
1116 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
1117
1118 if (flags & PERF_EF_START)
1119 imc_event_start(event, flags);
1120
1121 if (!is_core_imc_mem_inited(smp_processor_id()))
1122 return -EINVAL;
1123
1124 core_id = smp_processor_id() / threads_per_core;
1125 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
1126 mtspr(SPRN_LDBAR, ldbar_value);
1127
1128
1129
1130
1131
1132
1133
1134 ref = &core_imc_refc[core_id];
1135 if (!ref)
1136 return -EINVAL;
1137
1138 mutex_lock(&ref->lock);
1139 if (ref->refc == 0) {
1140 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1141 get_hard_smp_processor_id(smp_processor_id()))) {
1142 mutex_unlock(&ref->lock);
1143 pr_err("thread-imc: Unable to start the counter\
1144 for core %d\n", core_id);
1145 return -EINVAL;
1146 }
1147 }
1148 ++ref->refc;
1149 mutex_unlock(&ref->lock);
1150 return 0;
1151}
1152
1153static void thread_imc_event_del(struct perf_event *event, int flags)
1154{
1155
1156 int core_id;
1157 struct imc_pmu_ref *ref;
1158
1159 core_id = smp_processor_id() / threads_per_core;
1160 ref = &core_imc_refc[core_id];
1161 if (!ref) {
1162 pr_debug("imc: Failed to get event reference count\n");
1163 return;
1164 }
1165
1166 mutex_lock(&ref->lock);
1167 ref->refc--;
1168 if (ref->refc == 0) {
1169 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1170 get_hard_smp_processor_id(smp_processor_id()))) {
1171 mutex_unlock(&ref->lock);
1172 pr_err("thread-imc: Unable to stop the counters\
1173 for core %d\n", core_id);
1174 return;
1175 }
1176 } else if (ref->refc < 0) {
1177 ref->refc = 0;
1178 }
1179 mutex_unlock(&ref->lock);
1180
1181
1182 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1183
1184
1185
1186
1187
1188 imc_event_update(event);
1189}
1190
1191
1192
1193
1194static int trace_imc_mem_alloc(int cpu_id, int size)
1195{
1196 u64 *local_mem = per_cpu(trace_imc_mem, cpu_id);
1197 int phys_id = cpu_to_node(cpu_id), rc = 0;
1198 int core_id = (cpu_id / threads_per_core);
1199
1200 if (!local_mem) {
1201 struct page *page;
1202
1203 page = alloc_pages_node(phys_id,
1204 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
1205 __GFP_NOWARN, get_order(size));
1206 if (!page)
1207 return -ENOMEM;
1208 local_mem = page_address(page);
1209 per_cpu(trace_imc_mem, cpu_id) = local_mem;
1210
1211
1212 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_TRACE, __pa((void *)local_mem),
1213 get_hard_smp_processor_id(cpu_id));
1214 if (rc) {
1215 pr_info("IMC:opal init failed for trace imc\n");
1216 return rc;
1217 }
1218 }
1219
1220
1221 trace_imc_refc[core_id].id = core_id;
1222 mutex_init(&trace_imc_refc[core_id].lock);
1223
1224 mtspr(SPRN_LDBAR, 0);
1225 return 0;
1226}
1227
1228static int ppc_trace_imc_cpu_online(unsigned int cpu)
1229{
1230 return trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1231}
1232
1233static int ppc_trace_imc_cpu_offline(unsigned int cpu)
1234{
1235
1236
1237
1238
1239
1240
1241
1242 mutex_lock(&imc_global_refc.lock);
1243 if (imc_global_refc.id == IMC_DOMAIN_TRACE)
1244 imc_global_refc.refc--;
1245 mutex_unlock(&imc_global_refc.lock);
1246
1247 return 0;
1248}
1249
1250static int trace_imc_cpu_init(void)
1251{
1252 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
1253 "perf/powerpc/imc_trace:online",
1254 ppc_trace_imc_cpu_online,
1255 ppc_trace_imc_cpu_offline);
1256}
1257
1258static u64 get_trace_imc_event_base_addr(void)
1259{
1260 return (u64)per_cpu(trace_imc_mem, smp_processor_id());
1261}
1262
1263
1264
1265
1266
1267static int trace_imc_prepare_sample(struct trace_imc_data *mem,
1268 struct perf_sample_data *data,
1269 u64 *prev_tb,
1270 struct perf_event_header *header,
1271 struct perf_event *event)
1272{
1273
1274 if (be64_to_cpu(READ_ONCE(mem->tb1)) > *prev_tb)
1275 *prev_tb = be64_to_cpu(READ_ONCE(mem->tb1));
1276 else
1277 return -EINVAL;
1278
1279 if ((be64_to_cpu(READ_ONCE(mem->tb1)) & IMC_TRACE_RECORD_TB1_MASK) !=
1280 be64_to_cpu(READ_ONCE(mem->tb2)))
1281 return -EINVAL;
1282
1283
1284 data->ip = be64_to_cpu(READ_ONCE(mem->ip));
1285 data->period = event->hw.last_period;
1286
1287 header->type = PERF_RECORD_SAMPLE;
1288 header->size = sizeof(*header) + event->header_size;
1289 header->misc = 0;
1290
1291 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1292 switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) {
1293 case 0:
1294 header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1295 break;
1296 case 1:
1297 header->misc |= PERF_RECORD_MISC_GUEST_USER;
1298 break;
1299 case 2:
1300 header->misc |= PERF_RECORD_MISC_KERNEL;
1301 break;
1302 case 3:
1303 header->misc |= PERF_RECORD_MISC_USER;
1304 break;
1305 default:
1306 pr_info("IMC: Unable to set the flag based on MSR bits\n");
1307 break;
1308 }
1309 } else {
1310 if (is_kernel_addr(data->ip))
1311 header->misc |= PERF_RECORD_MISC_KERNEL;
1312 else
1313 header->misc |= PERF_RECORD_MISC_USER;
1314 }
1315 perf_event_header__init_id(header, data, event);
1316
1317 return 0;
1318}
1319
1320static void dump_trace_imc_data(struct perf_event *event)
1321{
1322 struct trace_imc_data *mem;
1323 int i, ret;
1324 u64 prev_tb = 0;
1325
1326 mem = (struct trace_imc_data *)get_trace_imc_event_base_addr();
1327 for (i = 0; i < (trace_imc_mem_size / sizeof(struct trace_imc_data));
1328 i++, mem++) {
1329 struct perf_sample_data data;
1330 struct perf_event_header header;
1331
1332 ret = trace_imc_prepare_sample(mem, &data, &prev_tb, &header, event);
1333 if (ret)
1334 break;
1335 else {
1336
1337 struct perf_output_handle handle;
1338
1339 if (perf_output_begin(&handle, &data, event, header.size))
1340 return;
1341
1342 perf_output_sample(&handle, &header, &data, event);
1343 perf_output_end(&handle);
1344 }
1345 }
1346}
1347
1348static int trace_imc_event_add(struct perf_event *event, int flags)
1349{
1350 int core_id = smp_processor_id() / threads_per_core;
1351 struct imc_pmu_ref *ref = NULL;
1352 u64 local_mem, ldbar_value;
1353
1354
1355 local_mem = get_trace_imc_event_base_addr();
1356 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | TRACE_IMC_ENABLE;
1357
1358
1359 if (trace_imc_refc)
1360 ref = &trace_imc_refc[core_id];
1361 if (!ref) {
1362 pr_debug("imc: Failed to get the event reference count\n");
1363 return -EINVAL;
1364 }
1365
1366 mtspr(SPRN_LDBAR, ldbar_value);
1367 mutex_lock(&ref->lock);
1368 if (ref->refc == 0) {
1369 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_TRACE,
1370 get_hard_smp_processor_id(smp_processor_id()))) {
1371 mutex_unlock(&ref->lock);
1372 pr_err("trace-imc: Unable to start the counters for core %d\n", core_id);
1373 return -EINVAL;
1374 }
1375 }
1376 ++ref->refc;
1377 mutex_unlock(&ref->lock);
1378 return 0;
1379}
1380
1381static void trace_imc_event_read(struct perf_event *event)
1382{
1383 return;
1384}
1385
1386static void trace_imc_event_stop(struct perf_event *event, int flags)
1387{
1388 u64 local_mem = get_trace_imc_event_base_addr();
1389 dump_trace_imc_data(event);
1390 memset((void *)local_mem, 0, sizeof(u64));
1391}
1392
1393static void trace_imc_event_start(struct perf_event *event, int flags)
1394{
1395 return;
1396}
1397
1398static void trace_imc_event_del(struct perf_event *event, int flags)
1399{
1400 int core_id = smp_processor_id() / threads_per_core;
1401 struct imc_pmu_ref *ref = NULL;
1402
1403 if (trace_imc_refc)
1404 ref = &trace_imc_refc[core_id];
1405 if (!ref) {
1406 pr_debug("imc: Failed to get event reference count\n");
1407 return;
1408 }
1409
1410 mutex_lock(&ref->lock);
1411 ref->refc--;
1412 if (ref->refc == 0) {
1413 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_TRACE,
1414 get_hard_smp_processor_id(smp_processor_id()))) {
1415 mutex_unlock(&ref->lock);
1416 pr_err("trace-imc: Unable to stop the counters for core %d\n", core_id);
1417 return;
1418 }
1419 } else if (ref->refc < 0) {
1420 ref->refc = 0;
1421 }
1422 mutex_unlock(&ref->lock);
1423
1424 trace_imc_event_stop(event, flags);
1425}
1426
1427static int trace_imc_event_init(struct perf_event *event)
1428{
1429 if (event->attr.type != event->pmu->type)
1430 return -ENOENT;
1431
1432 if (!perfmon_capable())
1433 return -EACCES;
1434
1435
1436 if (event->attr.sample_period == 0)
1437 return -ENOENT;
1438
1439
1440
1441
1442
1443
1444 mutex_lock(&imc_global_refc.lock);
1445 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_TRACE) {
1446
1447
1448
1449
1450 imc_global_refc.id = IMC_DOMAIN_TRACE;
1451 imc_global_refc.refc++;
1452 } else {
1453 mutex_unlock(&imc_global_refc.lock);
1454 return -EBUSY;
1455 }
1456 mutex_unlock(&imc_global_refc.lock);
1457
1458 event->hw.idx = -1;
1459
1460 event->pmu->task_ctx_nr = perf_hw_context;
1461 event->destroy = reset_global_refc;
1462 return 0;
1463}
1464
1465
1466static int update_pmu_ops(struct imc_pmu *pmu)
1467{
1468 pmu->pmu.task_ctx_nr = perf_invalid_context;
1469 pmu->pmu.add = imc_event_add;
1470 pmu->pmu.del = imc_event_stop;
1471 pmu->pmu.start = imc_event_start;
1472 pmu->pmu.stop = imc_event_stop;
1473 pmu->pmu.read = imc_event_update;
1474 pmu->pmu.attr_groups = pmu->attr_groups;
1475 pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1476 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1477
1478 switch (pmu->domain) {
1479 case IMC_DOMAIN_NEST:
1480 pmu->pmu.event_init = nest_imc_event_init;
1481 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1482 break;
1483 case IMC_DOMAIN_CORE:
1484 pmu->pmu.event_init = core_imc_event_init;
1485 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1486 break;
1487 case IMC_DOMAIN_THREAD:
1488 pmu->pmu.event_init = thread_imc_event_init;
1489 pmu->pmu.add = thread_imc_event_add;
1490 pmu->pmu.del = thread_imc_event_del;
1491 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1492 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1493 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1494 break;
1495 case IMC_DOMAIN_TRACE:
1496 pmu->pmu.event_init = trace_imc_event_init;
1497 pmu->pmu.add = trace_imc_event_add;
1498 pmu->pmu.del = trace_imc_event_del;
1499 pmu->pmu.start = trace_imc_event_start;
1500 pmu->pmu.stop = trace_imc_event_stop;
1501 pmu->pmu.read = trace_imc_event_read;
1502 pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
1503 break;
1504 default:
1505 break;
1506 }
1507
1508 return 0;
1509}
1510
1511
1512static int init_nest_pmu_ref(void)
1513{
1514 int nid, i, cpu;
1515
1516 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1517 GFP_KERNEL);
1518
1519 if (!nest_imc_refc)
1520 return -ENOMEM;
1521
1522 i = 0;
1523 for_each_node(nid) {
1524
1525
1526
1527
1528 mutex_init(&nest_imc_refc[i].lock);
1529
1530
1531
1532
1533
1534
1535
1536 nest_imc_refc[i++].id = nid;
1537 }
1538
1539
1540
1541
1542
1543 for_each_possible_cpu(cpu) {
1544 nid = cpu_to_node(cpu);
1545 for (i = 0; i < num_possible_nodes(); i++) {
1546 if (nest_imc_refc[i].id == nid) {
1547 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1548 break;
1549 }
1550 }
1551 }
1552 return 0;
1553}
1554
1555static void cleanup_all_core_imc_memory(void)
1556{
1557 int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1558 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1559 int size = core_imc_pmu->counter_mem_size;
1560
1561
1562 for (i = 0; i < nr_cores; i++) {
1563 if (ptr[i].vbase)
1564 free_pages((u64)ptr[i].vbase, get_order(size));
1565 }
1566
1567 kfree(ptr);
1568 kfree(core_imc_refc);
1569}
1570
1571static void thread_imc_ldbar_disable(void *dummy)
1572{
1573
1574
1575
1576
1577 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1578}
1579
1580void thread_imc_disable(void)
1581{
1582 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1583}
1584
1585static void cleanup_all_thread_imc_memory(void)
1586{
1587 int i, order = get_order(thread_imc_mem_size);
1588
1589 for_each_online_cpu(i) {
1590 if (per_cpu(thread_imc_mem, i))
1591 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1592
1593 }
1594}
1595
1596static void cleanup_all_trace_imc_memory(void)
1597{
1598 int i, order = get_order(trace_imc_mem_size);
1599
1600 for_each_online_cpu(i) {
1601 if (per_cpu(trace_imc_mem, i))
1602 free_pages((u64)per_cpu(trace_imc_mem, i), order);
1603
1604 }
1605 kfree(trace_imc_refc);
1606}
1607
1608
1609static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1610{
1611 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1612 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1613 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1614}
1615
1616
1617
1618
1619
1620
1621
1622static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1623{
1624 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1625 mutex_lock(&nest_init_lock);
1626 if (nest_pmus == 1) {
1627 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1628 kfree(nest_imc_refc);
1629 kfree(per_nest_pmu_arr);
1630 per_nest_pmu_arr = NULL;
1631 }
1632
1633 if (nest_pmus > 0)
1634 nest_pmus--;
1635 mutex_unlock(&nest_init_lock);
1636 }
1637
1638
1639 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1640 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1641 cleanup_all_core_imc_memory();
1642 }
1643
1644
1645 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1646 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1647 cleanup_all_thread_imc_memory();
1648 }
1649
1650 if (pmu_ptr->domain == IMC_DOMAIN_TRACE) {
1651 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE);
1652 cleanup_all_trace_imc_memory();
1653 }
1654}
1655
1656
1657
1658
1659
1660void unregister_thread_imc(void)
1661{
1662 imc_common_cpuhp_mem_free(thread_imc_pmu);
1663 imc_common_mem_free(thread_imc_pmu);
1664 perf_pmu_unregister(&thread_imc_pmu->pmu);
1665}
1666
1667
1668
1669
1670static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1671 int pmu_index)
1672{
1673 const char *s;
1674 int nr_cores, cpu, res = -ENOMEM;
1675
1676 if (of_property_read_string(parent, "name", &s))
1677 return -ENODEV;
1678
1679 switch (pmu_ptr->domain) {
1680 case IMC_DOMAIN_NEST:
1681
1682 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1683 if (!pmu_ptr->pmu.name)
1684 goto err;
1685
1686
1687 if (!per_nest_pmu_arr) {
1688 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1689 sizeof(struct imc_pmu *),
1690 GFP_KERNEL);
1691 if (!per_nest_pmu_arr)
1692 goto err;
1693 }
1694 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1695 break;
1696 case IMC_DOMAIN_CORE:
1697
1698 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1699 if (!pmu_ptr->pmu.name)
1700 goto err;
1701
1702 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1703 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1704 GFP_KERNEL);
1705
1706 if (!pmu_ptr->mem_info)
1707 goto err;
1708
1709 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1710 GFP_KERNEL);
1711
1712 if (!core_imc_refc) {
1713 kfree(pmu_ptr->mem_info);
1714 goto err;
1715 }
1716
1717 core_imc_pmu = pmu_ptr;
1718 break;
1719 case IMC_DOMAIN_THREAD:
1720
1721 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1722 if (!pmu_ptr->pmu.name)
1723 goto err;
1724
1725 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1726 for_each_online_cpu(cpu) {
1727 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1728 if (res) {
1729 cleanup_all_thread_imc_memory();
1730 goto err;
1731 }
1732 }
1733
1734 thread_imc_pmu = pmu_ptr;
1735 break;
1736 case IMC_DOMAIN_TRACE:
1737
1738 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1739 if (!pmu_ptr->pmu.name)
1740 return -ENOMEM;
1741
1742 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1743 trace_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1744 GFP_KERNEL);
1745 if (!trace_imc_refc)
1746 return -ENOMEM;
1747
1748 trace_imc_mem_size = pmu_ptr->counter_mem_size;
1749 for_each_online_cpu(cpu) {
1750 res = trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1751 if (res) {
1752 cleanup_all_trace_imc_memory();
1753 goto err;
1754 }
1755 }
1756 break;
1757 default:
1758 return -EINVAL;
1759 }
1760
1761 return 0;
1762err:
1763 return res;
1764}
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1777{
1778 int ret;
1779
1780 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1781 if (ret)
1782 goto err_free_mem;
1783
1784 switch (pmu_ptr->domain) {
1785 case IMC_DOMAIN_NEST:
1786
1787
1788
1789
1790
1791
1792 mutex_lock(&nest_init_lock);
1793 if (nest_pmus == 0) {
1794 ret = init_nest_pmu_ref();
1795 if (ret) {
1796 mutex_unlock(&nest_init_lock);
1797 kfree(per_nest_pmu_arr);
1798 per_nest_pmu_arr = NULL;
1799 goto err_free_mem;
1800 }
1801
1802 ret = nest_pmu_cpumask_init();
1803 if (ret) {
1804 mutex_unlock(&nest_init_lock);
1805 kfree(nest_imc_refc);
1806 kfree(per_nest_pmu_arr);
1807 per_nest_pmu_arr = NULL;
1808 goto err_free_mem;
1809 }
1810 }
1811 nest_pmus++;
1812 mutex_unlock(&nest_init_lock);
1813 break;
1814 case IMC_DOMAIN_CORE:
1815 ret = core_imc_pmu_cpumask_init();
1816 if (ret) {
1817 cleanup_all_core_imc_memory();
1818 goto err_free_mem;
1819 }
1820
1821 break;
1822 case IMC_DOMAIN_THREAD:
1823 ret = thread_imc_cpu_init();
1824 if (ret) {
1825 cleanup_all_thread_imc_memory();
1826 goto err_free_mem;
1827 }
1828
1829 break;
1830 case IMC_DOMAIN_TRACE:
1831 ret = trace_imc_cpu_init();
1832 if (ret) {
1833 cleanup_all_trace_imc_memory();
1834 goto err_free_mem;
1835 }
1836
1837 break;
1838 default:
1839 return -EINVAL;
1840 }
1841
1842 ret = update_events_in_group(parent, pmu_ptr);
1843 if (ret)
1844 goto err_free_cpuhp_mem;
1845
1846 ret = update_pmu_ops(pmu_ptr);
1847 if (ret)
1848 goto err_free_cpuhp_mem;
1849
1850 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1851 if (ret)
1852 goto err_free_cpuhp_mem;
1853
1854 pr_debug("%s performance monitor hardware support registered\n",
1855 pmu_ptr->pmu.name);
1856
1857 return 0;
1858
1859err_free_cpuhp_mem:
1860 imc_common_cpuhp_mem_free(pmu_ptr);
1861err_free_mem:
1862 imc_common_mem_free(pmu_ptr);
1863 return ret;
1864}
1865