LXR linux/arch/parisc/include/asm/cache.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * include/asm-parisc/cache.h
   4 */
   5
   6#ifndef __ARCH_PARISC_CACHE_H
   7#define __ARCH_PARISC_CACHE_H
   8
   9#include <asm/alternative.h>
  10
  11/*
  12 * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
  13 * have 32-byte cachelines.  The L1 length appears to be 16 bytes but this
  14 * is not clearly documented.
  15 */
  16#define L1_CACHE_BYTES 16
  17#define L1_CACHE_SHIFT 4
  18
  19#ifndef __ASSEMBLY__
  20
  21#define SMP_CACHE_BYTES L1_CACHE_BYTES
  22
  23#define ARCH_DMA_MINALIGN       L1_CACHE_BYTES
  24
  25#define __read_mostly __section(".data..read_mostly")
  26
  27void parisc_cache_init(void);   /* initializes cache-flushing */
  28void disable_sr_hashing_asm(int); /* low level support for above */
  29void disable_sr_hashing(void);   /* turns off space register hashing */
  30void free_sid(unsigned long);
  31unsigned long alloc_sid(void);
  32
  33struct seq_file;
  34extern void show_cache_info(struct seq_file *m);
  35
  36extern int split_tlb;
  37extern int dcache_stride;
  38extern int icache_stride;
  39extern struct pdc_cache_info cache_info;
  40void parisc_setup_cache_timing(void);
  41
  42#define pdtlb(addr)     asm volatile("pdtlb 0(%%sr1,%0)" \
  43                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
  44                        : : "r" (addr) : "memory")
  45#define pitlb(addr)     asm volatile("pitlb 0(%%sr1,%0)" \
  46                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
  47                        ALTERNATIVE(ALT_COND_NO_SPLIT_TLB, INSN_NOP) \
  48                        : : "r" (addr) : "memory")
  49#define pdtlb_kernel(addr)  asm volatile("pdtlb 0(%0)"   \
  50                        ALTERNATIVE(ALT_COND_NO_SMP, INSN_PxTLB) \
  51                        : : "r" (addr) : "memory")
  52
  53#define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
  54                        ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
  55                        ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
  56                        : : "r" (addr) : "memory")
  57#define asm_io_sync()   asm volatile("sync" \
  58                        ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
  59                        ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
  60
  61#endif /* ! __ASSEMBLY__ */
  62
  63/* Classes of processor wrt: disabling space register hashing */
  64
  65#define SRHASH_PCXST    0   /* pcxs, pcxt, pcxt_ */
  66#define SRHASH_PCXL     1   /* pcxl */
  67#define SRHASH_PA20     2   /* pcxu, pcxu_, pcxw, pcxw_ */
  68
  69#endif
  70