linux/arch/openrisc/include/asm/spr_defs.h
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   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * OpenRISC Linux
   4 *
   5 * SPR Definitions
   6 *
   7 * Copyright (C) 2000 Damjan Lampret
   8 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
   9 * Copyright (C) 2008, 2010 Embecosm Limited
  10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
  11 * et al.
  12 *
  13 * This file is part of OpenRISC 1000 Architectural Simulator.
  14 */
  15
  16#ifndef SPR_DEFS__H
  17#define SPR_DEFS__H
  18
  19/* Definition of special-purpose registers (SPRs). */
  20
  21#define MAX_GRPS (32)
  22#define MAX_SPRS_PER_GRP_BITS (11)
  23#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS)
  24#define MAX_SPRS (0x10000)
  25
  26/* Base addresses for the groups */
  27#define SPRGROUP_SYS    (0 << MAX_SPRS_PER_GRP_BITS)
  28#define SPRGROUP_DMMU   (1 << MAX_SPRS_PER_GRP_BITS)
  29#define SPRGROUP_IMMU   (2 << MAX_SPRS_PER_GRP_BITS)
  30#define SPRGROUP_DC     (3 << MAX_SPRS_PER_GRP_BITS)
  31#define SPRGROUP_IC     (4 << MAX_SPRS_PER_GRP_BITS)
  32#define SPRGROUP_MAC    (5 << MAX_SPRS_PER_GRP_BITS)
  33#define SPRGROUP_D      (6 << MAX_SPRS_PER_GRP_BITS)
  34#define SPRGROUP_PC     (7 << MAX_SPRS_PER_GRP_BITS)
  35#define SPRGROUP_PM     (8 << MAX_SPRS_PER_GRP_BITS)
  36#define SPRGROUP_PIC    (9 << MAX_SPRS_PER_GRP_BITS)
  37#define SPRGROUP_TT     (10 << MAX_SPRS_PER_GRP_BITS)
  38#define SPRGROUP_FP     (11 << MAX_SPRS_PER_GRP_BITS)
  39
  40/* System control and status group */
  41#define SPR_VR          (SPRGROUP_SYS + 0)
  42#define SPR_UPR         (SPRGROUP_SYS + 1)
  43#define SPR_CPUCFGR     (SPRGROUP_SYS + 2)
  44#define SPR_DMMUCFGR    (SPRGROUP_SYS + 3)
  45#define SPR_IMMUCFGR    (SPRGROUP_SYS + 4)
  46#define SPR_DCCFGR      (SPRGROUP_SYS + 5)
  47#define SPR_ICCFGR      (SPRGROUP_SYS + 6)
  48#define SPR_DCFGR       (SPRGROUP_SYS + 7)
  49#define SPR_PCCFGR      (SPRGROUP_SYS + 8)
  50#define SPR_VR2         (SPRGROUP_SYS + 9)
  51#define SPR_AVR         (SPRGROUP_SYS + 10)
  52#define SPR_EVBAR       (SPRGROUP_SYS + 11)
  53#define SPR_AECR        (SPRGROUP_SYS + 12)
  54#define SPR_AESR        (SPRGROUP_SYS + 13)
  55#define SPR_NPC         (SPRGROUP_SYS + 16)  /* CZ 21/06/01 */
  56#define SPR_SR          (SPRGROUP_SYS + 17)  /* CZ 21/06/01 */
  57#define SPR_PPC         (SPRGROUP_SYS + 18)  /* CZ 21/06/01 */
  58#define SPR_FPCSR       (SPRGROUP_SYS + 20)  /* CZ 21/06/01 */
  59#define SPR_EPCR_BASE   (SPRGROUP_SYS + 32)  /* CZ 21/06/01 */
  60#define SPR_EPCR_LAST   (SPRGROUP_SYS + 47)  /* CZ 21/06/01 */
  61#define SPR_EEAR_BASE   (SPRGROUP_SYS + 48)
  62#define SPR_EEAR_LAST   (SPRGROUP_SYS + 63)
  63#define SPR_ESR_BASE    (SPRGROUP_SYS + 64)
  64#define SPR_ESR_LAST    (SPRGROUP_SYS + 79)
  65#define SPR_COREID      (SPRGROUP_SYS + 128)
  66#define SPR_NUMCORES    (SPRGROUP_SYS + 129)
  67#define SPR_GPR_BASE    (SPRGROUP_SYS + 1024)
  68
  69/* Data MMU group */
  70#define SPR_DMMUCR      (SPRGROUP_DMMU + 0)
  71#define SPR_DTLBEIR     (SPRGROUP_DMMU + 2)
  72#define SPR_DTLBMR_BASE(WAY)    (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
  73#define SPR_DTLBMR_LAST(WAY)    (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
  74#define SPR_DTLBTR_BASE(WAY)    (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
  75#define SPR_DTLBTR_LAST(WAY)    (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
  76
  77/* Instruction MMU group */
  78#define SPR_IMMUCR      (SPRGROUP_IMMU + 0)
  79#define SPR_ITLBEIR     (SPRGROUP_IMMU + 2)
  80#define SPR_ITLBMR_BASE(WAY)    (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
  81#define SPR_ITLBMR_LAST(WAY)    (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
  82#define SPR_ITLBTR_BASE(WAY)    (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
  83#define SPR_ITLBTR_LAST(WAY)    (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
  84
  85/* Data cache group */
  86#define SPR_DCCR        (SPRGROUP_DC + 0)
  87#define SPR_DCBPR       (SPRGROUP_DC + 1)
  88#define SPR_DCBFR       (SPRGROUP_DC + 2)
  89#define SPR_DCBIR       (SPRGROUP_DC + 3)
  90#define SPR_DCBWR       (SPRGROUP_DC + 4)
  91#define SPR_DCBLR       (SPRGROUP_DC + 5)
  92#define SPR_DCR_BASE(WAY)       (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
  93#define SPR_DCR_LAST(WAY)       (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
  94
  95/* Instruction cache group */
  96#define SPR_ICCR        (SPRGROUP_IC + 0)
  97#define SPR_ICBPR       (SPRGROUP_IC + 1)
  98#define SPR_ICBIR       (SPRGROUP_IC + 2)
  99#define SPR_ICBLR       (SPRGROUP_IC + 3)
 100#define SPR_ICR_BASE(WAY)       (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
 101#define SPR_ICR_LAST(WAY)       (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
 102
 103/* MAC group */
 104#define SPR_MACLO       (SPRGROUP_MAC + 1)
 105#define SPR_MACHI       (SPRGROUP_MAC + 2)
 106
 107/* Debug group */
 108#define SPR_DVR(N)      (SPRGROUP_D + (N))
 109#define SPR_DCR(N)      (SPRGROUP_D + 8 + (N))
 110#define SPR_DMR1        (SPRGROUP_D + 16)
 111#define SPR_DMR2        (SPRGROUP_D + 17)
 112#define SPR_DWCR0       (SPRGROUP_D + 18)
 113#define SPR_DWCR1       (SPRGROUP_D + 19)
 114#define SPR_DSR         (SPRGROUP_D + 20)
 115#define SPR_DRR         (SPRGROUP_D + 21)
 116
 117/* Performance counters group */
 118#define SPR_PCCR(N)     (SPRGROUP_PC + (N))
 119#define SPR_PCMR(N)     (SPRGROUP_PC + 8 + (N))
 120
 121/* Power management group */
 122#define SPR_PMR (SPRGROUP_PM + 0)
 123
 124/* PIC group */
 125#define SPR_PICMR (SPRGROUP_PIC + 0)
 126#define SPR_PICPR (SPRGROUP_PIC + 1)
 127#define SPR_PICSR (SPRGROUP_PIC + 2)
 128
 129/* Tick Timer group */
 130#define SPR_TTMR (SPRGROUP_TT + 0)
 131#define SPR_TTCR (SPRGROUP_TT + 1)
 132
 133/*
 134 * Bit definitions for the Version Register
 135 *
 136 */
 137#define SPR_VR_VER      0xff000000  /* Processor version */
 138#define SPR_VR_CFG      0x00ff0000  /* Processor configuration */
 139#define SPR_VR_RES      0x0000ffc0  /* Reserved */
 140#define SPR_VR_REV      0x0000003f  /* Processor revision */
 141#define SPR_VR_UVRP     0x00000040  /* Updated Version Registers Present */
 142
 143#define SPR_VR_VER_OFF  24
 144#define SPR_VR_CFG_OFF  16
 145#define SPR_VR_REV_OFF  0
 146
 147/*
 148 * Bit definitions for the Version Register 2
 149 */
 150#define SPR_VR2_CPUID   0xff000000  /* Processor ID */
 151#define SPR_VR2_VER     0x00ffffff  /* Processor version */
 152
 153/*
 154 * Bit definitions for the Unit Present Register
 155 *
 156 */
 157#define SPR_UPR_UP         0x00000001  /* UPR present */
 158#define SPR_UPR_DCP        0x00000002  /* Data cache present */
 159#define SPR_UPR_ICP        0x00000004  /* Instruction cache present */
 160#define SPR_UPR_DMP        0x00000008  /* Data MMU present */
 161#define SPR_UPR_IMP        0x00000010  /* Instruction MMU present */
 162#define SPR_UPR_MP         0x00000020  /* MAC present */
 163#define SPR_UPR_DUP        0x00000040  /* Debug unit present */
 164#define SPR_UPR_PCUP       0x00000080  /* Performance counters unit present */
 165#define SPR_UPR_PICP       0x00000100  /* PIC present */
 166#define SPR_UPR_PMP        0x00000200  /* Power management present */
 167#define SPR_UPR_TTP        0x00000400  /* Tick timer present */
 168#define SPR_UPR_RES        0x00fe0000  /* Reserved */
 169#define SPR_UPR_CUP        0xff000000  /* Context units present */
 170
 171/*
 172 * JPB: Bit definitions for the CPU configuration register
 173 *
 174 */
 175#define SPR_CPUCFGR_NSGF   0x0000000f  /* Number of shadow GPR files */
 176#define SPR_CPUCFGR_CGF    0x00000010  /* Custom GPR file */
 177#define SPR_CPUCFGR_OB32S  0x00000020  /* ORBIS32 supported */
 178#define SPR_CPUCFGR_OB64S  0x00000040  /* ORBIS64 supported */
 179#define SPR_CPUCFGR_OF32S  0x00000080  /* ORFPX32 supported */
 180#define SPR_CPUCFGR_OF64S  0x00000100  /* ORFPX64 supported */
 181#define SPR_CPUCFGR_OV64S  0x00000200  /* ORVDX64 supported */
 182#define SPR_CPUCFGR_RES    0xfffffc00  /* Reserved */
 183
 184/*
 185 * JPB: Bit definitions for the Debug configuration register and other
 186 * constants.
 187 *
 188 */
 189
 190#define SPR_DCFGR_NDP      0x00000007  /* Number of matchpoints mask */
 191#define SPR_DCFGR_NDP1     0x00000000  /* One matchpoint supported */
 192#define SPR_DCFGR_NDP2     0x00000001  /* Two matchpoints supported */
 193#define SPR_DCFGR_NDP3     0x00000002  /* Three matchpoints supported */
 194#define SPR_DCFGR_NDP4     0x00000003  /* Four matchpoints supported */
 195#define SPR_DCFGR_NDP5     0x00000004  /* Five matchpoints supported */
 196#define SPR_DCFGR_NDP6     0x00000005  /* Six matchpoints supported */
 197#define SPR_DCFGR_NDP7     0x00000006  /* Seven matchpoints supported */
 198#define SPR_DCFGR_NDP8     0x00000007  /* Eight matchpoints supported */
 199#define SPR_DCFGR_WPCI     0x00000008  /* Watchpoint counters implemented */
 200
 201#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
 202                               2 == n ? SPR_DCFGR_NDP2 : \
 203                               3 == n ? SPR_DCFGR_NDP3 : \
 204                               4 == n ? SPR_DCFGR_NDP4 : \
 205                               5 == n ? SPR_DCFGR_NDP5 : \
 206                               6 == n ? SPR_DCFGR_NDP6 : \
 207                               7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
 208#define MAX_MATCHPOINTS  8
 209#define MAX_WATCHPOINTS  (MAX_MATCHPOINTS + 2)
 210
 211/*
 212 * Bit definitions for the Supervision Register
 213 *
 214 */
 215#define SPR_SR_SM          0x00000001  /* Supervisor Mode */
 216#define SPR_SR_TEE         0x00000002  /* Tick timer Exception Enable */
 217#define SPR_SR_IEE         0x00000004  /* Interrupt Exception Enable */
 218#define SPR_SR_DCE         0x00000008  /* Data Cache Enable */
 219#define SPR_SR_ICE         0x00000010  /* Instruction Cache Enable */
 220#define SPR_SR_DME         0x00000020  /* Data MMU Enable */
 221#define SPR_SR_IME         0x00000040  /* Instruction MMU Enable */
 222#define SPR_SR_LEE         0x00000080  /* Little Endian Enable */
 223#define SPR_SR_CE          0x00000100  /* CID Enable */
 224#define SPR_SR_F           0x00000200  /* Condition Flag */
 225#define SPR_SR_CY          0x00000400  /* Carry flag */
 226#define SPR_SR_OV          0x00000800  /* Overflow flag */
 227#define SPR_SR_OVE         0x00001000  /* Overflow flag Exception */
 228#define SPR_SR_DSX         0x00002000  /* Delay Slot Exception */
 229#define SPR_SR_EPH         0x00004000  /* Exception Prefix High */
 230#define SPR_SR_FO          0x00008000  /* Fixed one */
 231#define SPR_SR_SUMRA       0x00010000  /* Supervisor SPR read access */
 232#define SPR_SR_RES         0x0ffe0000  /* Reserved */
 233#define SPR_SR_CID         0xf0000000  /* Context ID */
 234
 235/*
 236 * Bit definitions for the Data MMU Control Register
 237 *
 238 */
 239#define SPR_DMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
 240#define SPR_DMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
 241#define SPR_DMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
 242#define SPR_DMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
 243
 244/*
 245 * Bit definitions for the Instruction MMU Control Register
 246 *
 247 */
 248#define SPR_IMMUCR_P2S     0x0000003e  /* Level 2 Page Size */
 249#define SPR_IMMUCR_P1S     0x000007c0  /* Level 1 Page Size */
 250#define SPR_IMMUCR_VADDR_WIDTH  0x0000f800  /* Virtual ADDR Width */
 251#define SPR_IMMUCR_PADDR_WIDTH  0x000f0000  /* Physical ADDR Width */
 252
 253/*
 254 * Bit definitions for the Data TLB Match Register
 255 *
 256 */
 257#define SPR_DTLBMR_V       0x00000001  /* Valid */
 258#define SPR_DTLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
 259#define SPR_DTLBMR_CID     0x0000003c  /* Context ID */
 260#define SPR_DTLBMR_LRU     0x000000c0  /* Least Recently Used */
 261#define SPR_DTLBMR_VPN     0xfffff000  /* Virtual Page Number */
 262
 263/*
 264 * Bit definitions for the Data TLB Translate Register
 265 *
 266 */
 267#define SPR_DTLBTR_CC      0x00000001  /* Cache Coherency */
 268#define SPR_DTLBTR_CI      0x00000002  /* Cache Inhibit */
 269#define SPR_DTLBTR_WBC     0x00000004  /* Write-Back Cache */
 270#define SPR_DTLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
 271#define SPR_DTLBTR_A       0x00000010  /* Accessed */
 272#define SPR_DTLBTR_D       0x00000020  /* Dirty */
 273#define SPR_DTLBTR_URE     0x00000040  /* User Read Enable */
 274#define SPR_DTLBTR_UWE     0x00000080  /* User Write Enable */
 275#define SPR_DTLBTR_SRE     0x00000100  /* Supervisor Read Enable */
 276#define SPR_DTLBTR_SWE     0x00000200  /* Supervisor Write Enable */
 277#define SPR_DTLBTR_PPN     0xfffff000  /* Physical Page Number */
 278
 279/*
 280 * Bit definitions for the Instruction TLB Match Register
 281 *
 282 */
 283#define SPR_ITLBMR_V       0x00000001  /* Valid */
 284#define SPR_ITLBMR_PL1     0x00000002  /* Page Level 1 (if 0 then PL2) */
 285#define SPR_ITLBMR_CID     0x0000003c  /* Context ID */
 286#define SPR_ITLBMR_LRU     0x000000c0  /* Least Recently Used */
 287#define SPR_ITLBMR_VPN     0xfffff000  /* Virtual Page Number */
 288
 289/*
 290 * Bit definitions for the Instruction TLB Translate Register
 291 *
 292 */
 293#define SPR_ITLBTR_CC      0x00000001  /* Cache Coherency */
 294#define SPR_ITLBTR_CI      0x00000002  /* Cache Inhibit */
 295#define SPR_ITLBTR_WBC     0x00000004  /* Write-Back Cache */
 296#define SPR_ITLBTR_WOM     0x00000008  /* Weakly-Ordered Memory */
 297#define SPR_ITLBTR_A       0x00000010  /* Accessed */
 298#define SPR_ITLBTR_D       0x00000020  /* Dirty */
 299#define SPR_ITLBTR_SXE     0x00000040  /* User Read Enable */
 300#define SPR_ITLBTR_UXE     0x00000080  /* User Write Enable */
 301#define SPR_ITLBTR_PPN     0xfffff000  /* Physical Page Number */
 302
 303/*
 304 * Bit definitions for Data Cache Control register
 305 *
 306 */
 307#define SPR_DCCR_EW        0x000000ff  /* Enable ways */
 308
 309/*
 310 * Bit definitions for Insn Cache Control register
 311 *
 312 */
 313#define SPR_ICCR_EW        0x000000ff  /* Enable ways */
 314
 315/*
 316 * Bit definitions for Data Cache Configuration Register
 317 *
 318 */
 319
 320#define SPR_DCCFGR_NCW          0x00000007
 321#define SPR_DCCFGR_NCS          0x00000078
 322#define SPR_DCCFGR_CBS          0x00000080
 323#define SPR_DCCFGR_CWS          0x00000100
 324#define SPR_DCCFGR_CCRI         0x00000200
 325#define SPR_DCCFGR_CBIRI        0x00000400
 326#define SPR_DCCFGR_CBPRI        0x00000800
 327#define SPR_DCCFGR_CBLRI        0x00001000
 328#define SPR_DCCFGR_CBFRI        0x00002000
 329#define SPR_DCCFGR_CBWBRI       0x00004000
 330
 331#define SPR_DCCFGR_NCW_OFF      0
 332#define SPR_DCCFGR_NCS_OFF      3
 333#define SPR_DCCFGR_CBS_OFF      7
 334
 335/*
 336 * Bit definitions for Instruction Cache Configuration Register
 337 *
 338 */
 339#define SPR_ICCFGR_NCW          0x00000007
 340#define SPR_ICCFGR_NCS          0x00000078
 341#define SPR_ICCFGR_CBS          0x00000080
 342#define SPR_ICCFGR_CCRI         0x00000200
 343#define SPR_ICCFGR_CBIRI        0x00000400
 344#define SPR_ICCFGR_CBPRI        0x00000800
 345#define SPR_ICCFGR_CBLRI        0x00001000
 346
 347#define SPR_ICCFGR_NCW_OFF      0
 348#define SPR_ICCFGR_NCS_OFF      3
 349#define SPR_ICCFGR_CBS_OFF      7
 350
 351/*
 352 * Bit definitions for Data MMU Configuration Register
 353 *
 354 */
 355
 356#define SPR_DMMUCFGR_NTW        0x00000003
 357#define SPR_DMMUCFGR_NTS        0x0000001C
 358#define SPR_DMMUCFGR_NAE        0x000000E0
 359#define SPR_DMMUCFGR_CRI        0x00000100
 360#define SPR_DMMUCFGR_PRI        0x00000200
 361#define SPR_DMMUCFGR_TEIRI      0x00000400
 362#define SPR_DMMUCFGR_HTR        0x00000800
 363
 364#define SPR_DMMUCFGR_NTW_OFF    0
 365#define SPR_DMMUCFGR_NTS_OFF    2
 366
 367/*
 368 * Bit definitions for Instruction MMU Configuration Register
 369 *
 370 */
 371
 372#define SPR_IMMUCFGR_NTW        0x00000003
 373#define SPR_IMMUCFGR_NTS        0x0000001C
 374#define SPR_IMMUCFGR_NAE        0x000000E0
 375#define SPR_IMMUCFGR_CRI        0x00000100
 376#define SPR_IMMUCFGR_PRI        0x00000200
 377#define SPR_IMMUCFGR_TEIRI      0x00000400
 378#define SPR_IMMUCFGR_HTR        0x00000800
 379
 380#define SPR_IMMUCFGR_NTW_OFF    0
 381#define SPR_IMMUCFGR_NTS_OFF    2
 382
 383/*
 384 * Bit definitions for Debug Control registers
 385 *
 386 */
 387#define SPR_DCR_DP      0x00000001  /* DVR/DCR present */
 388#define SPR_DCR_CC      0x0000000e  /* Compare condition */
 389#define SPR_DCR_SC      0x00000010  /* Signed compare */
 390#define SPR_DCR_CT      0x000000e0  /* Compare to */
 391
 392/* Bit results with SPR_DCR_CC mask */
 393#define SPR_DCR_CC_MASKED 0x00000000
 394#define SPR_DCR_CC_EQUAL  0x00000002
 395#define SPR_DCR_CC_LESS   0x00000004
 396#define SPR_DCR_CC_LESSE  0x00000006
 397#define SPR_DCR_CC_GREAT  0x00000008
 398#define SPR_DCR_CC_GREATE 0x0000000a
 399#define SPR_DCR_CC_NEQUAL 0x0000000c
 400
 401/* Bit results with SPR_DCR_CT mask */
 402#define SPR_DCR_CT_DISABLED 0x00000000
 403#define SPR_DCR_CT_IFEA     0x00000020
 404#define SPR_DCR_CT_LEA      0x00000040
 405#define SPR_DCR_CT_SEA      0x00000060
 406#define SPR_DCR_CT_LD       0x00000080
 407#define SPR_DCR_CT_SD       0x000000a0
 408#define SPR_DCR_CT_LSEA     0x000000c0
 409#define SPR_DCR_CT_LSD      0x000000e0
 410/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
 411
 412/*
 413 * Bit definitions for Debug Mode 1 register
 414 *
 415 */
 416#define SPR_DMR1_CW       0x000fffff  /* Chain register pair data */
 417#define SPR_DMR1_CW0_AND  0x00000001
 418#define SPR_DMR1_CW0_OR   0x00000002
 419#define SPR_DMR1_CW0      (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
 420#define SPR_DMR1_CW1_AND  0x00000004
 421#define SPR_DMR1_CW1_OR   0x00000008
 422#define SPR_DMR1_CW1      (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
 423#define SPR_DMR1_CW2_AND  0x00000010
 424#define SPR_DMR1_CW2_OR   0x00000020
 425#define SPR_DMR1_CW2      (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
 426#define SPR_DMR1_CW3_AND  0x00000040
 427#define SPR_DMR1_CW3_OR   0x00000080
 428#define SPR_DMR1_CW3      (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
 429#define SPR_DMR1_CW4_AND  0x00000100
 430#define SPR_DMR1_CW4_OR   0x00000200
 431#define SPR_DMR1_CW4      (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
 432#define SPR_DMR1_CW5_AND  0x00000400
 433#define SPR_DMR1_CW5_OR   0x00000800
 434#define SPR_DMR1_CW5      (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
 435#define SPR_DMR1_CW6_AND  0x00001000
 436#define SPR_DMR1_CW6_OR   0x00002000
 437#define SPR_DMR1_CW6      (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
 438#define SPR_DMR1_CW7_AND  0x00004000
 439#define SPR_DMR1_CW7_OR   0x00008000
 440#define SPR_DMR1_CW7      (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
 441#define SPR_DMR1_CW8_AND  0x00010000
 442#define SPR_DMR1_CW8_OR   0x00020000
 443#define SPR_DMR1_CW8      (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
 444#define SPR_DMR1_CW9_AND  0x00040000
 445#define SPR_DMR1_CW9_OR   0x00080000
 446#define SPR_DMR1_CW9      (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
 447#define SPR_DMR1_RES1      0x00300000  /* Reserved */
 448#define SPR_DMR1_ST       0x00400000  /* Single-step trace*/
 449#define SPR_DMR1_BT       0x00800000  /* Branch trace */
 450#define SPR_DMR1_RES2     0xff000000  /* Reserved */
 451
 452/*
 453 * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
 454 *
 455 */
 456#define SPR_DMR2_WCE0      0x00000001  /* Watchpoint counter 0 enable */
 457#define SPR_DMR2_WCE1      0x00000002  /* Watchpoint counter 0 enable */
 458#define SPR_DMR2_AWTC      0x00000ffc  /* Assign watchpoints to counters */
 459#define SPR_DMR2_AWTC_OFF           2  /* Bit offset to AWTC field */
 460#define SPR_DMR2_WGB       0x003ff000  /* Watchpoints generating breakpoint */
 461#define SPR_DMR2_WGB_OFF           12  /* Bit offset to WGB field */
 462#define SPR_DMR2_WBS       0xffc00000  /* JPB: Watchpoint status */
 463#define SPR_DMR2_WBS_OFF           22  /* Bit offset to WBS field */
 464
 465/*
 466 * Bit definitions for Debug watchpoint counter registers
 467 *
 468 */
 469#define SPR_DWCR_COUNT      0x0000ffff  /* Count */
 470#define SPR_DWCR_MATCH      0xffff0000  /* Match */
 471#define SPR_DWCR_MATCH_OFF          16  /* Match bit offset */
 472
 473/*
 474 * Bit definitions for Debug stop register
 475 *
 476 */
 477#define SPR_DSR_RSTE    0x00000001  /* Reset exception */
 478#define SPR_DSR_BUSEE   0x00000002  /* Bus error exception */
 479#define SPR_DSR_DPFE    0x00000004  /* Data Page Fault exception */
 480#define SPR_DSR_IPFE    0x00000008  /* Insn Page Fault exception */
 481#define SPR_DSR_TTE     0x00000010  /* Tick Timer exception */
 482#define SPR_DSR_AE      0x00000020  /* Alignment exception */
 483#define SPR_DSR_IIE     0x00000040  /* Illegal Instruction exception */
 484#define SPR_DSR_IE      0x00000080  /* Interrupt exception */
 485#define SPR_DSR_DME     0x00000100  /* DTLB miss exception */
 486#define SPR_DSR_IME     0x00000200  /* ITLB miss exception */
 487#define SPR_DSR_RE      0x00000400  /* Range exception */
 488#define SPR_DSR_SCE     0x00000800  /* System call exception */
 489#define SPR_DSR_FPE     0x00001000  /* Floating Point Exception */
 490#define SPR_DSR_TE      0x00002000  /* Trap exception */
 491
 492/*
 493 * Bit definitions for Debug reason register
 494 *
 495 */
 496#define SPR_DRR_RSTE    0x00000001  /* Reset exception */
 497#define SPR_DRR_BUSEE   0x00000002  /* Bus error exception */
 498#define SPR_DRR_DPFE    0x00000004  /* Data Page Fault exception */
 499#define SPR_DRR_IPFE    0x00000008  /* Insn Page Fault exception */
 500#define SPR_DRR_TTE     0x00000010  /* Tick Timer exception */
 501#define SPR_DRR_AE      0x00000020  /* Alignment exception */
 502#define SPR_DRR_IIE     0x00000040  /* Illegal Instruction exception */
 503#define SPR_DRR_IE      0x00000080  /* Interrupt exception */
 504#define SPR_DRR_DME     0x00000100  /* DTLB miss exception */
 505#define SPR_DRR_IME     0x00000200  /* ITLB miss exception */
 506#define SPR_DRR_RE      0x00000400  /* Range exception */
 507#define SPR_DRR_SCE     0x00000800  /* System call exception */
 508#define SPR_DRR_FPE     0x00001000  /* Floating Point Exception */
 509#define SPR_DRR_TE      0x00002000  /* Trap exception */
 510
 511/*
 512 * Bit definitions for Performance counters mode registers
 513 *
 514 */
 515#define SPR_PCMR_CP     0x00000001  /* Counter present */
 516#define SPR_PCMR_UMRA   0x00000002  /* User mode read access */
 517#define SPR_PCMR_CISM   0x00000004  /* Count in supervisor mode */
 518#define SPR_PCMR_CIUM   0x00000008  /* Count in user mode */
 519#define SPR_PCMR_LA     0x00000010  /* Load access event */
 520#define SPR_PCMR_SA     0x00000020  /* Store access event */
 521#define SPR_PCMR_IF     0x00000040  /* Instruction fetch event*/
 522#define SPR_PCMR_DCM    0x00000080  /* Data cache miss event */
 523#define SPR_PCMR_ICM    0x00000100  /* Insn cache miss event */
 524#define SPR_PCMR_IFS    0x00000200  /* Insn fetch stall event */
 525#define SPR_PCMR_LSUS   0x00000400  /* LSU stall event */
 526#define SPR_PCMR_BS     0x00000800  /* Branch stall event */
 527#define SPR_PCMR_DTLBM  0x00001000  /* DTLB miss event */
 528#define SPR_PCMR_ITLBM  0x00002000  /* ITLB miss event */
 529#define SPR_PCMR_DDS    0x00004000  /* Data dependency stall event */
 530#define SPR_PCMR_WPE    0x03ff8000  /* Watchpoint events */
 531
 532/*
 533 * Bit definitions for the Power management register
 534 *
 535 */
 536#define SPR_PMR_SDF     0x0000000f  /* Slow down factor */
 537#define SPR_PMR_DME     0x00000010  /* Doze mode enable */
 538#define SPR_PMR_SME     0x00000020  /* Sleep mode enable */
 539#define SPR_PMR_DCGE    0x00000040  /* Dynamic clock gating enable */
 540#define SPR_PMR_SUME    0x00000080  /* Suspend mode enable */
 541
 542/*
 543 * Bit definitions for PICMR
 544 *
 545 */
 546#define SPR_PICMR_IUM   0xfffffffc  /* Interrupt unmask */
 547
 548/*
 549 * Bit definitions for PICPR
 550 *
 551 */
 552#define SPR_PICPR_IPRIO 0xfffffffc  /* Interrupt priority */
 553
 554/*
 555 * Bit definitions for PICSR
 556 *
 557 */
 558#define SPR_PICSR_IS    0xffffffff  /* Interrupt status */
 559
 560/*
 561 * Bit definitions for Tick Timer Control Register
 562 *
 563 */
 564
 565#define SPR_TTCR_CNT    0xffffffff  /* Count, time period */
 566#define SPR_TTMR_TP     0x0fffffff  /* Time period */
 567#define SPR_TTMR_IP     0x10000000  /* Interrupt Pending */
 568#define SPR_TTMR_IE     0x20000000  /* Interrupt Enable */
 569#define SPR_TTMR_DI     0x00000000  /* Disabled */
 570#define SPR_TTMR_RT     0x40000000  /* Restart tick */
 571#define SPR_TTMR_SR     0x80000000  /* Single run */
 572#define SPR_TTMR_CR     0xc0000000  /* Continuous run */
 573#define SPR_TTMR_M      0xc0000000  /* Tick mode */
 574
 575/*
 576 * Bit definitions for the FP Control Status Register
 577 *
 578 */
 579#define SPR_FPCSR_FPEE  0x00000001  /* Floating Point Exception Enable */
 580#define SPR_FPCSR_RM    0x00000006  /* Rounding Mode */
 581#define SPR_FPCSR_OVF   0x00000008  /* Overflow Flag */
 582#define SPR_FPCSR_UNF   0x00000010  /* Underflow Flag */
 583#define SPR_FPCSR_SNF   0x00000020  /* SNAN Flag */
 584#define SPR_FPCSR_QNF   0x00000040  /* QNAN Flag */
 585#define SPR_FPCSR_ZF    0x00000080  /* Zero Flag */
 586#define SPR_FPCSR_IXF   0x00000100  /* Inexact Flag */
 587#define SPR_FPCSR_IVF   0x00000200  /* Invalid Flag */
 588#define SPR_FPCSR_INF   0x00000400  /* Infinity Flag */
 589#define SPR_FPCSR_DZF   0x00000800  /* Divide By Zero Flag */
 590#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
 591                        SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF |  \
 592                        SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
 593
 594#define FPCSR_RM_RN (0<<1)
 595#define FPCSR_RM_RZ (1<<1)
 596#define FPCSR_RM_RIP (2<<1)
 597#define FPCSR_RM_RIN (3<<1)
 598
 599/*
 600 * l.nop constants
 601 *
 602 */
 603#define NOP_NOP          0x0000      /* Normal nop instruction */
 604#define NOP_EXIT         0x0001      /* End of simulation */
 605#define NOP_REPORT       0x0002      /* Simple report */
 606/*#define NOP_PRINTF       0x0003       Simprintf instruction (obsolete)*/
 607#define NOP_PUTC         0x0004      /* JPB: Simputc instruction */
 608#define NOP_CNT_RESET    0x0005      /* Reset statistics counters */
 609#define NOP_GET_TICKS    0x0006      /* JPB: Get # ticks running */
 610#define NOP_GET_PS       0x0007      /* JPB: Get picosecs/cycle */
 611#define NOP_REPORT_FIRST 0x0400      /* Report with number */
 612#define NOP_REPORT_LAST  0x03ff      /* Report with number */
 613
 614#endif  /* SPR_DEFS__H */
 615