linux/arch/mips/kernel/asm-offsets.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * asm-offsets.c: Calculate pt_regs and task_struct offsets.
   4 *
   5 * Copyright (C) 1996 David S. Miller
   6 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003 Ralf Baechle
   7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   8 *
   9 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10 * Copyright (C) 2000 MIPS Technologies, Inc.
  11 */
  12#include <linux/compat.h>
  13#include <linux/types.h>
  14#include <linux/sched.h>
  15#include <linux/mm.h>
  16#include <linux/kbuild.h>
  17#include <linux/suspend.h>
  18#include <asm/cpu-info.h>
  19#include <asm/pm.h>
  20#include <asm/ptrace.h>
  21#include <asm/processor.h>
  22#include <asm/smp-cps.h>
  23
  24#include <linux/kvm_host.h>
  25
  26void output_ptreg_defines(void)
  27{
  28        COMMENT("MIPS pt_regs offsets.");
  29        OFFSET(PT_R0, pt_regs, regs[0]);
  30        OFFSET(PT_R1, pt_regs, regs[1]);
  31        OFFSET(PT_R2, pt_regs, regs[2]);
  32        OFFSET(PT_R3, pt_regs, regs[3]);
  33        OFFSET(PT_R4, pt_regs, regs[4]);
  34        OFFSET(PT_R5, pt_regs, regs[5]);
  35        OFFSET(PT_R6, pt_regs, regs[6]);
  36        OFFSET(PT_R7, pt_regs, regs[7]);
  37        OFFSET(PT_R8, pt_regs, regs[8]);
  38        OFFSET(PT_R9, pt_regs, regs[9]);
  39        OFFSET(PT_R10, pt_regs, regs[10]);
  40        OFFSET(PT_R11, pt_regs, regs[11]);
  41        OFFSET(PT_R12, pt_regs, regs[12]);
  42        OFFSET(PT_R13, pt_regs, regs[13]);
  43        OFFSET(PT_R14, pt_regs, regs[14]);
  44        OFFSET(PT_R15, pt_regs, regs[15]);
  45        OFFSET(PT_R16, pt_regs, regs[16]);
  46        OFFSET(PT_R17, pt_regs, regs[17]);
  47        OFFSET(PT_R18, pt_regs, regs[18]);
  48        OFFSET(PT_R19, pt_regs, regs[19]);
  49        OFFSET(PT_R20, pt_regs, regs[20]);
  50        OFFSET(PT_R21, pt_regs, regs[21]);
  51        OFFSET(PT_R22, pt_regs, regs[22]);
  52        OFFSET(PT_R23, pt_regs, regs[23]);
  53        OFFSET(PT_R24, pt_regs, regs[24]);
  54        OFFSET(PT_R25, pt_regs, regs[25]);
  55        OFFSET(PT_R26, pt_regs, regs[26]);
  56        OFFSET(PT_R27, pt_regs, regs[27]);
  57        OFFSET(PT_R28, pt_regs, regs[28]);
  58        OFFSET(PT_R29, pt_regs, regs[29]);
  59        OFFSET(PT_R30, pt_regs, regs[30]);
  60        OFFSET(PT_R31, pt_regs, regs[31]);
  61        OFFSET(PT_LO, pt_regs, lo);
  62        OFFSET(PT_HI, pt_regs, hi);
  63#ifdef CONFIG_CPU_HAS_SMARTMIPS
  64        OFFSET(PT_ACX, pt_regs, acx);
  65#endif
  66        OFFSET(PT_EPC, pt_regs, cp0_epc);
  67        OFFSET(PT_BVADDR, pt_regs, cp0_badvaddr);
  68        OFFSET(PT_STATUS, pt_regs, cp0_status);
  69        OFFSET(PT_CAUSE, pt_regs, cp0_cause);
  70#ifdef CONFIG_CPU_CAVIUM_OCTEON
  71        OFFSET(PT_MPL, pt_regs, mpl);
  72        OFFSET(PT_MTP, pt_regs, mtp);
  73#endif /* CONFIG_CPU_CAVIUM_OCTEON */
  74        DEFINE(PT_SIZE, sizeof(struct pt_regs));
  75        BLANK();
  76}
  77
  78void output_task_defines(void)
  79{
  80        COMMENT("MIPS task_struct offsets.");
  81        OFFSET(TASK_THREAD_INFO, task_struct, stack);
  82        OFFSET(TASK_FLAGS, task_struct, flags);
  83        OFFSET(TASK_MM, task_struct, mm);
  84        OFFSET(TASK_PID, task_struct, pid);
  85#if defined(CONFIG_STACKPROTECTOR)
  86        OFFSET(TASK_STACK_CANARY, task_struct, stack_canary);
  87#endif
  88        DEFINE(TASK_STRUCT_SIZE, sizeof(struct task_struct));
  89        BLANK();
  90}
  91
  92void output_thread_info_defines(void)
  93{
  94        COMMENT("MIPS thread_info offsets.");
  95        OFFSET(TI_TASK, thread_info, task);
  96        OFFSET(TI_FLAGS, thread_info, flags);
  97        OFFSET(TI_TP_VALUE, thread_info, tp_value);
  98        OFFSET(TI_CPU, thread_info, cpu);
  99        OFFSET(TI_PRE_COUNT, thread_info, preempt_count);
 100        OFFSET(TI_REGS, thread_info, regs);
 101        DEFINE(_THREAD_SIZE, THREAD_SIZE);
 102        DEFINE(_THREAD_MASK, THREAD_MASK);
 103        DEFINE(_IRQ_STACK_SIZE, IRQ_STACK_SIZE);
 104        DEFINE(_IRQ_STACK_START, IRQ_STACK_START);
 105        BLANK();
 106}
 107
 108void output_thread_defines(void)
 109{
 110        COMMENT("MIPS specific thread_struct offsets.");
 111        OFFSET(THREAD_REG16, task_struct, thread.reg16);
 112        OFFSET(THREAD_REG17, task_struct, thread.reg17);
 113        OFFSET(THREAD_REG18, task_struct, thread.reg18);
 114        OFFSET(THREAD_REG19, task_struct, thread.reg19);
 115        OFFSET(THREAD_REG20, task_struct, thread.reg20);
 116        OFFSET(THREAD_REG21, task_struct, thread.reg21);
 117        OFFSET(THREAD_REG22, task_struct, thread.reg22);
 118        OFFSET(THREAD_REG23, task_struct, thread.reg23);
 119        OFFSET(THREAD_REG29, task_struct, thread.reg29);
 120        OFFSET(THREAD_REG30, task_struct, thread.reg30);
 121        OFFSET(THREAD_REG31, task_struct, thread.reg31);
 122        OFFSET(THREAD_STATUS, task_struct,
 123               thread.cp0_status);
 124
 125        OFFSET(THREAD_BVADDR, task_struct, \
 126               thread.cp0_badvaddr);
 127        OFFSET(THREAD_BUADDR, task_struct, \
 128               thread.cp0_baduaddr);
 129        OFFSET(THREAD_ECODE, task_struct, \
 130               thread.error_code);
 131        OFFSET(THREAD_TRAPNO, task_struct, thread.trap_nr);
 132        BLANK();
 133}
 134
 135#ifdef CONFIG_MIPS_FP_SUPPORT
 136void output_thread_fpu_defines(void)
 137{
 138        OFFSET(THREAD_FPU, task_struct, thread.fpu);
 139
 140        OFFSET(THREAD_FPR0, task_struct, thread.fpu.fpr[0]);
 141        OFFSET(THREAD_FPR1, task_struct, thread.fpu.fpr[1]);
 142        OFFSET(THREAD_FPR2, task_struct, thread.fpu.fpr[2]);
 143        OFFSET(THREAD_FPR3, task_struct, thread.fpu.fpr[3]);
 144        OFFSET(THREAD_FPR4, task_struct, thread.fpu.fpr[4]);
 145        OFFSET(THREAD_FPR5, task_struct, thread.fpu.fpr[5]);
 146        OFFSET(THREAD_FPR6, task_struct, thread.fpu.fpr[6]);
 147        OFFSET(THREAD_FPR7, task_struct, thread.fpu.fpr[7]);
 148        OFFSET(THREAD_FPR8, task_struct, thread.fpu.fpr[8]);
 149        OFFSET(THREAD_FPR9, task_struct, thread.fpu.fpr[9]);
 150        OFFSET(THREAD_FPR10, task_struct, thread.fpu.fpr[10]);
 151        OFFSET(THREAD_FPR11, task_struct, thread.fpu.fpr[11]);
 152        OFFSET(THREAD_FPR12, task_struct, thread.fpu.fpr[12]);
 153        OFFSET(THREAD_FPR13, task_struct, thread.fpu.fpr[13]);
 154        OFFSET(THREAD_FPR14, task_struct, thread.fpu.fpr[14]);
 155        OFFSET(THREAD_FPR15, task_struct, thread.fpu.fpr[15]);
 156        OFFSET(THREAD_FPR16, task_struct, thread.fpu.fpr[16]);
 157        OFFSET(THREAD_FPR17, task_struct, thread.fpu.fpr[17]);
 158        OFFSET(THREAD_FPR18, task_struct, thread.fpu.fpr[18]);
 159        OFFSET(THREAD_FPR19, task_struct, thread.fpu.fpr[19]);
 160        OFFSET(THREAD_FPR20, task_struct, thread.fpu.fpr[20]);
 161        OFFSET(THREAD_FPR21, task_struct, thread.fpu.fpr[21]);
 162        OFFSET(THREAD_FPR22, task_struct, thread.fpu.fpr[22]);
 163        OFFSET(THREAD_FPR23, task_struct, thread.fpu.fpr[23]);
 164        OFFSET(THREAD_FPR24, task_struct, thread.fpu.fpr[24]);
 165        OFFSET(THREAD_FPR25, task_struct, thread.fpu.fpr[25]);
 166        OFFSET(THREAD_FPR26, task_struct, thread.fpu.fpr[26]);
 167        OFFSET(THREAD_FPR27, task_struct, thread.fpu.fpr[27]);
 168        OFFSET(THREAD_FPR28, task_struct, thread.fpu.fpr[28]);
 169        OFFSET(THREAD_FPR29, task_struct, thread.fpu.fpr[29]);
 170        OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]);
 171        OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]);
 172
 173        OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31);
 174        OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr);
 175        BLANK();
 176}
 177#endif
 178
 179void output_mm_defines(void)
 180{
 181        COMMENT("Size of struct page");
 182        DEFINE(STRUCT_PAGE_SIZE, sizeof(struct page));
 183        BLANK();
 184        COMMENT("Linux mm_struct offsets.");
 185        OFFSET(MM_USERS, mm_struct, mm_users);
 186        OFFSET(MM_PGD, mm_struct, pgd);
 187        OFFSET(MM_CONTEXT, mm_struct, context);
 188        BLANK();
 189        DEFINE(_PGD_T_SIZE, sizeof(pgd_t));
 190        DEFINE(_PMD_T_SIZE, sizeof(pmd_t));
 191        DEFINE(_PTE_T_SIZE, sizeof(pte_t));
 192        BLANK();
 193        DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
 194#ifndef __PAGETABLE_PMD_FOLDED
 195        DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
 196#endif
 197        DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
 198        BLANK();
 199        DEFINE(_PGD_ORDER, PGD_ORDER);
 200#ifndef __PAGETABLE_PMD_FOLDED
 201        DEFINE(_PMD_ORDER, PMD_ORDER);
 202#endif
 203        DEFINE(_PTE_ORDER, PTE_ORDER);
 204        BLANK();
 205        DEFINE(_PMD_SHIFT, PMD_SHIFT);
 206        DEFINE(_PGDIR_SHIFT, PGDIR_SHIFT);
 207        BLANK();
 208        DEFINE(_PTRS_PER_PGD, PTRS_PER_PGD);
 209        DEFINE(_PTRS_PER_PMD, PTRS_PER_PMD);
 210        DEFINE(_PTRS_PER_PTE, PTRS_PER_PTE);
 211        BLANK();
 212        DEFINE(_PAGE_SHIFT, PAGE_SHIFT);
 213        DEFINE(_PAGE_SIZE, PAGE_SIZE);
 214        BLANK();
 215}
 216
 217#ifdef CONFIG_32BIT
 218void output_sc_defines(void)
 219{
 220        COMMENT("Linux sigcontext offsets.");
 221        OFFSET(SC_REGS, sigcontext, sc_regs);
 222        OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
 223        OFFSET(SC_ACX, sigcontext, sc_acx);
 224        OFFSET(SC_MDHI, sigcontext, sc_mdhi);
 225        OFFSET(SC_MDLO, sigcontext, sc_mdlo);
 226        OFFSET(SC_PC, sigcontext, sc_pc);
 227        OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
 228        OFFSET(SC_FPC_EIR, sigcontext, sc_fpc_eir);
 229        OFFSET(SC_HI1, sigcontext, sc_hi1);
 230        OFFSET(SC_LO1, sigcontext, sc_lo1);
 231        OFFSET(SC_HI2, sigcontext, sc_hi2);
 232        OFFSET(SC_LO2, sigcontext, sc_lo2);
 233        OFFSET(SC_HI3, sigcontext, sc_hi3);
 234        OFFSET(SC_LO3, sigcontext, sc_lo3);
 235        BLANK();
 236}
 237#endif
 238
 239#ifdef CONFIG_64BIT
 240void output_sc_defines(void)
 241{
 242        COMMENT("Linux sigcontext offsets.");
 243        OFFSET(SC_REGS, sigcontext, sc_regs);
 244        OFFSET(SC_FPREGS, sigcontext, sc_fpregs);
 245        OFFSET(SC_MDHI, sigcontext, sc_mdhi);
 246        OFFSET(SC_MDLO, sigcontext, sc_mdlo);
 247        OFFSET(SC_PC, sigcontext, sc_pc);
 248        OFFSET(SC_FPC_CSR, sigcontext, sc_fpc_csr);
 249        BLANK();
 250}
 251#endif
 252
 253void output_signal_defined(void)
 254{
 255        COMMENT("Linux signal numbers.");
 256        DEFINE(_SIGHUP, SIGHUP);
 257        DEFINE(_SIGINT, SIGINT);
 258        DEFINE(_SIGQUIT, SIGQUIT);
 259        DEFINE(_SIGILL, SIGILL);
 260        DEFINE(_SIGTRAP, SIGTRAP);
 261        DEFINE(_SIGIOT, SIGIOT);
 262        DEFINE(_SIGABRT, SIGABRT);
 263        DEFINE(_SIGEMT, SIGEMT);
 264        DEFINE(_SIGFPE, SIGFPE);
 265        DEFINE(_SIGKILL, SIGKILL);
 266        DEFINE(_SIGBUS, SIGBUS);
 267        DEFINE(_SIGSEGV, SIGSEGV);
 268        DEFINE(_SIGSYS, SIGSYS);
 269        DEFINE(_SIGPIPE, SIGPIPE);
 270        DEFINE(_SIGALRM, SIGALRM);
 271        DEFINE(_SIGTERM, SIGTERM);
 272        DEFINE(_SIGUSR1, SIGUSR1);
 273        DEFINE(_SIGUSR2, SIGUSR2);
 274        DEFINE(_SIGCHLD, SIGCHLD);
 275        DEFINE(_SIGPWR, SIGPWR);
 276        DEFINE(_SIGWINCH, SIGWINCH);
 277        DEFINE(_SIGURG, SIGURG);
 278        DEFINE(_SIGIO, SIGIO);
 279        DEFINE(_SIGSTOP, SIGSTOP);
 280        DEFINE(_SIGTSTP, SIGTSTP);
 281        DEFINE(_SIGCONT, SIGCONT);
 282        DEFINE(_SIGTTIN, SIGTTIN);
 283        DEFINE(_SIGTTOU, SIGTTOU);
 284        DEFINE(_SIGVTALRM, SIGVTALRM);
 285        DEFINE(_SIGPROF, SIGPROF);
 286        DEFINE(_SIGXCPU, SIGXCPU);
 287        DEFINE(_SIGXFSZ, SIGXFSZ);
 288        BLANK();
 289}
 290
 291#ifdef CONFIG_CPU_CAVIUM_OCTEON
 292void output_octeon_cop2_state_defines(void)
 293{
 294        COMMENT("Octeon specific octeon_cop2_state offsets.");
 295        OFFSET(OCTEON_CP2_CRC_IV,       octeon_cop2_state, cop2_crc_iv);
 296        OFFSET(OCTEON_CP2_CRC_LENGTH,   octeon_cop2_state, cop2_crc_length);
 297        OFFSET(OCTEON_CP2_CRC_POLY,     octeon_cop2_state, cop2_crc_poly);
 298        OFFSET(OCTEON_CP2_LLM_DAT,      octeon_cop2_state, cop2_llm_dat);
 299        OFFSET(OCTEON_CP2_3DES_IV,      octeon_cop2_state, cop2_3des_iv);
 300        OFFSET(OCTEON_CP2_3DES_KEY,     octeon_cop2_state, cop2_3des_key);
 301        OFFSET(OCTEON_CP2_3DES_RESULT,  octeon_cop2_state, cop2_3des_result);
 302        OFFSET(OCTEON_CP2_AES_INP0,     octeon_cop2_state, cop2_aes_inp0);
 303        OFFSET(OCTEON_CP2_AES_IV,       octeon_cop2_state, cop2_aes_iv);
 304        OFFSET(OCTEON_CP2_AES_KEY,      octeon_cop2_state, cop2_aes_key);
 305        OFFSET(OCTEON_CP2_AES_KEYLEN,   octeon_cop2_state, cop2_aes_keylen);
 306        OFFSET(OCTEON_CP2_AES_RESULT,   octeon_cop2_state, cop2_aes_result);
 307        OFFSET(OCTEON_CP2_GFM_MULT,     octeon_cop2_state, cop2_gfm_mult);
 308        OFFSET(OCTEON_CP2_GFM_POLY,     octeon_cop2_state, cop2_gfm_poly);
 309        OFFSET(OCTEON_CP2_GFM_RESULT,   octeon_cop2_state, cop2_gfm_result);
 310        OFFSET(OCTEON_CP2_HSH_DATW,     octeon_cop2_state, cop2_hsh_datw);
 311        OFFSET(OCTEON_CP2_HSH_IVW,      octeon_cop2_state, cop2_hsh_ivw);
 312        OFFSET(OCTEON_CP2_SHA3,         octeon_cop2_state, cop2_sha3);
 313        OFFSET(THREAD_CP2,      task_struct, thread.cp2);
 314        OFFSET(THREAD_CVMSEG,   task_struct, thread.cvmseg.cvmseg);
 315        BLANK();
 316}
 317#endif
 318
 319#ifdef CONFIG_HIBERNATION
 320void output_pbe_defines(void)
 321{
 322        COMMENT(" Linux struct pbe offsets. ");
 323        OFFSET(PBE_ADDRESS, pbe, address);
 324        OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
 325        OFFSET(PBE_NEXT, pbe, next);
 326        DEFINE(PBE_SIZE, sizeof(struct pbe));
 327        BLANK();
 328}
 329#endif
 330
 331#ifdef CONFIG_CPU_PM
 332void output_pm_defines(void)
 333{
 334        COMMENT(" PM offsets. ");
 335#ifdef CONFIG_EVA
 336        OFFSET(SSS_SEGCTL0,     mips_static_suspend_state, segctl[0]);
 337        OFFSET(SSS_SEGCTL1,     mips_static_suspend_state, segctl[1]);
 338        OFFSET(SSS_SEGCTL2,     mips_static_suspend_state, segctl[2]);
 339#endif
 340        OFFSET(SSS_SP,          mips_static_suspend_state, sp);
 341        BLANK();
 342}
 343#endif
 344
 345#ifdef CONFIG_MIPS_FP_SUPPORT
 346void output_kvm_defines(void)
 347{
 348        COMMENT(" KVM/MIPS Specific offsets. ");
 349
 350        OFFSET(VCPU_FPR0, kvm_vcpu_arch, fpu.fpr[0]);
 351        OFFSET(VCPU_FPR1, kvm_vcpu_arch, fpu.fpr[1]);
 352        OFFSET(VCPU_FPR2, kvm_vcpu_arch, fpu.fpr[2]);
 353        OFFSET(VCPU_FPR3, kvm_vcpu_arch, fpu.fpr[3]);
 354        OFFSET(VCPU_FPR4, kvm_vcpu_arch, fpu.fpr[4]);
 355        OFFSET(VCPU_FPR5, kvm_vcpu_arch, fpu.fpr[5]);
 356        OFFSET(VCPU_FPR6, kvm_vcpu_arch, fpu.fpr[6]);
 357        OFFSET(VCPU_FPR7, kvm_vcpu_arch, fpu.fpr[7]);
 358        OFFSET(VCPU_FPR8, kvm_vcpu_arch, fpu.fpr[8]);
 359        OFFSET(VCPU_FPR9, kvm_vcpu_arch, fpu.fpr[9]);
 360        OFFSET(VCPU_FPR10, kvm_vcpu_arch, fpu.fpr[10]);
 361        OFFSET(VCPU_FPR11, kvm_vcpu_arch, fpu.fpr[11]);
 362        OFFSET(VCPU_FPR12, kvm_vcpu_arch, fpu.fpr[12]);
 363        OFFSET(VCPU_FPR13, kvm_vcpu_arch, fpu.fpr[13]);
 364        OFFSET(VCPU_FPR14, kvm_vcpu_arch, fpu.fpr[14]);
 365        OFFSET(VCPU_FPR15, kvm_vcpu_arch, fpu.fpr[15]);
 366        OFFSET(VCPU_FPR16, kvm_vcpu_arch, fpu.fpr[16]);
 367        OFFSET(VCPU_FPR17, kvm_vcpu_arch, fpu.fpr[17]);
 368        OFFSET(VCPU_FPR18, kvm_vcpu_arch, fpu.fpr[18]);
 369        OFFSET(VCPU_FPR19, kvm_vcpu_arch, fpu.fpr[19]);
 370        OFFSET(VCPU_FPR20, kvm_vcpu_arch, fpu.fpr[20]);
 371        OFFSET(VCPU_FPR21, kvm_vcpu_arch, fpu.fpr[21]);
 372        OFFSET(VCPU_FPR22, kvm_vcpu_arch, fpu.fpr[22]);
 373        OFFSET(VCPU_FPR23, kvm_vcpu_arch, fpu.fpr[23]);
 374        OFFSET(VCPU_FPR24, kvm_vcpu_arch, fpu.fpr[24]);
 375        OFFSET(VCPU_FPR25, kvm_vcpu_arch, fpu.fpr[25]);
 376        OFFSET(VCPU_FPR26, kvm_vcpu_arch, fpu.fpr[26]);
 377        OFFSET(VCPU_FPR27, kvm_vcpu_arch, fpu.fpr[27]);
 378        OFFSET(VCPU_FPR28, kvm_vcpu_arch, fpu.fpr[28]);
 379        OFFSET(VCPU_FPR29, kvm_vcpu_arch, fpu.fpr[29]);
 380        OFFSET(VCPU_FPR30, kvm_vcpu_arch, fpu.fpr[30]);
 381        OFFSET(VCPU_FPR31, kvm_vcpu_arch, fpu.fpr[31]);
 382
 383        OFFSET(VCPU_FCR31, kvm_vcpu_arch, fpu.fcr31);
 384        OFFSET(VCPU_MSA_CSR, kvm_vcpu_arch, fpu.msacsr);
 385        BLANK();
 386}
 387#endif
 388
 389#ifdef CONFIG_MIPS_CPS
 390void output_cps_defines(void)
 391{
 392        COMMENT(" MIPS CPS offsets. ");
 393
 394        OFFSET(COREBOOTCFG_VPEMASK, core_boot_config, vpe_mask);
 395        OFFSET(COREBOOTCFG_VPECONFIG, core_boot_config, vpe_config);
 396        DEFINE(COREBOOTCFG_SIZE, sizeof(struct core_boot_config));
 397
 398        OFFSET(VPEBOOTCFG_PC, vpe_boot_config, pc);
 399        OFFSET(VPEBOOTCFG_SP, vpe_boot_config, sp);
 400        OFFSET(VPEBOOTCFG_GP, vpe_boot_config, gp);
 401        DEFINE(VPEBOOTCFG_SIZE, sizeof(struct vpe_boot_config));
 402}
 403#endif
 404