linux/arch/mips/include/asm/octeon/cvmx-pko.h
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   1/***********************license start***************
   2 * Author: Cavium Networks
   3 *
   4 * Contact: support@caviumnetworks.com
   5 * This file is part of the OCTEON SDK
   6 *
   7 * Copyright (c) 2003-2008 Cavium Networks
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this file; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22 * or visit http://www.gnu.org/licenses/.
  23 *
  24 * This file may also be available under a different license from Cavium.
  25 * Contact Cavium Networks for more information
  26 ***********************license end**************************************/
  27
  28/**
  29 *
  30 * Interface to the hardware Packet Output unit.
  31 *
  32 * Starting with SDK 1.7.0, the PKO output functions now support
  33 * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
  34 * function similarly to previous SDKs by using POW atomic tags
  35 * to preserve ordering and exclusivity. As a new option, you
  36 * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
  37 * memory based locking instead. This locking has the advantage
  38 * of not affecting the tag state but doesn't preserve packet
  39 * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
  40 * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
  41 * with hand tuned fast path code.
  42 *
  43 * Some of other SDK differences visible to the command queuing:
  44 * - PKO indexes are no longer stored in the FAU. A large
  45 *   percentage of the FAU register block used to be tied up
  46 *   maintaining PKO queue pointers. These are now stored in a
  47 *   global named block.
  48 * - The PKO <b>use_locking</b> parameter can now have a global
  49 *   effect. Since all application use the same named block,
  50 *   queue locking correctly applies across all operating
  51 *   systems when using CVMX_PKO_LOCK_CMD_QUEUE.
  52 * - PKO 3 word commands are now supported. Use
  53 *   cvmx_pko_send_packet_finish3().
  54 *
  55 */
  56
  57#ifndef __CVMX_PKO_H__
  58#define __CVMX_PKO_H__
  59
  60#include <asm/octeon/cvmx-fpa.h>
  61#include <asm/octeon/cvmx-pow.h>
  62#include <asm/octeon/cvmx-cmd-queue.h>
  63#include <asm/octeon/cvmx-pko-defs.h>
  64
  65/* Adjust the command buffer size by 1 word so that in the case of using only
  66 * two word PKO commands no command words stradle buffers.  The useful values
  67 * for this are 0 and 1. */
  68#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
  69
  70#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
  71#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
  72        OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
  73        OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
  74                (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
  75                OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
  76#define CVMX_PKO_NUM_OUTPUT_PORTS       40
  77/* use this for queues that are not used */
  78#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
  79#define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
  80#define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
  81#define CVMX_PKO_MAX_QUEUE_DEPTH 0
  82
  83typedef enum {
  84        CVMX_PKO_SUCCESS,
  85        CVMX_PKO_INVALID_PORT,
  86        CVMX_PKO_INVALID_QUEUE,
  87        CVMX_PKO_INVALID_PRIORITY,
  88        CVMX_PKO_NO_MEMORY,
  89        CVMX_PKO_PORT_ALREADY_SETUP,
  90        CVMX_PKO_CMD_QUEUE_INIT_ERROR
  91} cvmx_pko_status_t;
  92
  93/**
  94 * This enumeration represents the differnet locking modes supported by PKO.
  95 */
  96typedef enum {
  97        /*
  98         * PKO doesn't do any locking. It is the responsibility of the
  99         * application to make sure that no other core is accessing
 100         * the same queue at the same time
 101         */
 102        CVMX_PKO_LOCK_NONE = 0,
 103        /*
 104         * PKO performs an atomic tagswitch to insure exclusive access
 105         * to the output queue. This will maintain packet ordering on
 106         * output.
 107         */
 108        CVMX_PKO_LOCK_ATOMIC_TAG = 1,
 109        /*
 110         * PKO uses the common command queue locks to insure exclusive
 111         * access to the output queue. This is a memory based
 112         * ll/sc. This is the most portable locking mechanism.
 113         */
 114        CVMX_PKO_LOCK_CMD_QUEUE = 2,
 115} cvmx_pko_lock_t;
 116
 117typedef struct {
 118        uint32_t packets;
 119        uint64_t octets;
 120        uint64_t doorbell;
 121} cvmx_pko_port_status_t;
 122
 123/**
 124 * This structure defines the address to use on a packet enqueue
 125 */
 126typedef union {
 127        uint64_t u64;
 128        struct {
 129#ifdef __BIG_ENDIAN_BITFIELD
 130                /* Must CVMX_IO_SEG */
 131                uint64_t mem_space:2;
 132                /* Must be zero */
 133                uint64_t reserved:13;
 134                /* Must be one */
 135                uint64_t is_io:1;
 136                /* The ID of the device on the non-coherent bus */
 137                uint64_t did:8;
 138                /* Must be zero */
 139                uint64_t reserved2:4;
 140                /* Must be zero */
 141                uint64_t reserved3:18;
 142                /*
 143                 * The hardware likes to have the output port in
 144                 * addition to the output queue,
 145                 */
 146                uint64_t port:6;
 147                /*
 148                 * The output queue to send the packet to (0-127 are
 149                 * legal)
 150                 */
 151                uint64_t queue:9;
 152                /* Must be zero */
 153                uint64_t reserved4:3;
 154#else
 155                uint64_t reserved4:3;
 156                uint64_t queue:9;
 157                uint64_t port:9;
 158                uint64_t reserved3:15;
 159                uint64_t reserved2:4;
 160                uint64_t did:8;
 161                uint64_t is_io:1;
 162                uint64_t reserved:13;
 163                uint64_t mem_space:2;
 164#endif
 165        } s;
 166} cvmx_pko_doorbell_address_t;
 167
 168/**
 169 * Structure of the first packet output command word.
 170 */
 171union cvmx_pko_command_word0 {
 172        uint64_t u64;
 173        struct {
 174#ifdef __BIG_ENDIAN_BITFIELD
 175                /*
 176                 * The size of the reg1 operation - could be 8, 16,
 177                 * 32, or 64 bits.
 178                 */
 179                uint64_t size1:2;
 180                /*
 181                 * The size of the reg0 operation - could be 8, 16,
 182                 * 32, or 64 bits.
 183                 */
 184                uint64_t size0:2;
 185                /*
 186                 * If set, subtract 1, if clear, subtract packet
 187                 * size.
 188                 */
 189                uint64_t subone1:1;
 190                /*
 191                 * The register, subtract will be done if reg1 is
 192                 * non-zero.
 193                 */
 194                uint64_t reg1:11;
 195                /* If set, subtract 1, if clear, subtract packet size */
 196                uint64_t subone0:1;
 197                /* The register, subtract will be done if reg0 is non-zero */
 198                uint64_t reg0:11;
 199                /*
 200                 * When set, interpret segment pointer and segment
 201                 * bytes in little endian order.
 202                 */
 203                uint64_t le:1;
 204                /*
 205                 * When set, packet data not allocated in L2 cache by
 206                 * PKO.
 207                 */
 208                uint64_t n2:1;
 209                /*
 210                 * If set and rsp is set, word3 contains a pointer to
 211                 * a work queue entry.
 212                 */
 213                uint64_t wqp:1;
 214                /* If set, the hardware will send a response when done */
 215                uint64_t rsp:1;
 216                /*
 217                 * If set, the supplied pkt_ptr is really a pointer to
 218                 * a list of pkt_ptr's.
 219                 */
 220                uint64_t gather:1;
 221                /*
 222                 * If ipoffp1 is non zero, (ipoffp1-1) is the number
 223                 * of bytes to IP header, and the hardware will
 224                 * calculate and insert the UDP/TCP checksum.
 225                 */
 226                uint64_t ipoffp1:7;
 227                /*
 228                 * If set, ignore the I bit (force to zero) from all
 229                 * pointer structures.
 230                 */
 231                uint64_t ignore_i:1;
 232                /*
 233                 * If clear, the hardware will attempt to free the
 234                 * buffers containing the packet.
 235                 */
 236                uint64_t dontfree:1;
 237                /*
 238                 * The total number of segs in the packet, if gather
 239                 * set, also gather list length.
 240                 */
 241                uint64_t segs:6;
 242                /* Including L2, but no trailing CRC */
 243                uint64_t total_bytes:16;
 244#else
 245                uint64_t total_bytes:16;
 246                uint64_t segs:6;
 247                uint64_t dontfree:1;
 248                uint64_t ignore_i:1;
 249                uint64_t ipoffp1:7;
 250                uint64_t gather:1;
 251                uint64_t rsp:1;
 252                uint64_t wqp:1;
 253                uint64_t n2:1;
 254                uint64_t le:1;
 255                uint64_t reg0:11;
 256                uint64_t subone0:1;
 257                uint64_t reg1:11;
 258                uint64_t subone1:1;
 259                uint64_t size0:2;
 260                uint64_t size1:2;
 261#endif
 262        } s;
 263};
 264
 265/* CSR typedefs have been moved to cvmx-csr-*.h */
 266
 267/**
 268 * Definition of internal state for Packet output processing
 269 */
 270typedef struct {
 271        /* ptr to start of buffer, offset kept in FAU reg */
 272        uint64_t *start_ptr;
 273} cvmx_pko_state_elem_t;
 274
 275/**
 276 * Call before any other calls to initialize the packet
 277 * output system.
 278 */
 279extern void cvmx_pko_initialize_global(void);
 280extern int cvmx_pko_initialize_local(void);
 281
 282/**
 283 * Enables the packet output hardware. It must already be
 284 * configured.
 285 */
 286extern void cvmx_pko_enable(void);
 287
 288/**
 289 * Disables the packet output. Does not affect any configuration.
 290 */
 291extern void cvmx_pko_disable(void);
 292
 293/**
 294 * Shutdown and free resources required by packet output.
 295 */
 296
 297extern void cvmx_pko_shutdown(void);
 298
 299/**
 300 * Configure a output port and the associated queues for use.
 301 *
 302 * @port:       Port to configure.
 303 * @base_queue: First queue number to associate with this port.
 304 * @num_queues: Number of queues t oassociate with this port
 305 * @priority:   Array of priority levels for each queue. Values are
 306 *                   allowed to be 1-8. A value of 8 get 8 times the traffic
 307 *                   of a value of 1. There must be num_queues elements in the
 308 *                   array.
 309 */
 310extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
 311                                              uint64_t base_queue,
 312                                              uint64_t num_queues,
 313                                              const uint64_t priority[]);
 314
 315/**
 316 * Ring the packet output doorbell. This tells the packet
 317 * output hardware that "len" command words have been added
 318 * to its pending list.  This command includes the required
 319 * CVMX_SYNCWS before the doorbell ring.
 320 *
 321 * @port:   Port the packet is for
 322 * @queue:  Queue the packet is for
 323 * @len:    Length of the command in 64 bit words
 324 */
 325static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
 326                                     uint64_t len)
 327{
 328        cvmx_pko_doorbell_address_t ptr;
 329
 330        ptr.u64 = 0;
 331        ptr.s.mem_space = CVMX_IO_SEG;
 332        ptr.s.did = CVMX_OCT_DID_PKT_SEND;
 333        ptr.s.is_io = 1;
 334        ptr.s.port = port;
 335        ptr.s.queue = queue;
 336        /*
 337         * Need to make sure output queue data is in DRAM before
 338         * doorbell write.
 339         */
 340        CVMX_SYNCWS;
 341        cvmx_write_io(ptr.u64, len);
 342}
 343
 344/**
 345 * Prepare to send a packet.  This may initiate a tag switch to
 346 * get exclusive access to the output queue structure, and
 347 * performs other prep work for the packet send operation.
 348 *
 349 * cvmx_pko_send_packet_finish() MUST be called after this function is called,
 350 * and must be called with the same port/queue/use_locking arguments.
 351 *
 352 * The use_locking parameter allows the caller to use three
 353 * possible locking modes.
 354 * - CVMX_PKO_LOCK_NONE
 355 *      - PKO doesn't do any locking. It is the responsibility
 356 *          of the application to make sure that no other core
 357 *          is accessing the same queue at the same time.
 358 * - CVMX_PKO_LOCK_ATOMIC_TAG
 359 *      - PKO performs an atomic tagswitch to insure exclusive
 360 *          access to the output queue. This will maintain
 361 *          packet ordering on output.
 362 * - CVMX_PKO_LOCK_CMD_QUEUE
 363 *      - PKO uses the common command queue locks to insure
 364 *          exclusive access to the output queue. This is a
 365 *          memory based ll/sc. This is the most portable
 366 *          locking mechanism.
 367 *
 368 * NOTE: If atomic locking is used, the POW entry CANNOT be
 369 * descheduled, as it does not contain a valid WQE pointer.
 370 *
 371 * @port:   Port to send it on
 372 * @queue:  Queue to use
 373 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
 374 *               CVMX_PKO_LOCK_CMD_QUEUE
 375 */
 376
 377static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
 378                                                cvmx_pko_lock_t use_locking)
 379{
 380        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
 381                /*
 382                 * Must do a full switch here to handle all cases.  We
 383                 * use a fake WQE pointer, as the POW does not access
 384                 * this memory.  The WQE pointer and group are only
 385                 * used if this work is descheduled, which is not
 386                 * supported by the
 387                 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
 388                 * combination.  Note that this is a special case in
 389                 * which these fake values can be used - this is not a
 390                 * general technique.
 391                 */
 392                uint32_t tag =
 393                    CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
 394                    CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
 395                    (CVMX_TAG_SUBGROUP_MASK & queue);
 396                cvmx_pow_tag_sw_full((struct cvmx_wqe *) cvmx_phys_to_ptr(0x80), tag,
 397                                     CVMX_POW_TAG_TYPE_ATOMIC, 0);
 398        }
 399}
 400
 401/**
 402 * Complete packet output. cvmx_pko_send_packet_prepare() must be
 403 * called exactly once before this, and the same parameters must be
 404 * passed to both cvmx_pko_send_packet_prepare() and
 405 * cvmx_pko_send_packet_finish().
 406 *
 407 * @port:   Port to send it on
 408 * @queue:  Queue to use
 409 * @pko_command:
 410 *               PKO HW command word
 411 * @packet: Packet to send
 412 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
 413 *               CVMX_PKO_LOCK_CMD_QUEUE
 414 *
 415 * Returns: CVMX_PKO_SUCCESS on success, or error code on
 416 * failure of output
 417 */
 418static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
 419        uint64_t port,
 420        uint64_t queue,
 421        union cvmx_pko_command_word0 pko_command,
 422        union cvmx_buf_ptr packet,
 423        cvmx_pko_lock_t use_locking)
 424{
 425        cvmx_cmd_queue_result_t result;
 426        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
 427                cvmx_pow_tag_sw_wait();
 428        result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
 429                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
 430                                       pko_command.u64, packet.u64);
 431        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
 432                cvmx_pko_doorbell(port, queue, 2);
 433                return CVMX_PKO_SUCCESS;
 434        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
 435                   || (result == CVMX_CMD_QUEUE_FULL)) {
 436                return CVMX_PKO_NO_MEMORY;
 437        } else {
 438                return CVMX_PKO_INVALID_QUEUE;
 439        }
 440}
 441
 442/**
 443 * Complete packet output. cvmx_pko_send_packet_prepare() must be
 444 * called exactly once before this, and the same parameters must be
 445 * passed to both cvmx_pko_send_packet_prepare() and
 446 * cvmx_pko_send_packet_finish().
 447 *
 448 * @port:   Port to send it on
 449 * @queue:  Queue to use
 450 * @pko_command:
 451 *               PKO HW command word
 452 * @packet: Packet to send
 453 * @addr: Plysical address of a work queue entry or physical address
 454 *        to zero on complete.
 455 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
 456 *               CVMX_PKO_LOCK_CMD_QUEUE
 457 *
 458 * Returns: CVMX_PKO_SUCCESS on success, or error code on
 459 * failure of output
 460 */
 461static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
 462        uint64_t port,
 463        uint64_t queue,
 464        union cvmx_pko_command_word0 pko_command,
 465        union cvmx_buf_ptr packet,
 466        uint64_t addr,
 467        cvmx_pko_lock_t use_locking)
 468{
 469        cvmx_cmd_queue_result_t result;
 470        if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
 471                cvmx_pow_tag_sw_wait();
 472        result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
 473                                       (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
 474                                       pko_command.u64, packet.u64, addr);
 475        if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
 476                cvmx_pko_doorbell(port, queue, 3);
 477                return CVMX_PKO_SUCCESS;
 478        } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
 479                   || (result == CVMX_CMD_QUEUE_FULL)) {
 480                return CVMX_PKO_NO_MEMORY;
 481        } else {
 482                return CVMX_PKO_INVALID_QUEUE;
 483        }
 484}
 485
 486/**
 487 * Return the pko output queue associated with a port and a specific core.
 488 * In normal mode (PKO lockless operation is disabled), the value returned
 489 * is the base queue.
 490 *
 491 * @port:   Port number
 492 * @core:   Core to get queue for
 493 *
 494 * Returns Core-specific output queue
 495 */
 496static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
 497{
 498#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
 499#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
 500#endif
 501#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
 502#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
 503#endif
 504
 505        if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
 506                return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
 507        else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
 508                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
 509                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
 510                                                           16) *
 511                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
 512        else if ((port >= 32) && (port < 36))
 513                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
 514                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
 515                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
 516                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
 517                                                           32) *
 518                    CVMX_PKO_QUEUES_PER_PORT_PCI;
 519        else if ((port >= 36) && (port < 40))
 520                return CVMX_PKO_MAX_PORTS_INTERFACE0 *
 521                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
 522                    CVMX_PKO_MAX_PORTS_INTERFACE1 *
 523                    CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
 524                    4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
 525                                                        36) *
 526                    CVMX_PKO_QUEUES_PER_PORT_LOOP;
 527        else
 528                /* Given the limit on the number of ports we can map to
 529                 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
 530                 * divided among all cores), the remaining unmapped ports
 531                 * are assigned an illegal queue number */
 532                return CVMX_PKO_ILLEGAL_QUEUE;
 533}
 534
 535/**
 536 * For a given port number, return the base pko output queue
 537 * for the port.
 538 *
 539 * @port:   Port number
 540 * Returns Base output queue
 541 */
 542static inline int cvmx_pko_get_base_queue(int port)
 543{
 544        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
 545                return port;
 546
 547        return cvmx_pko_get_base_queue_per_core(port, 0);
 548}
 549
 550/**
 551 * For a given port number, return the number of pko output queues.
 552 *
 553 * @port:   Port number
 554 * Returns Number of output queues
 555 */
 556static inline int cvmx_pko_get_num_queues(int port)
 557{
 558        if (port < 16)
 559                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
 560        else if (port < 32)
 561                return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
 562        else if (port < 36)
 563                return CVMX_PKO_QUEUES_PER_PORT_PCI;
 564        else if (port < 40)
 565                return CVMX_PKO_QUEUES_PER_PORT_LOOP;
 566        else
 567                return 0;
 568}
 569
 570/**
 571 * Get the status counters for a port.
 572 *
 573 * @port_num: Port number to get statistics for.
 574 * @clear:    Set to 1 to clear the counters after they are read
 575 * @status:   Where to put the results.
 576 */
 577static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
 578                                            cvmx_pko_port_status_t *status)
 579{
 580        union cvmx_pko_reg_read_idx pko_reg_read_idx;
 581        union cvmx_pko_mem_count0 pko_mem_count0;
 582        union cvmx_pko_mem_count1 pko_mem_count1;
 583
 584        pko_reg_read_idx.u64 = 0;
 585        pko_reg_read_idx.s.index = port_num;
 586        cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
 587
 588        pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
 589        status->packets = pko_mem_count0.s.count;
 590        if (clear) {
 591                pko_mem_count0.s.count = port_num;
 592                cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
 593        }
 594
 595        pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
 596        status->octets = pko_mem_count1.s.count;
 597        if (clear) {
 598                pko_mem_count1.s.count = port_num;
 599                cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
 600        }
 601
 602        if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
 603                union cvmx_pko_mem_debug9 debug9;
 604                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
 605                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
 606                debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
 607                status->doorbell = debug9.cn38xx.doorbell;
 608        } else {
 609                union cvmx_pko_mem_debug8 debug8;
 610                pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
 611                cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
 612                debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
 613                status->doorbell = debug8.cn50xx.doorbell;
 614        }
 615}
 616
 617/**
 618 * Rate limit a PKO port to a max packets/sec. This function is only
 619 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
 620 *
 621 * @port:      Port to rate limit
 622 * @packets_s: Maximum packet/sec
 623 * @burst:     Maximum number of packets to burst in a row before rate
 624 *                  limiting cuts in.
 625 *
 626 * Returns Zero on success, negative on failure
 627 */
 628extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
 629
 630/**
 631 * Rate limit a PKO port to a max bits/sec. This function is only
 632 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
 633 *
 634 * @port:   Port to rate limit
 635 * @bits_s: PKO rate limit in bits/sec
 636 * @burst:  Maximum number of bits to burst before rate
 637 *               limiting cuts in.
 638 *
 639 * Returns Zero on success, negative on failure
 640 */
 641extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
 642
 643#endif /* __CVMX_PKO_H__ */
 644