linux/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
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   1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2/* Copyright (c) 2017 Microsemi Corporation */
   3
   4/dts-v1/;
   5
   6#include <dt-bindings/gpio/gpio.h>
   7#include <dt-bindings/interrupt-controller/irq.h>
   8#include <dt-bindings/phy/phy-ocelot-serdes.h>
   9#include "ocelot.dtsi"
  10
  11/ {
  12        compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
  13
  14        chosen {
  15                stdout-path = "serial0:115200n8";
  16        };
  17
  18        memory@0 {
  19                device_type = "memory";
  20                reg = <0x0 0x0e000000>;
  21        };
  22};
  23
  24&gpio {
  25        phy_int_pins: phy_int_pins {
  26                pins = "GPIO_4";
  27                function = "gpio";
  28        };
  29
  30        phy_load_save_pins: phy_load_save_pins {
  31                pins = "GPIO_10";
  32                function = "ptp2";
  33        };
  34};
  35
  36&mdio0 {
  37        status = "okay";
  38};
  39
  40&mdio1 {
  41        status = "okay";
  42        pinctrl-names = "default";
  43        pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
  44
  45        phy7: ethernet-phy@0 {
  46                reg = <0>;
  47                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  48                interrupt-parent = <&gpio>;
  49                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  50        };
  51        phy6: ethernet-phy@1 {
  52                reg = <1>;
  53                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  54                interrupt-parent = <&gpio>;
  55                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  56        };
  57        phy5: ethernet-phy@2 {
  58                reg = <2>;
  59                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  60                interrupt-parent = <&gpio>;
  61                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  62        };
  63        phy4: ethernet-phy@3 {
  64                reg = <3>;
  65                interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
  66                interrupt-parent = <&gpio>;
  67                load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
  68        };
  69};
  70
  71&port0 {
  72        phy-handle = <&phy0>;
  73};
  74
  75&port1 {
  76        phy-handle = <&phy1>;
  77};
  78
  79&port2 {
  80        phy-handle = <&phy2>;
  81};
  82
  83&port3 {
  84        phy-handle = <&phy3>;
  85};
  86
  87&port4 {
  88        phy-handle = <&phy7>;
  89        phy-mode = "sgmii";
  90        phys = <&serdes 4 SERDES1G(2)>;
  91};
  92
  93&port5 {
  94        phy-handle = <&phy4>;
  95        phy-mode = "sgmii";
  96        phys = <&serdes 5 SERDES1G(5)>;
  97};
  98
  99&port6 {
 100        phy-handle = <&phy6>;
 101        phy-mode = "sgmii";
 102        phys = <&serdes 6 SERDES1G(3)>;
 103};
 104
 105&port9 {
 106        phy-handle = <&phy5>;
 107        phy-mode = "sgmii";
 108        phys = <&serdes 9 SERDES1G(4)>;
 109};
 110
 111&uart0 {
 112        status = "okay";
 113};
 114
 115&uart2 {
 116        status = "okay";
 117};
 118