linux/arch/mips/boot/dts/brcm/bcm7362.dtsi
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   1// SPDX-License-Identifier: GPL-2.0
   2/ {
   3        #address-cells = <1>;
   4        #size-cells = <1>;
   5        compatible = "brcm,bcm7362";
   6
   7        cpus {
   8                #address-cells = <1>;
   9                #size-cells = <0>;
  10
  11                mips-hpt-frequency = <375000000>;
  12
  13                cpu@0 {
  14                        compatible = "brcm,bmips4380";
  15                        device_type = "cpu";
  16                        reg = <0>;
  17                };
  18
  19                cpu@1 {
  20                        compatible = "brcm,bmips4380";
  21                        device_type = "cpu";
  22                        reg = <1>;
  23                };
  24        };
  25
  26        aliases {
  27                uart0 = &uart0;
  28        };
  29
  30        cpu_intc: interrupt-controller {
  31                #address-cells = <0>;
  32                compatible = "mti,cpu-interrupt-controller";
  33
  34                interrupt-controller;
  35                #interrupt-cells = <1>;
  36        };
  37
  38        clocks {
  39                uart_clk: uart_clk {
  40                        compatible = "fixed-clock";
  41                        #clock-cells = <0>;
  42                        clock-frequency = <81000000>;
  43                };
  44
  45                upg_clk: upg_clk {
  46                        compatible = "fixed-clock";
  47                        #clock-cells = <0>;
  48                        clock-frequency = <27000000>;
  49                };
  50        };
  51
  52        rdb {
  53                #address-cells = <1>;
  54                #size-cells = <1>;
  55
  56                compatible = "simple-bus";
  57                ranges = <0 0x10000000 0x01000000>;
  58
  59                periph_intc: interrupt-controller@411400 {
  60                        compatible = "brcm,bcm7038-l1-intc";
  61                        reg = <0x411400 0x30>, <0x411600 0x30>;
  62
  63                        interrupt-controller;
  64                        #interrupt-cells = <1>;
  65
  66                        interrupt-parent = <&cpu_intc>;
  67                        interrupts = <2>, <3>;
  68                };
  69
  70                sun_l2_intc: interrupt-controller@403000 {
  71                        compatible = "brcm,l2-intc";
  72                        reg = <0x403000 0x30>;
  73                        interrupt-controller;
  74                        #interrupt-cells = <1>;
  75                        interrupt-parent = <&periph_intc>;
  76                        interrupts = <48>;
  77                };
  78
  79                gisb-arb@400000 {
  80                        compatible = "brcm,bcm7400-gisb-arb";
  81                        reg = <0x400000 0xdc>;
  82                        native-endian;
  83                        interrupt-parent = <&sun_l2_intc>;
  84                        interrupts = <0>, <2>;
  85                        brcm,gisb-arb-master-mask = <0x2f3>;
  86                        brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
  87                                                     "rdc_0", "raaga_0",
  88                                                     "avd_0", "jtag_0";
  89                };
  90
  91                upg_irq0_intc: interrupt-controller@406600 {
  92                        compatible = "brcm,bcm7120-l2-intc";
  93                        reg = <0x406600 0x8>;
  94
  95                        brcm,int-map-mask = <0x44>, <0x7000000>;
  96                        brcm,int-fwd-mask = <0x70000>;
  97
  98                        interrupt-controller;
  99                        #interrupt-cells = <1>;
 100
 101                        interrupt-parent = <&periph_intc>;
 102                        interrupts = <56>, <54>;
 103                        interrupt-names = "upg_main", "upg_bsc";
 104                };
 105
 106                upg_aon_irq0_intc: interrupt-controller@408b80 {
 107                        compatible = "brcm,bcm7120-l2-intc";
 108                        reg = <0x408b80 0x8>;
 109
 110                        brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
 111                        brcm,int-fwd-mask = <0>;
 112                        brcm,irq-can-wake;
 113
 114                        interrupt-controller;
 115                        #interrupt-cells = <1>;
 116
 117                        interrupt-parent = <&periph_intc>;
 118                        interrupts = <57>, <55>, <59>;
 119                        interrupt-names = "upg_main_aon", "upg_bsc_aon",
 120                                          "upg_spi";
 121                };
 122
 123                sun_top_ctrl: syscon@404000 {
 124                        compatible = "brcm,bcm7362-sun-top-ctrl", "syscon";
 125                        reg = <0x404000 0x51c>;
 126                        native-endian;
 127                };
 128
 129                reboot {
 130                        compatible = "brcm,brcmstb-reboot";
 131                        syscon = <&sun_top_ctrl 0x304 0x308>;
 132                };
 133
 134                uart0: serial@406800 {
 135                        compatible = "ns16550a";
 136                        reg = <0x406800 0x20>;
 137                        reg-io-width = <0x4>;
 138                        reg-shift = <0x2>;
 139                        native-endian;
 140                        interrupt-parent = <&periph_intc>;
 141                        interrupts = <61>;
 142                        clocks = <&uart_clk>;
 143                        status = "disabled";
 144                };
 145
 146                uart1: serial@406840 {
 147                        compatible = "ns16550a";
 148                        reg = <0x406840 0x20>;
 149                        reg-io-width = <0x4>;
 150                        reg-shift = <0x2>;
 151                        native-endian;
 152                        interrupt-parent = <&periph_intc>;
 153                        interrupts = <62>;
 154                        clocks = <&uart_clk>;
 155                        status = "disabled";
 156                };
 157
 158                uart2: serial@406880 {
 159                        compatible = "ns16550a";
 160                        reg = <0x406880 0x20>;
 161                        reg-io-width = <0x4>;
 162                        reg-shift = <0x2>;
 163                        native-endian;
 164                        interrupt-parent = <&periph_intc>;
 165                        interrupts = <63>;
 166                        clocks = <&uart_clk>;
 167                        status = "disabled";
 168                };
 169
 170                bsca: i2c@406200 {
 171                      clock-frequency = <390000>;
 172                      compatible = "brcm,brcmstb-i2c";
 173                      interrupt-parent = <&upg_irq0_intc>;
 174                      reg = <0x406200 0x58>;
 175                      interrupts = <24>;
 176                      interrupt-names = "upg_bsca";
 177                      status = "disabled";
 178                };
 179
 180                bscb: i2c@406280 {
 181                      clock-frequency = <390000>;
 182                      compatible = "brcm,brcmstb-i2c";
 183                      interrupt-parent = <&upg_irq0_intc>;
 184                      reg = <0x406280 0x58>;
 185                      interrupts = <25>;
 186                      interrupt-names = "upg_bscb";
 187                      status = "disabled";
 188                };
 189
 190                bscd: i2c@408980 {
 191                      clock-frequency = <390000>;
 192                      compatible = "brcm,brcmstb-i2c";
 193                      interrupt-parent = <&upg_aon_irq0_intc>;
 194                      reg = <0x408980 0x58>;
 195                      interrupts = <27>;
 196                      interrupt-names = "upg_bscd";
 197                      status = "disabled";
 198                };
 199
 200                pwma: pwm@406400 {
 201                        compatible = "brcm,bcm7038-pwm";
 202                        reg = <0x406400 0x28>;
 203                        #pwm-cells = <2>;
 204                        clocks = <&upg_clk>;
 205                        status = "disabled";
 206                };
 207
 208                watchdog: watchdog@4066a8 {
 209                        clocks = <&upg_clk>;
 210                        compatible = "brcm,bcm7038-wdt";
 211                        reg = <0x4066a8 0x14>;
 212                        status = "disabled";
 213                };
 214
 215                aon_pm_l2_intc: interrupt-controller@408440 {
 216                        compatible = "brcm,l2-intc";
 217                        reg = <0x408440 0x30>;
 218                        interrupt-controller;
 219                        #interrupt-cells = <1>;
 220                        interrupt-parent = <&periph_intc>;
 221                        interrupts = <50>;
 222                        brcm,irq-can-wake;
 223                };
 224
 225                aon_ctrl: syscon@408000 {
 226                        compatible = "brcm,brcmstb-aon-ctrl";
 227                        reg = <0x408000 0x100>, <0x408200 0x200>;
 228                        reg-names = "aon-ctrl", "aon-sram";
 229                };
 230
 231                timers: timer@406680 {
 232                        compatible = "brcm,brcmstb-timers";
 233                        reg = <0x406680 0x40>;
 234                };
 235
 236                upg_gio: gpio@406500 {
 237                        compatible = "brcm,brcmstb-gpio";
 238                        reg = <0x406500 0xa0>;
 239                        #gpio-cells = <2>;
 240                        #interrupt-cells = <2>;
 241                        gpio-controller;
 242                        interrupt-controller;
 243                        interrupt-parent = <&upg_irq0_intc>;
 244                        interrupts = <6>;
 245                        brcm,gpio-bank-widths = <32 32 32 29 4>;
 246                };
 247
 248                upg_gio_aon: gpio@408c00 {
 249                        compatible = "brcm,brcmstb-gpio";
 250                        reg = <0x408c00 0x60>;
 251                        #gpio-cells = <2>;
 252                        #interrupt-cells = <2>;
 253                        gpio-controller;
 254                        interrupt-controller;
 255                        interrupt-parent = <&upg_aon_irq0_intc>;
 256                        interrupts = <6>;
 257                        interrupts-extended = <&upg_aon_irq0_intc 6>,
 258                                              <&aon_pm_l2_intc 5>;
 259                        wakeup-source;
 260                        brcm,gpio-bank-widths = <21 32 2>;
 261                };
 262
 263                enet0: ethernet@430000 {
 264                        phy-mode = "internal";
 265                        phy-handle = <&phy1>;
 266                        mac-address = [ 00 10 18 36 23 1a ];
 267                        compatible = "brcm,genet-v2";
 268                        #address-cells = <0x1>;
 269                        #size-cells = <0x1>;
 270                        reg = <0x430000 0x4c8c>;
 271                        interrupts = <24>, <25>;
 272                        interrupt-parent = <&periph_intc>;
 273                        status = "disabled";
 274
 275                        mdio@e14 {
 276                                compatible = "brcm,genet-mdio-v2";
 277                                #address-cells = <0x1>;
 278                                #size-cells = <0x0>;
 279                                reg = <0xe14 0x8>;
 280
 281                                phy1: ethernet-phy@1 {
 282                                        max-speed = <100>;
 283                                        reg = <0x1>;
 284                                        compatible = "brcm,40nm-ephy",
 285                                                "ethernet-phy-ieee802.3-c22";
 286                                };
 287                        };
 288                };
 289
 290                ehci0: usb@480300 {
 291                        compatible = "brcm,bcm7362-ehci", "generic-ehci";
 292                        reg = <0x480300 0x100>;
 293                        native-endian;
 294                        interrupt-parent = <&periph_intc>;
 295                        interrupts = <65>;
 296                        status = "disabled";
 297                };
 298
 299                ohci0: usb@480400 {
 300                        compatible = "brcm,bcm7362-ohci", "generic-ohci";
 301                        reg = <0x480400 0x100>;
 302                        native-endian;
 303                        no-big-frame-no;
 304                        interrupt-parent = <&periph_intc>;
 305                        interrupts = <66>;
 306                        status = "disabled";
 307                };
 308
 309                hif_l2_intc: interrupt-controller@411000 {
 310                        compatible = "brcm,l2-intc";
 311                        reg = <0x411000 0x30>;
 312                        interrupt-controller;
 313                        #interrupt-cells = <1>;
 314                        interrupt-parent = <&periph_intc>;
 315                        interrupts = <30>;
 316                };
 317
 318                nand: nand@412800 {
 319                        compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
 320                        #address-cells = <1>;
 321                        #size-cells = <0>;
 322                        reg-names = "nand";
 323                        reg = <0x412800 0x400>;
 324                        interrupt-parent = <&hif_l2_intc>;
 325                        interrupts = <24>;
 326                        status = "disabled";
 327                };
 328
 329                sata: sata@181000 {
 330                        compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
 331                        reg-names = "ahci", "top-ctrl";
 332                        reg = <0x181000 0xa9c>, <0x180020 0x1c>;
 333                        interrupt-parent = <&periph_intc>;
 334                        interrupts = <86>;
 335                        #address-cells = <1>;
 336                        #size-cells = <0>;
 337                        status = "disabled";
 338
 339                        sata0: sata-port@0 {
 340                                reg = <0>;
 341                                phys = <&sata_phy0>;
 342                        };
 343
 344                        sata1: sata-port@1 {
 345                                reg = <1>;
 346                                phys = <&sata_phy1>;
 347                        };
 348                };
 349
 350                sata_phy: sata-phy@180100 {
 351                        compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3";
 352                        reg = <0x180100 0x0eff>;
 353                        reg-names = "phy";
 354                        #address-cells = <1>;
 355                        #size-cells = <0>;
 356                        status = "disabled";
 357
 358                        sata_phy0: sata-phy@0 {
 359                                reg = <0>;
 360                                #phy-cells = <0>;
 361                        };
 362
 363                        sata_phy1: sata-phy@1 {
 364                                reg = <1>;
 365                                #phy-cells = <0>;
 366                        };
 367                };
 368
 369                sdhci0: sdhci@410000 {
 370                        compatible = "brcm,bcm7425-sdhci";
 371                        reg = <0x410000 0x100>;
 372                        interrupt-parent = <&periph_intc>;
 373                        interrupts = <82>;
 374                        status = "disabled";
 375                };
 376
 377                spi_l2_intc: interrupt-controller@411d00 {
 378                        compatible = "brcm,l2-intc";
 379                        reg = <0x411d00 0x30>;
 380                        interrupt-controller;
 381                        #interrupt-cells = <1>;
 382                        interrupt-parent = <&periph_intc>;
 383                        interrupts = <31>;
 384                };
 385
 386                qspi: spi@413000 {
 387                        #address-cells = <0x1>;
 388                        #size-cells = <0x0>;
 389                        compatible = "brcm,spi-bcm-qspi",
 390                                     "brcm,spi-brcmstb-qspi";
 391                        clocks = <&upg_clk>;
 392                        reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
 393                        reg-names = "cs_reg", "hif_mspi", "bspi";
 394                        interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
 395                        interrupt-parent = <&spi_l2_intc>;
 396                        interrupt-names = "spi_lr_fullness_reached",
 397                                          "spi_lr_session_aborted",
 398                                          "spi_lr_impatient",
 399                                          "spi_lr_session_done",
 400                                          "spi_lr_overread",
 401                                          "mspi_done",
 402                                          "mspi_halted";
 403                        status = "disabled";
 404                };
 405
 406                mspi: spi@408a00 {
 407                        #address-cells = <1>;
 408                        #size-cells = <0>;
 409                        compatible = "brcm,spi-bcm-qspi",
 410                                     "brcm,spi-brcmstb-mspi";
 411                        clocks = <&upg_clk>;
 412                        reg = <0x408a00 0x180>;
 413                        reg-names = "mspi";
 414                        interrupts = <0x14>;
 415                        interrupt-parent = <&upg_aon_irq0_intc>;
 416                        interrupt-names = "mspi_done";
 417                        status = "disabled";
 418                };
 419
 420                waketimer: waketimer@408e80 {
 421                        compatible = "brcm,brcmstb-waketimer";
 422                        reg = <0x408e80 0x14>;
 423                        interrupts = <0x3>;
 424                        interrupt-parent = <&aon_pm_l2_intc>;
 425                        interrupt-names = "timer";
 426                        clocks = <&upg_clk>;
 427                        status = "disabled";
 428                };
 429        };
 430
 431        memory_controllers {
 432                compatible = "simple-bus";
 433                ranges = <0x0 0x103b0000 0xa000>;
 434                #address-cells = <1>;
 435                #size-cells = <1>;
 436
 437                memory-controller@0 {
 438                        compatible = "brcm,brcmstb-memc", "simple-bus";
 439                        ranges = <0x0 0x0 0xa000>;
 440                        #address-cells = <1>;
 441                        #size-cells = <1>;
 442
 443                        memc-arb@1000 {
 444                                compatible = "brcm,brcmstb-memc-arb";
 445                                reg = <0x1000 0x248>;
 446                        };
 447
 448                        memc-ddr@2000 {
 449                                compatible = "brcm,brcmstb-memc-ddr";
 450                                reg = <0x2000 0x300>;
 451                        };
 452
 453                        ddr-phy@6000 {
 454                                compatible = "brcm,brcmstb-ddr-phy";
 455                                reg = <0x6000 0xc8>;
 456                        };
 457
 458                        shimphy@8000 {
 459                                compatible = "brcm,brcmstb-ddr-shimphy";
 460                                reg = <0x8000 0x13c>;
 461                        };
 462                };
 463        };
 464};
 465