linux/arch/mips/boot/dts/brcm/bcm3368.dtsi
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   1// SPDX-License-Identifier: GPL-2.0
   2
   3#include "dt-bindings/clock/bcm3368-clock.h"
   4
   5/ {
   6        #address-cells = <1>;
   7        #size-cells = <1>;
   8        compatible = "brcm,bcm3368";
   9
  10        cpus {
  11                #address-cells = <1>;
  12                #size-cells = <0>;
  13
  14                mips-hpt-frequency = <150000000>;
  15
  16                cpu@0 {
  17                        compatible = "brcm,bmips4350";
  18                        device_type = "cpu";
  19                        reg = <0>;
  20                };
  21
  22                cpu@1 {
  23                        compatible = "brcm,bmips4350";
  24                        device_type = "cpu";
  25                        reg = <1>;
  26                };
  27        };
  28
  29        clocks {
  30                periph_clk: periph-clk {
  31                        compatible = "fixed-clock";
  32                        #clock-cells = <0>;
  33                        clock-frequency = <50000000>;
  34                };
  35        };
  36
  37        aliases {
  38                serial0 = &uart0;
  39                serial1 = &uart1;
  40        };
  41
  42        cpu_intc: interrupt-controller {
  43                #address-cells = <0>;
  44                compatible = "mti,cpu-interrupt-controller";
  45
  46                interrupt-controller;
  47                #interrupt-cells = <1>;
  48        };
  49
  50        ubus {
  51                #address-cells = <1>;
  52                #size-cells = <1>;
  53
  54                compatible = "simple-bus";
  55                ranges;
  56
  57                clkctl: clock-controller@fff8c004 {
  58                        compatible = "brcm,bcm3368-clocks";
  59                        reg = <0xfff8c004 0x4>;
  60                        #clock-cells = <1>;
  61                };
  62
  63                periph_cntl: syscon@fff8c008 {
  64                        compatible = "syscon";
  65                        reg = <0xfff8c008 0x4>;
  66                        native-endian;
  67                };
  68
  69                reboot: syscon-reboot@fff8c008 {
  70                        compatible = "syscon-reboot";
  71                        regmap = <&periph_cntl>;
  72                        offset = <0x0>;
  73                        mask = <0x1>;
  74                };
  75
  76                periph_intc: interrupt-controller@fff8c00c {
  77                        compatible = "brcm,bcm6345-l1-intc";
  78                        reg = <0xfff8c00c 0x8>;
  79
  80                        interrupt-controller;
  81                        #interrupt-cells = <1>;
  82
  83                        interrupt-parent = <&cpu_intc>;
  84                        interrupts = <2>;
  85                };
  86
  87                uart0: serial@fff8c100 {
  88                        compatible = "brcm,bcm6345-uart";
  89                        reg = <0xfff8c100 0x18>;
  90
  91                        interrupt-parent = <&periph_intc>;
  92                        interrupts = <2>;
  93
  94                        clocks = <&periph_clk>;
  95                        clock-names = "refclk";
  96
  97                        status = "disabled";
  98                };
  99
 100                uart1: serial@fff8c120 {
 101                        compatible = "brcm,bcm6345-uart";
 102                        reg = <0xfff8c120 0x18>;
 103
 104                        interrupt-parent = <&periph_intc>;
 105                        interrupts = <3>;
 106
 107                        clocks = <&periph_clk>;
 108                        clock-names = "refclk";
 109
 110                        status = "disabled";
 111                };
 112        };
 113};
 114