linux/arch/arm64/kernel/perf_event.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * ARMv8 PMUv3 Performance Events handling code.
   4 *
   5 * Copyright (C) 2012 ARM Limited
   6 * Author: Will Deacon <will.deacon@arm.com>
   7 *
   8 * This code is based heavily on the ARMv7 perf event code.
   9 */
  10
  11#include <asm/irq_regs.h>
  12#include <asm/perf_event.h>
  13#include <asm/sysreg.h>
  14#include <asm/virt.h>
  15
  16#include <clocksource/arm_arch_timer.h>
  17
  18#include <linux/acpi.h>
  19#include <linux/clocksource.h>
  20#include <linux/kvm_host.h>
  21#include <linux/of.h>
  22#include <linux/perf/arm_pmu.h>
  23#include <linux/platform_device.h>
  24#include <linux/sched_clock.h>
  25#include <linux/smp.h>
  26
  27/* ARMv8 Cortex-A53 specific event types. */
  28#define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
  29
  30/* ARMv8 Cavium ThunderX specific event types. */
  31#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
  32#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
  33#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
  34#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
  35#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
  36
  37/*
  38 * ARMv8 Architectural defined events, not all of these may
  39 * be supported on any given implementation. Unsupported events will
  40 * be disabled at run-time based on the PMCEID registers.
  41 */
  42static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
  43        PERF_MAP_ALL_UNSUPPORTED,
  44        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
  45        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
  46        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  47        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  48        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
  49        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  50        [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
  51        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
  52        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
  53};
  54
  55static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  56                                                [PERF_COUNT_HW_CACHE_OP_MAX]
  57                                                [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  58        PERF_CACHE_MAP_ALL_UNSUPPORTED,
  59
  60        [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
  61        [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
  62
  63        [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
  64        [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
  65
  66        [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
  67        [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
  68
  69        [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
  70        [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
  71
  72        [C(LL)][C(OP_READ)][C(RESULT_MISS)]     = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
  73        [C(LL)][C(OP_READ)][C(RESULT_ACCESS)]   = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
  74
  75        [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
  76        [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
  77};
  78
  79static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  80                                              [PERF_COUNT_HW_CACHE_OP_MAX]
  81                                              [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  82        PERF_CACHE_MAP_ALL_UNSUPPORTED,
  83
  84        [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
  85
  86        [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
  87        [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
  88};
  89
  90static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
  91                                              [PERF_COUNT_HW_CACHE_OP_MAX]
  92                                              [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
  93        PERF_CACHE_MAP_ALL_UNSUPPORTED,
  94
  95        [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
  96        [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
  97        [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
  98        [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
  99
 100        [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 101        [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 102
 103        [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 104        [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 105};
 106
 107static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 108                                              [PERF_COUNT_HW_CACHE_OP_MAX]
 109                                              [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 110        PERF_CACHE_MAP_ALL_UNSUPPORTED,
 111
 112        [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 113        [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 114};
 115
 116static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 117                                                   [PERF_COUNT_HW_CACHE_OP_MAX]
 118                                                   [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 119        PERF_CACHE_MAP_ALL_UNSUPPORTED,
 120
 121        [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 122        [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 123        [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 124        [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 125        [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 126        [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 127
 128        [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 129        [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 130
 131        [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 132        [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 133        [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 134        [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 135};
 136
 137static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 138                                              [PERF_COUNT_HW_CACHE_OP_MAX]
 139                                              [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 140        PERF_CACHE_MAP_ALL_UNSUPPORTED,
 141
 142        [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 143        [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 144        [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 145        [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 146
 147        [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 148        [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 149        [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 150        [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 151
 152        [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 153        [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 154};
 155
 156static ssize_t
 157armv8pmu_events_sysfs_show(struct device *dev,
 158                           struct device_attribute *attr, char *page)
 159{
 160        struct perf_pmu_events_attr *pmu_attr;
 161
 162        pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 163
 164        return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
 165}
 166
 167#define ARMV8_EVENT_ATTR(name, config)                                          \
 168        PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
 169
 170static struct attribute *armv8_pmuv3_event_attrs[] = {
 171        ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR),
 172        ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
 173        ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
 174        ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
 175        ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
 176        ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
 177        ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
 178        ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
 179        ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
 180        ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
 181        ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
 182        ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
 183        ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
 184        ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
 185        ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
 186        ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
 187        ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
 188        ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
 189        ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
 190        ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
 191        ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
 192        ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
 193        ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
 194        ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
 195        ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
 196        ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
 197        ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
 198        ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
 199        ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
 200        ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
 201        /* Don't expose the chain event in /sys, since it's useless in isolation */
 202        ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
 203        ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
 204        ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
 205        ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
 206        ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
 207        ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
 208        ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
 209        ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
 210        ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
 211        ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
 212        ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
 213        ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
 214        ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
 215        ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
 216        ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
 217        ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
 218        ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
 219        ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
 220        ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
 221        ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
 222        ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
 223        ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
 224        ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
 225        ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
 226        ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
 227        ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
 228        ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
 229        ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
 230        ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
 231        ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
 232        ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
 233        ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
 234        ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
 235        ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
 236        ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
 237        ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
 238        ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
 239        ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
 240        ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
 241        ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
 242        ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
 243        ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
 244        ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
 245        ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
 246        ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
 247        ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
 248        ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
 249        ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
 250        ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
 251        NULL,
 252};
 253
 254static umode_t
 255armv8pmu_event_attr_is_visible(struct kobject *kobj,
 256                               struct attribute *attr, int unused)
 257{
 258        struct device *dev = kobj_to_dev(kobj);
 259        struct pmu *pmu = dev_get_drvdata(dev);
 260        struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 261        struct perf_pmu_events_attr *pmu_attr;
 262
 263        pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 264
 265        if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 266            test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 267                return attr->mode;
 268
 269        if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
 270                u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
 271
 272                if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
 273                    test_bit(id, cpu_pmu->pmceid_ext_bitmap))
 274                        return attr->mode;
 275        }
 276
 277        return 0;
 278}
 279
 280static const struct attribute_group armv8_pmuv3_events_attr_group = {
 281        .name = "events",
 282        .attrs = armv8_pmuv3_event_attrs,
 283        .is_visible = armv8pmu_event_attr_is_visible,
 284};
 285
 286PMU_FORMAT_ATTR(event, "config:0-15");
 287PMU_FORMAT_ATTR(long, "config1:0");
 288
 289static inline bool armv8pmu_event_is_64bit(struct perf_event *event)
 290{
 291        return event->attr.config1 & 0x1;
 292}
 293
 294static struct attribute *armv8_pmuv3_format_attrs[] = {
 295        &format_attr_event.attr,
 296        &format_attr_long.attr,
 297        NULL,
 298};
 299
 300static const struct attribute_group armv8_pmuv3_format_attr_group = {
 301        .name = "format",
 302        .attrs = armv8_pmuv3_format_attrs,
 303};
 304
 305static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
 306                          char *page)
 307{
 308        struct pmu *pmu = dev_get_drvdata(dev);
 309        struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 310        u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK;
 311
 312        return sysfs_emit(page, "0x%08x\n", slots);
 313}
 314
 315static DEVICE_ATTR_RO(slots);
 316
 317static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
 318                              char *page)
 319{
 320        struct pmu *pmu = dev_get_drvdata(dev);
 321        struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 322        u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT)
 323                        & ARMV8_PMU_BUS_SLOTS_MASK;
 324
 325        return sysfs_emit(page, "0x%08x\n", bus_slots);
 326}
 327
 328static DEVICE_ATTR_RO(bus_slots);
 329
 330static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
 331                              char *page)
 332{
 333        struct pmu *pmu = dev_get_drvdata(dev);
 334        struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 335        u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT)
 336                        & ARMV8_PMU_BUS_WIDTH_MASK;
 337        u32 val = 0;
 338
 339        /* Encoded as Log2(number of bytes), plus one */
 340        if (bus_width > 2 && bus_width < 13)
 341                val = 1 << (bus_width - 1);
 342
 343        return sysfs_emit(page, "0x%08x\n", val);
 344}
 345
 346static DEVICE_ATTR_RO(bus_width);
 347
 348static struct attribute *armv8_pmuv3_caps_attrs[] = {
 349        &dev_attr_slots.attr,
 350        &dev_attr_bus_slots.attr,
 351        &dev_attr_bus_width.attr,
 352        NULL,
 353};
 354
 355static const struct attribute_group armv8_pmuv3_caps_attr_group = {
 356        .name = "caps",
 357        .attrs = armv8_pmuv3_caps_attrs,
 358};
 359
 360/*
 361 * Perf Events' indices
 362 */
 363#define ARMV8_IDX_CYCLE_COUNTER 0
 364#define ARMV8_IDX_COUNTER0      1
 365
 366
 367/*
 368 * We unconditionally enable ARMv8.5-PMU long event counter support
 369 * (64-bit events) where supported. Indicate if this arm_pmu has long
 370 * event counter support.
 371 */
 372static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
 373{
 374        return (cpu_pmu->pmuver >= ID_AA64DFR0_PMUVER_8_5);
 375}
 376
 377/*
 378 * We must chain two programmable counters for 64 bit events,
 379 * except when we have allocated the 64bit cycle counter (for CPU
 380 * cycles event). This must be called only when the event has
 381 * a counter allocated.
 382 */
 383static inline bool armv8pmu_event_is_chained(struct perf_event *event)
 384{
 385        int idx = event->hw.idx;
 386        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 387
 388        return !WARN_ON(idx < 0) &&
 389               armv8pmu_event_is_64bit(event) &&
 390               !armv8pmu_has_long_event(cpu_pmu) &&
 391               (idx != ARMV8_IDX_CYCLE_COUNTER);
 392}
 393
 394/*
 395 * ARMv8 low level PMU access
 396 */
 397
 398/*
 399 * Perf Event to low level counters mapping
 400 */
 401#define ARMV8_IDX_TO_COUNTER(x) \
 402        (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 403
 404/*
 405 * This code is really good
 406 */
 407
 408#define PMEVN_CASE(n, case_macro) \
 409        case n: case_macro(n); break
 410
 411#define PMEVN_SWITCH(x, case_macro)                             \
 412        do {                                                    \
 413                switch (x) {                                    \
 414                PMEVN_CASE(0,  case_macro);                     \
 415                PMEVN_CASE(1,  case_macro);                     \
 416                PMEVN_CASE(2,  case_macro);                     \
 417                PMEVN_CASE(3,  case_macro);                     \
 418                PMEVN_CASE(4,  case_macro);                     \
 419                PMEVN_CASE(5,  case_macro);                     \
 420                PMEVN_CASE(6,  case_macro);                     \
 421                PMEVN_CASE(7,  case_macro);                     \
 422                PMEVN_CASE(8,  case_macro);                     \
 423                PMEVN_CASE(9,  case_macro);                     \
 424                PMEVN_CASE(10, case_macro);                     \
 425                PMEVN_CASE(11, case_macro);                     \
 426                PMEVN_CASE(12, case_macro);                     \
 427                PMEVN_CASE(13, case_macro);                     \
 428                PMEVN_CASE(14, case_macro);                     \
 429                PMEVN_CASE(15, case_macro);                     \
 430                PMEVN_CASE(16, case_macro);                     \
 431                PMEVN_CASE(17, case_macro);                     \
 432                PMEVN_CASE(18, case_macro);                     \
 433                PMEVN_CASE(19, case_macro);                     \
 434                PMEVN_CASE(20, case_macro);                     \
 435                PMEVN_CASE(21, case_macro);                     \
 436                PMEVN_CASE(22, case_macro);                     \
 437                PMEVN_CASE(23, case_macro);                     \
 438                PMEVN_CASE(24, case_macro);                     \
 439                PMEVN_CASE(25, case_macro);                     \
 440                PMEVN_CASE(26, case_macro);                     \
 441                PMEVN_CASE(27, case_macro);                     \
 442                PMEVN_CASE(28, case_macro);                     \
 443                PMEVN_CASE(29, case_macro);                     \
 444                PMEVN_CASE(30, case_macro);                     \
 445                default: WARN(1, "Invalid PMEV* index\n");      \
 446                }                                               \
 447        } while (0)
 448
 449#define RETURN_READ_PMEVCNTRN(n) \
 450        return read_sysreg(pmevcntr##n##_el0)
 451static unsigned long read_pmevcntrn(int n)
 452{
 453        PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
 454        return 0;
 455}
 456
 457#define WRITE_PMEVCNTRN(n) \
 458        write_sysreg(val, pmevcntr##n##_el0)
 459static void write_pmevcntrn(int n, unsigned long val)
 460{
 461        PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
 462}
 463
 464#define WRITE_PMEVTYPERN(n) \
 465        write_sysreg(val, pmevtyper##n##_el0)
 466static void write_pmevtypern(int n, unsigned long val)
 467{
 468        PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
 469}
 470
 471static inline u32 armv8pmu_pmcr_read(void)
 472{
 473        return read_sysreg(pmcr_el0);
 474}
 475
 476static inline void armv8pmu_pmcr_write(u32 val)
 477{
 478        val &= ARMV8_PMU_PMCR_MASK;
 479        isb();
 480        write_sysreg(val, pmcr_el0);
 481}
 482
 483static inline int armv8pmu_has_overflowed(u32 pmovsr)
 484{
 485        return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 486}
 487
 488static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 489{
 490        return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 491}
 492
 493static inline u64 armv8pmu_read_evcntr(int idx)
 494{
 495        u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 496
 497        return read_pmevcntrn(counter);
 498}
 499
 500static inline u64 armv8pmu_read_hw_counter(struct perf_event *event)
 501{
 502        int idx = event->hw.idx;
 503        u64 val = armv8pmu_read_evcntr(idx);
 504
 505        if (armv8pmu_event_is_chained(event))
 506                val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
 507        return val;
 508}
 509
 510/*
 511 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
 512 * is set the event counters also become 64-bit counters. Unless the
 513 * user has requested a long counter (attr.config1) then we want to
 514 * interrupt upon 32-bit overflow - we achieve this by applying a bias.
 515 */
 516static bool armv8pmu_event_needs_bias(struct perf_event *event)
 517{
 518        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 519        struct hw_perf_event *hwc = &event->hw;
 520        int idx = hwc->idx;
 521
 522        if (armv8pmu_event_is_64bit(event))
 523                return false;
 524
 525        if (armv8pmu_has_long_event(cpu_pmu) ||
 526            idx == ARMV8_IDX_CYCLE_COUNTER)
 527                return true;
 528
 529        return false;
 530}
 531
 532static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
 533{
 534        if (armv8pmu_event_needs_bias(event))
 535                value |= GENMASK(63, 32);
 536
 537        return value;
 538}
 539
 540static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
 541{
 542        if (armv8pmu_event_needs_bias(event))
 543                value &= ~GENMASK(63, 32);
 544
 545        return value;
 546}
 547
 548static u64 armv8pmu_read_counter(struct perf_event *event)
 549{
 550        struct hw_perf_event *hwc = &event->hw;
 551        int idx = hwc->idx;
 552        u64 value;
 553
 554        if (idx == ARMV8_IDX_CYCLE_COUNTER)
 555                value = read_sysreg(pmccntr_el0);
 556        else
 557                value = armv8pmu_read_hw_counter(event);
 558
 559        return  armv8pmu_unbias_long_counter(event, value);
 560}
 561
 562static inline void armv8pmu_write_evcntr(int idx, u64 value)
 563{
 564        u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 565
 566        write_pmevcntrn(counter, value);
 567}
 568
 569static inline void armv8pmu_write_hw_counter(struct perf_event *event,
 570                                             u64 value)
 571{
 572        int idx = event->hw.idx;
 573
 574        if (armv8pmu_event_is_chained(event)) {
 575                armv8pmu_write_evcntr(idx, upper_32_bits(value));
 576                armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
 577        } else {
 578                armv8pmu_write_evcntr(idx, value);
 579        }
 580}
 581
 582static void armv8pmu_write_counter(struct perf_event *event, u64 value)
 583{
 584        struct hw_perf_event *hwc = &event->hw;
 585        int idx = hwc->idx;
 586
 587        value = armv8pmu_bias_long_counter(event, value);
 588
 589        if (idx == ARMV8_IDX_CYCLE_COUNTER)
 590                write_sysreg(value, pmccntr_el0);
 591        else
 592                armv8pmu_write_hw_counter(event, value);
 593}
 594
 595static inline void armv8pmu_write_evtype(int idx, u32 val)
 596{
 597        u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 598
 599        val &= ARMV8_PMU_EVTYPE_MASK;
 600        write_pmevtypern(counter, val);
 601}
 602
 603static inline void armv8pmu_write_event_type(struct perf_event *event)
 604{
 605        struct hw_perf_event *hwc = &event->hw;
 606        int idx = hwc->idx;
 607
 608        /*
 609         * For chained events, the low counter is programmed to count
 610         * the event of interest and the high counter is programmed
 611         * with CHAIN event code with filters set to count at all ELs.
 612         */
 613        if (armv8pmu_event_is_chained(event)) {
 614                u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
 615                                ARMV8_PMU_INCLUDE_EL2;
 616
 617                armv8pmu_write_evtype(idx - 1, hwc->config_base);
 618                armv8pmu_write_evtype(idx, chain_evt);
 619        } else {
 620                if (idx == ARMV8_IDX_CYCLE_COUNTER)
 621                        write_sysreg(hwc->config_base, pmccfiltr_el0);
 622                else
 623                        armv8pmu_write_evtype(idx, hwc->config_base);
 624        }
 625}
 626
 627static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
 628{
 629        int counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 630        u32 mask = BIT(counter);
 631
 632        if (armv8pmu_event_is_chained(event))
 633                mask |= BIT(counter - 1);
 634        return mask;
 635}
 636
 637static inline void armv8pmu_enable_counter(u32 mask)
 638{
 639        /*
 640         * Make sure event configuration register writes are visible before we
 641         * enable the counter.
 642         * */
 643        isb();
 644        write_sysreg(mask, pmcntenset_el0);
 645}
 646
 647static inline void armv8pmu_enable_event_counter(struct perf_event *event)
 648{
 649        struct perf_event_attr *attr = &event->attr;
 650        u32 mask = armv8pmu_event_cnten_mask(event);
 651
 652        kvm_set_pmu_events(mask, attr);
 653
 654        /* We rely on the hypervisor switch code to enable guest counters */
 655        if (!kvm_pmu_counter_deferred(attr))
 656                armv8pmu_enable_counter(mask);
 657}
 658
 659static inline void armv8pmu_disable_counter(u32 mask)
 660{
 661        write_sysreg(mask, pmcntenclr_el0);
 662        /*
 663         * Make sure the effects of disabling the counter are visible before we
 664         * start configuring the event.
 665         */
 666        isb();
 667}
 668
 669static inline void armv8pmu_disable_event_counter(struct perf_event *event)
 670{
 671        struct perf_event_attr *attr = &event->attr;
 672        u32 mask = armv8pmu_event_cnten_mask(event);
 673
 674        kvm_clr_pmu_events(mask);
 675
 676        /* We rely on the hypervisor switch code to disable guest counters */
 677        if (!kvm_pmu_counter_deferred(attr))
 678                armv8pmu_disable_counter(mask);
 679}
 680
 681static inline void armv8pmu_enable_intens(u32 mask)
 682{
 683        write_sysreg(mask, pmintenset_el1);
 684}
 685
 686static inline void armv8pmu_enable_event_irq(struct perf_event *event)
 687{
 688        u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 689        armv8pmu_enable_intens(BIT(counter));
 690}
 691
 692static inline void armv8pmu_disable_intens(u32 mask)
 693{
 694        write_sysreg(mask, pmintenclr_el1);
 695        isb();
 696        /* Clear the overflow flag in case an interrupt is pending. */
 697        write_sysreg(mask, pmovsclr_el0);
 698        isb();
 699}
 700
 701static inline void armv8pmu_disable_event_irq(struct perf_event *event)
 702{
 703        u32 counter = ARMV8_IDX_TO_COUNTER(event->hw.idx);
 704        armv8pmu_disable_intens(BIT(counter));
 705}
 706
 707static inline u32 armv8pmu_getreset_flags(void)
 708{
 709        u32 value;
 710
 711        /* Read */
 712        value = read_sysreg(pmovsclr_el0);
 713
 714        /* Write to clear flags */
 715        value &= ARMV8_PMU_OVSR_MASK;
 716        write_sysreg(value, pmovsclr_el0);
 717
 718        return value;
 719}
 720
 721static void armv8pmu_enable_event(struct perf_event *event)
 722{
 723        /*
 724         * Enable counter and interrupt, and set the counter to count
 725         * the event that we're interested in.
 726         */
 727
 728        /*
 729         * Disable counter
 730         */
 731        armv8pmu_disable_event_counter(event);
 732
 733        /*
 734         * Set event.
 735         */
 736        armv8pmu_write_event_type(event);
 737
 738        /*
 739         * Enable interrupt for this counter
 740         */
 741        armv8pmu_enable_event_irq(event);
 742
 743        /*
 744         * Enable counter
 745         */
 746        armv8pmu_enable_event_counter(event);
 747}
 748
 749static void armv8pmu_disable_event(struct perf_event *event)
 750{
 751        /*
 752         * Disable counter
 753         */
 754        armv8pmu_disable_event_counter(event);
 755
 756        /*
 757         * Disable interrupt for this counter
 758         */
 759        armv8pmu_disable_event_irq(event);
 760}
 761
 762static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 763{
 764        /* Enable all counters */
 765        armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 766}
 767
 768static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 769{
 770        /* Disable all counters */
 771        armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 772}
 773
 774static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
 775{
 776        u32 pmovsr;
 777        struct perf_sample_data data;
 778        struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 779        struct pt_regs *regs;
 780        int idx;
 781
 782        /*
 783         * Get and reset the IRQ flags
 784         */
 785        pmovsr = armv8pmu_getreset_flags();
 786
 787        /*
 788         * Did an overflow occur?
 789         */
 790        if (!armv8pmu_has_overflowed(pmovsr))
 791                return IRQ_NONE;
 792
 793        /*
 794         * Handle the counter(s) overflow(s)
 795         */
 796        regs = get_irq_regs();
 797
 798        /*
 799         * Stop the PMU while processing the counter overflows
 800         * to prevent skews in group events.
 801         */
 802        armv8pmu_stop(cpu_pmu);
 803        for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 804                struct perf_event *event = cpuc->events[idx];
 805                struct hw_perf_event *hwc;
 806
 807                /* Ignore if we don't have an event. */
 808                if (!event)
 809                        continue;
 810
 811                /*
 812                 * We have a single interrupt for all counters. Check that
 813                 * each counter has overflowed before we process it.
 814                 */
 815                if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 816                        continue;
 817
 818                hwc = &event->hw;
 819                armpmu_event_update(event);
 820                perf_sample_data_init(&data, 0, hwc->last_period);
 821                if (!armpmu_event_set_period(event))
 822                        continue;
 823
 824                /*
 825                 * Perf event overflow will queue the processing of the event as
 826                 * an irq_work which will be taken care of in the handling of
 827                 * IPI_IRQ_WORK.
 828                 */
 829                if (perf_event_overflow(event, &data, regs))
 830                        cpu_pmu->disable(event);
 831        }
 832        armv8pmu_start(cpu_pmu);
 833
 834        return IRQ_HANDLED;
 835}
 836
 837static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
 838                                    struct arm_pmu *cpu_pmu)
 839{
 840        int idx;
 841
 842        for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; idx++) {
 843                if (!test_and_set_bit(idx, cpuc->used_mask))
 844                        return idx;
 845        }
 846        return -EAGAIN;
 847}
 848
 849static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
 850                                   struct arm_pmu *cpu_pmu)
 851{
 852        int idx;
 853
 854        /*
 855         * Chaining requires two consecutive event counters, where
 856         * the lower idx must be even.
 857         */
 858        for (idx = ARMV8_IDX_COUNTER0 + 1; idx < cpu_pmu->num_events; idx += 2) {
 859                if (!test_and_set_bit(idx, cpuc->used_mask)) {
 860                        /* Check if the preceding even counter is available */
 861                        if (!test_and_set_bit(idx - 1, cpuc->used_mask))
 862                                return idx;
 863                        /* Release the Odd counter */
 864                        clear_bit(idx, cpuc->used_mask);
 865                }
 866        }
 867        return -EAGAIN;
 868}
 869
 870static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 871                                  struct perf_event *event)
 872{
 873        struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 874        struct hw_perf_event *hwc = &event->hw;
 875        unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 876
 877        /* Always prefer to place a cycle counter into the cycle counter. */
 878        if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 879                if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 880                        return ARMV8_IDX_CYCLE_COUNTER;
 881        }
 882
 883        /*
 884         * Otherwise use events counters
 885         */
 886        if (armv8pmu_event_is_64bit(event) &&
 887            !armv8pmu_has_long_event(cpu_pmu))
 888                return  armv8pmu_get_chain_idx(cpuc, cpu_pmu);
 889        else
 890                return armv8pmu_get_single_idx(cpuc, cpu_pmu);
 891}
 892
 893static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
 894                                     struct perf_event *event)
 895{
 896        int idx = event->hw.idx;
 897
 898        clear_bit(idx, cpuc->used_mask);
 899        if (armv8pmu_event_is_chained(event))
 900                clear_bit(idx - 1, cpuc->used_mask);
 901}
 902
 903/*
 904 * Add an event filter to a given event.
 905 */
 906static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 907                                     struct perf_event_attr *attr)
 908{
 909        unsigned long config_base = 0;
 910
 911        if (attr->exclude_idle)
 912                return -EPERM;
 913
 914        /*
 915         * If we're running in hyp mode, then we *are* the hypervisor.
 916         * Therefore we ignore exclude_hv in this configuration, since
 917         * there's no hypervisor to sample anyway. This is consistent
 918         * with other architectures (x86 and Power).
 919         */
 920        if (is_kernel_in_hyp_mode()) {
 921                if (!attr->exclude_kernel && !attr->exclude_host)
 922                        config_base |= ARMV8_PMU_INCLUDE_EL2;
 923                if (attr->exclude_guest)
 924                        config_base |= ARMV8_PMU_EXCLUDE_EL1;
 925                if (attr->exclude_host)
 926                        config_base |= ARMV8_PMU_EXCLUDE_EL0;
 927        } else {
 928                if (!attr->exclude_hv && !attr->exclude_host)
 929                        config_base |= ARMV8_PMU_INCLUDE_EL2;
 930        }
 931
 932        /*
 933         * Filter out !VHE kernels and guest kernels
 934         */
 935        if (attr->exclude_kernel)
 936                config_base |= ARMV8_PMU_EXCLUDE_EL1;
 937
 938        if (attr->exclude_user)
 939                config_base |= ARMV8_PMU_EXCLUDE_EL0;
 940
 941        /*
 942         * Install the filter into config_base as this is used to
 943         * construct the event type.
 944         */
 945        event->config_base = config_base;
 946
 947        return 0;
 948}
 949
 950static int armv8pmu_filter_match(struct perf_event *event)
 951{
 952        unsigned long evtype = event->hw.config_base & ARMV8_PMU_EVTYPE_EVENT;
 953        return evtype != ARMV8_PMUV3_PERFCTR_CHAIN;
 954}
 955
 956static void armv8pmu_reset(void *info)
 957{
 958        struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 959        u32 pmcr;
 960
 961        /* The counter and interrupt enable registers are unknown at reset. */
 962        armv8pmu_disable_counter(U32_MAX);
 963        armv8pmu_disable_intens(U32_MAX);
 964
 965        /* Clear the counters we flip at guest entry/exit */
 966        kvm_clr_pmu_events(U32_MAX);
 967
 968        /*
 969         * Initialize & Reset PMNC. Request overflow interrupt for
 970         * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 971         */
 972        pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
 973
 974        /* Enable long event counter support where available */
 975        if (armv8pmu_has_long_event(cpu_pmu))
 976                pmcr |= ARMV8_PMU_PMCR_LP;
 977
 978        armv8pmu_pmcr_write(pmcr);
 979}
 980
 981static int __armv8_pmuv3_map_event(struct perf_event *event,
 982                                   const unsigned (*extra_event_map)
 983                                                  [PERF_COUNT_HW_MAX],
 984                                   const unsigned (*extra_cache_map)
 985                                                  [PERF_COUNT_HW_CACHE_MAX]
 986                                                  [PERF_COUNT_HW_CACHE_OP_MAX]
 987                                                  [PERF_COUNT_HW_CACHE_RESULT_MAX])
 988{
 989        int hw_event_id;
 990        struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 991
 992        hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
 993                                       &armv8_pmuv3_perf_cache_map,
 994                                       ARMV8_PMU_EVTYPE_EVENT);
 995
 996        if (armv8pmu_event_is_64bit(event))
 997                event->hw.flags |= ARMPMU_EVT_64BIT;
 998
 999        /* Only expose micro/arch events supported by this PMU */
1000        if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
1001            && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
1002                return hw_event_id;
1003        }
1004
1005        return armpmu_map_event(event, extra_event_map, extra_cache_map,
1006                                ARMV8_PMU_EVTYPE_EVENT);
1007}
1008
1009static int armv8_pmuv3_map_event(struct perf_event *event)
1010{
1011        return __armv8_pmuv3_map_event(event, NULL, NULL);
1012}
1013
1014static int armv8_a53_map_event(struct perf_event *event)
1015{
1016        return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
1017}
1018
1019static int armv8_a57_map_event(struct perf_event *event)
1020{
1021        return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
1022}
1023
1024static int armv8_a73_map_event(struct perf_event *event)
1025{
1026        return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1027}
1028
1029static int armv8_thunder_map_event(struct perf_event *event)
1030{
1031        return __armv8_pmuv3_map_event(event, NULL,
1032                                       &armv8_thunder_perf_cache_map);
1033}
1034
1035static int armv8_vulcan_map_event(struct perf_event *event)
1036{
1037        return __armv8_pmuv3_map_event(event, NULL,
1038                                       &armv8_vulcan_perf_cache_map);
1039}
1040
1041struct armv8pmu_probe_info {
1042        struct arm_pmu *pmu;
1043        bool present;
1044};
1045
1046static void __armv8pmu_probe_pmu(void *info)
1047{
1048        struct armv8pmu_probe_info *probe = info;
1049        struct arm_pmu *cpu_pmu = probe->pmu;
1050        u64 dfr0;
1051        u64 pmceid_raw[2];
1052        u32 pmceid[2];
1053        int pmuver;
1054
1055        dfr0 = read_sysreg(id_aa64dfr0_el1);
1056        pmuver = cpuid_feature_extract_unsigned_field(dfr0,
1057                        ID_AA64DFR0_PMUVER_SHIFT);
1058        if (pmuver == 0xf || pmuver == 0)
1059                return;
1060
1061        cpu_pmu->pmuver = pmuver;
1062        probe->present = true;
1063
1064        /* Read the nb of CNTx counters supported from PMNC */
1065        cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
1066                & ARMV8_PMU_PMCR_N_MASK;
1067
1068        /* Add the CPU cycles counter */
1069        cpu_pmu->num_events += 1;
1070
1071        pmceid[0] = pmceid_raw[0] = read_sysreg(pmceid0_el0);
1072        pmceid[1] = pmceid_raw[1] = read_sysreg(pmceid1_el0);
1073
1074        bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1075                             pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1076
1077        pmceid[0] = pmceid_raw[0] >> 32;
1078        pmceid[1] = pmceid_raw[1] >> 32;
1079
1080        bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1081                             pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1082
1083        /* store PMMIR_EL1 register for sysfs */
1084        if (pmuver >= ID_AA64DFR0_PMUVER_8_4 && (pmceid_raw[1] & BIT(31)))
1085                cpu_pmu->reg_pmmir = read_cpuid(PMMIR_EL1);
1086        else
1087                cpu_pmu->reg_pmmir = 0;
1088}
1089
1090static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1091{
1092        struct armv8pmu_probe_info probe = {
1093                .pmu = cpu_pmu,
1094                .present = false,
1095        };
1096        int ret;
1097
1098        ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1099                                    __armv8pmu_probe_pmu,
1100                                    &probe, 1);
1101        if (ret)
1102                return ret;
1103
1104        return probe.present ? 0 : -ENODEV;
1105}
1106
1107static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1108                          int (*map_event)(struct perf_event *event),
1109                          const struct attribute_group *events,
1110                          const struct attribute_group *format,
1111                          const struct attribute_group *caps)
1112{
1113        int ret = armv8pmu_probe_pmu(cpu_pmu);
1114        if (ret)
1115                return ret;
1116
1117        cpu_pmu->handle_irq             = armv8pmu_handle_irq;
1118        cpu_pmu->enable                 = armv8pmu_enable_event;
1119        cpu_pmu->disable                = armv8pmu_disable_event;
1120        cpu_pmu->read_counter           = armv8pmu_read_counter;
1121        cpu_pmu->write_counter          = armv8pmu_write_counter;
1122        cpu_pmu->get_event_idx          = armv8pmu_get_event_idx;
1123        cpu_pmu->clear_event_idx        = armv8pmu_clear_event_idx;
1124        cpu_pmu->start                  = armv8pmu_start;
1125        cpu_pmu->stop                   = armv8pmu_stop;
1126        cpu_pmu->reset                  = armv8pmu_reset;
1127        cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1128        cpu_pmu->filter_match           = armv8pmu_filter_match;
1129
1130        cpu_pmu->name                   = name;
1131        cpu_pmu->map_event              = map_event;
1132        cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
1133                        events : &armv8_pmuv3_events_attr_group;
1134        cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
1135                        format : &armv8_pmuv3_format_attr_group;
1136        cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ?
1137                        caps : &armv8_pmuv3_caps_attr_group;
1138
1139        return 0;
1140}
1141
1142static int armv8_pmu_init_nogroups(struct arm_pmu *cpu_pmu, char *name,
1143                                   int (*map_event)(struct perf_event *event))
1144{
1145        return armv8_pmu_init(cpu_pmu, name, map_event, NULL, NULL, NULL);
1146}
1147
1148static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
1149{
1150        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_pmuv3",
1151                                       armv8_pmuv3_map_event);
1152}
1153
1154static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
1155{
1156        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a34",
1157                                       armv8_pmuv3_map_event);
1158}
1159
1160static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
1161{
1162        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a35",
1163                                       armv8_a53_map_event);
1164}
1165
1166static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1167{
1168        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a53",
1169                                       armv8_a53_map_event);
1170}
1171
1172static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
1173{
1174        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a55",
1175                                       armv8_pmuv3_map_event);
1176}
1177
1178static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1179{
1180        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a57",
1181                                       armv8_a57_map_event);
1182}
1183
1184static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
1185{
1186        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a65",
1187                                       armv8_pmuv3_map_event);
1188}
1189
1190static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1191{
1192        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a72",
1193                                       armv8_a57_map_event);
1194}
1195
1196static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1197{
1198        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a73",
1199                                       armv8_a73_map_event);
1200}
1201
1202static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
1203{
1204        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a75",
1205                                       armv8_pmuv3_map_event);
1206}
1207
1208static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
1209{
1210        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a76",
1211                                       armv8_pmuv3_map_event);
1212}
1213
1214static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
1215{
1216        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a77",
1217                                       armv8_pmuv3_map_event);
1218}
1219
1220static int armv8_a78_pmu_init(struct arm_pmu *cpu_pmu)
1221{
1222        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cortex_a78",
1223                                       armv8_pmuv3_map_event);
1224}
1225
1226static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
1227{
1228        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_e1",
1229                                       armv8_pmuv3_map_event);
1230}
1231
1232static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
1233{
1234        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_neoverse_n1",
1235                                       armv8_pmuv3_map_event);
1236}
1237
1238static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1239{
1240        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_cavium_thunder",
1241                                       armv8_thunder_map_event);
1242}
1243
1244static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1245{
1246        return armv8_pmu_init_nogroups(cpu_pmu, "armv8_brcm_vulcan",
1247                                       armv8_vulcan_map_event);
1248}
1249
1250static const struct of_device_id armv8_pmu_of_device_ids[] = {
1251        {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
1252        {.compatible = "arm,cortex-a34-pmu",    .data = armv8_a34_pmu_init},
1253        {.compatible = "arm,cortex-a35-pmu",    .data = armv8_a35_pmu_init},
1254        {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1255        {.compatible = "arm,cortex-a55-pmu",    .data = armv8_a55_pmu_init},
1256        {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1257        {.compatible = "arm,cortex-a65-pmu",    .data = armv8_a65_pmu_init},
1258        {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1259        {.compatible = "arm,cortex-a73-pmu",    .data = armv8_a73_pmu_init},
1260        {.compatible = "arm,cortex-a75-pmu",    .data = armv8_a75_pmu_init},
1261        {.compatible = "arm,cortex-a76-pmu",    .data = armv8_a76_pmu_init},
1262        {.compatible = "arm,cortex-a77-pmu",    .data = armv8_a77_pmu_init},
1263        {.compatible = "arm,cortex-a78-pmu",    .data = armv8_a78_pmu_init},
1264        {.compatible = "arm,neoverse-e1-pmu",   .data = armv8_e1_pmu_init},
1265        {.compatible = "arm,neoverse-n1-pmu",   .data = armv8_n1_pmu_init},
1266        {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1267        {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1268        {},
1269};
1270
1271static int armv8_pmu_device_probe(struct platform_device *pdev)
1272{
1273        return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1274}
1275
1276static struct platform_driver armv8_pmu_driver = {
1277        .driver         = {
1278                .name   = ARMV8_PMU_PDEV_NAME,
1279                .of_match_table = armv8_pmu_of_device_ids,
1280                .suppress_bind_attrs = true,
1281        },
1282        .probe          = armv8_pmu_device_probe,
1283};
1284
1285static int __init armv8_pmu_driver_init(void)
1286{
1287        if (acpi_disabled)
1288                return platform_driver_register(&armv8_pmu_driver);
1289        else
1290                return arm_pmu_acpi_probe(armv8_pmuv3_init);
1291}
1292device_initcall(armv8_pmu_driver_init)
1293
1294void arch_perf_update_userpage(struct perf_event *event,
1295                               struct perf_event_mmap_page *userpg, u64 now)
1296{
1297        struct clock_read_data *rd;
1298        unsigned int seq;
1299        u64 ns;
1300
1301        userpg->cap_user_time = 0;
1302        userpg->cap_user_time_zero = 0;
1303        userpg->cap_user_time_short = 0;
1304
1305        do {
1306                rd = sched_clock_read_begin(&seq);
1307
1308                if (rd->read_sched_clock != arch_timer_read_counter)
1309                        return;
1310
1311                userpg->time_mult = rd->mult;
1312                userpg->time_shift = rd->shift;
1313                userpg->time_zero = rd->epoch_ns;
1314                userpg->time_cycles = rd->epoch_cyc;
1315                userpg->time_mask = rd->sched_clock_mask;
1316
1317                /*
1318                 * Subtract the cycle base, such that software that
1319                 * doesn't know about cap_user_time_short still 'works'
1320                 * assuming no wraps.
1321                 */
1322                ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1323                userpg->time_zero -= ns;
1324
1325        } while (sched_clock_read_retry(seq));
1326
1327        userpg->time_offset = userpg->time_zero - now;
1328
1329        /*
1330         * time_shift is not expected to be greater than 31 due to
1331         * the original published conversion algorithm shifting a
1332         * 32-bit value (now specifies a 64-bit value) - refer
1333         * perf_event_mmap_page documentation in perf_event.h.
1334         */
1335        if (userpg->time_shift == 32) {
1336                userpg->time_shift = 31;
1337                userpg->time_mult >>= 1;
1338        }
1339
1340        /*
1341         * Internal timekeeping for enabled/running/stopped times
1342         * is always computed with the sched_clock.
1343         */
1344        userpg->cap_user_time = 1;
1345        userpg->cap_user_time_zero = 1;
1346        userpg->cap_user_time_short = 1;
1347}
1348