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63#define pr_fmt(fmt) "CPU features: " fmt
64
65#include <linux/bsearch.h>
66#include <linux/cpumask.h>
67#include <linux/crash_dump.h>
68#include <linux/sort.h>
69#include <linux/stop_machine.h>
70#include <linux/types.h>
71#include <linux/minmax.h>
72#include <linux/mm.h>
73#include <linux/cpu.h>
74#include <linux/kasan.h>
75#include <asm/cpu.h>
76#include <asm/cpufeature.h>
77#include <asm/cpu_ops.h>
78#include <asm/fpsimd.h>
79#include <asm/insn.h>
80#include <asm/kvm_host.h>
81#include <asm/mmu_context.h>
82#include <asm/mte.h>
83#include <asm/processor.h>
84#include <asm/smp.h>
85#include <asm/sysreg.h>
86#include <asm/traps.h>
87#include <asm/virt.h>
88
89
90static unsigned long elf_hwcap __read_mostly;
91
92#ifdef CONFIG_COMPAT
93#define COMPAT_ELF_HWCAP_DEFAULT \
94 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
95 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
96 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
97 COMPAT_HWCAP_LPAE)
98unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
99unsigned int compat_elf_hwcap2 __read_mostly;
100#endif
101
102DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
103EXPORT_SYMBOL(cpu_hwcaps);
104static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
105
106
107DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
108
109bool arm64_use_ng_mappings = false;
110EXPORT_SYMBOL(arm64_use_ng_mappings);
111
112
113
114
115
116static bool __read_mostly allow_mismatched_32bit_el0;
117
118
119
120
121
122DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
123
124
125
126
127
128static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly;
129
130
131
132
133
134
135
136
137
138
139DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
140EXPORT_SYMBOL(arm64_const_caps_ready);
141static inline void finalize_system_capabilities(void)
142{
143 static_branch_enable(&arm64_const_caps_ready);
144}
145
146void dump_cpu_features(void)
147{
148
149 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
150}
151
152DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
153EXPORT_SYMBOL(cpu_hwcap_keys);
154
155#define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
156 { \
157 .sign = SIGNED, \
158 .visible = VISIBLE, \
159 .strict = STRICT, \
160 .type = TYPE, \
161 .shift = SHIFT, \
162 .width = WIDTH, \
163 .safe_val = SAFE_VAL, \
164 }
165
166
167#define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
168 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
169
170
171#define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
172 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
173
174#define ARM64_FTR_END \
175 { \
176 .width = 0, \
177 }
178
179static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
180
181static bool __system_matches_cap(unsigned int n);
182
183
184
185
186
187static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
188 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0),
189 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0),
190 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
191 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
192 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
193 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
194 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
195 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
196 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
197 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
198 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
199 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
200 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
201 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
202 ARM64_FTR_END,
203};
204
205static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
206 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_I8MM_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DGH_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_BF16_SHIFT, 4, 0),
209 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SPECRES_SHIFT, 4, 0),
210 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
211 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
212 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
213 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
214 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
215 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
216 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
217 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
218 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
220 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
222 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
224 ARM64_FTR_END,
225};
226
227static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_MPAM_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SEL2_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
235 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
236 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
237 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
238 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
239 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
240 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
241 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
242 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
243 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
244 ARM64_FTR_END,
245};
246
247static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
248 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MPAMFRAC_SHIFT, 4, 0),
249 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_RASFRAC_SHIFT, 4, 0),
250 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE),
251 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_MTE_SHIFT, 4, ID_AA64PFR1_MTE_NI),
252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI),
254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_BT_SHIFT, 4, 0),
255 ARM64_FTR_END,
256};
257
258static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
259 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
260 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F64MM_SHIFT, 4, 0),
261 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
262 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_F32MM_SHIFT, 4, 0),
263 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
264 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_I8MM_SHIFT, 4, 0),
265 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
266 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
267 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
268 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
269 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
270 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BF16_SHIFT, 4, 0),
271 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
272 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
273 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
274 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
276 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
277 ARM64_FTR_END,
278};
279
280static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
281 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
282 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
284
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299 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
300 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
302
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309 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
310 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
311 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
312
313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
314
315 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
316 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
318
319
320
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322 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
323 ARM64_FTR_END,
324};
325
326static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_ETS_SHIFT, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_TWED_SHIFT, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_XNX_SHIFT, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0),
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
333 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
334 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
335 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
336 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
337 ARM64_FTR_END,
338};
339
340static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
341 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
342 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EVT_SHIFT, 4, 0),
343 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_BBM_SHIFT, 4, 0),
344 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
345 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
346 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IDS_SHIFT, 4, 0),
347 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
348 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_ST_SHIFT, 4, 0),
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_NV_SHIFT, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CCIDX_SHIFT, 4, 0),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
356 ARM64_FTR_END,
357};
358
359static const struct arm64_ftr_bits ftr_ctr[] = {
360 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),
361 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
362 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
363 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
364 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
365 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
366
367
368
369
370
371 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_L1IP_SHIFT, 2, ICACHE_POLICY_VIPT),
372 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
373 ARM64_FTR_END,
374};
375
376static struct arm64_ftr_override __ro_after_init no_override = { };
377
378struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
379 .name = "SYS_CTR_EL0",
380 .ftr_bits = ftr_ctr,
381 .override = &no_override,
382};
383
384static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
385 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_INNERSHR_SHIFT, 4, 0xf),
386 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_FCSE_SHIFT, 4, 0),
387 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_AUXREG_SHIFT, 4, 0),
388 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_TCM_SHIFT, 4, 0),
389 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_SHARELVL_SHIFT, 4, 0),
390 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_OUTERSHR_SHIFT, 4, 0xf),
391 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_PMSA_SHIFT, 4, 0),
392 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_VMSA_SHIFT, 4, 0),
393 ARM64_FTR_END,
394};
395
396static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
397 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_DOUBLELOCK_SHIFT, 4, 0),
398 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
399 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
400 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
401 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
402
403
404
405
406 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
407 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
408 ARM64_FTR_END,
409};
410
411static const struct arm64_ftr_bits ftr_mvfr2[] = {
412 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_FPMISC_SHIFT, 4, 0),
413 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_SIMDMISC_SHIFT, 4, 0),
414 ARM64_FTR_END,
415};
416
417static const struct arm64_ftr_bits ftr_dczid[] = {
418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1),
419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0),
420 ARM64_FTR_END,
421};
422
423static const struct arm64_ftr_bits ftr_gmid[] = {
424 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, SYS_GMID_EL1_BS_SHIFT, 4, 0),
425 ARM64_FTR_END,
426};
427
428static const struct arm64_ftr_bits ftr_id_isar0[] = {
429 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DIVIDE_SHIFT, 4, 0),
430 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_DEBUG_SHIFT, 4, 0),
431 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_COPROC_SHIFT, 4, 0),
432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_CMPBRANCH_SHIFT, 4, 0),
433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITFIELD_SHIFT, 4, 0),
434 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_BITCOUNT_SHIFT, 4, 0),
435 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_SWAP_SHIFT, 4, 0),
436 ARM64_FTR_END,
437};
438
439static const struct arm64_ftr_bits ftr_id_isar5[] = {
440 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
441 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
442 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
443 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
444 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
445 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
446 ARM64_FTR_END,
447};
448
449static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
452 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
453 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
454 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
455 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
456 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_AC2_SHIFT, 4, 0),
457
458
459
460
461
462
463
464 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
465 ARM64_FTR_END,
466};
467
468static const struct arm64_ftr_bits ftr_id_isar4[] = {
469 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SWP_FRAC_SHIFT, 4, 0),
470 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_PSR_M_SHIFT, 4, 0),
471 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SYNCH_PRIM_FRAC_SHIFT, 4, 0),
472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_BARRIER_SHIFT, 4, 0),
473 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_SMC_SHIFT, 4, 0),
474 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WRITEBACK_SHIFT, 4, 0),
475 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_WITHSHIFTS_SHIFT, 4, 0),
476 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_UNPRIV_SHIFT, 4, 0),
477 ARM64_FTR_END,
478};
479
480static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0),
482 ARM64_FTR_END,
483};
484
485static const struct arm64_ftr_bits ftr_id_isar6[] = {
486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_I8MM_SHIFT, 4, 0),
487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_BF16_SHIFT, 4, 0),
488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SPECRES_SHIFT, 4, 0),
489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_SB_SHIFT, 4, 0),
490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_FHM_SHIFT, 4, 0),
491 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_DP_SHIFT, 4, 0),
492 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_JSCVT_SHIFT, 4, 0),
493 ARM64_FTR_END,
494};
495
496static const struct arm64_ftr_bits ftr_id_pfr0[] = {
497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_DIT_SHIFT, 4, 0),
498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_CSV2_SHIFT, 4, 0),
499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE3_SHIFT, 4, 0),
500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE2_SHIFT, 4, 0),
501 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE1_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_STATE0_SHIFT, 4, 0),
503 ARM64_FTR_END,
504};
505
506static const struct arm64_ftr_bits ftr_id_pfr1[] = {
507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GIC_SHIFT, 4, 0),
508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRT_FRAC_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SEC_FRAC_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_GENTIMER_SHIFT, 4, 0),
511 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_VIRTUALIZATION_SHIFT, 4, 0),
512 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_MPROGMOD_SHIFT, 4, 0),
513 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_SECURITY_SHIFT, 4, 0),
514 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_PROGMOD_SHIFT, 4, 0),
515 ARM64_FTR_END,
516};
517
518static const struct arm64_ftr_bits ftr_id_pfr2[] = {
519 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_SSBS_SHIFT, 4, 0),
520 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_CSV3_SHIFT, 4, 0),
521 ARM64_FTR_END,
522};
523
524static const struct arm64_ftr_bits ftr_id_dfr0[] = {
525
526 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_PERFMON_SHIFT, 4, 0xf),
527 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MPROFDBG_SHIFT, 4, 0),
528 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPTRC_SHIFT, 4, 0),
529 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPTRC_SHIFT, 4, 0),
530 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_MMAPDBG_SHIFT, 4, 0),
531 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPSDBG_SHIFT, 4, 0),
532 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_COPDBG_SHIFT, 4, 0),
533 ARM64_FTR_END,
534};
535
536static const struct arm64_ftr_bits ftr_id_dfr1[] = {
537 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
538 ARM64_FTR_END,
539};
540
541static const struct arm64_ftr_bits ftr_zcr[] = {
542 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
543 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),
544 ARM64_FTR_END,
545};
546
547
548
549
550
551
552
553static const struct arm64_ftr_bits ftr_generic_32bits[] = {
554 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
559 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
562 ARM64_FTR_END,
563};
564
565
566static const struct arm64_ftr_bits ftr_single32[] = {
567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
568 ARM64_FTR_END,
569};
570
571static const struct arm64_ftr_bits ftr_raz[] = {
572 ARM64_FTR_END,
573};
574
575#define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \
576 .sys_id = id, \
577 .reg = &(struct arm64_ftr_reg){ \
578 .name = #id, \
579 .override = (ovr), \
580 .ftr_bits = &((table)[0]), \
581 }}
582
583#define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override)
584
585struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;
586struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;
587struct arm64_ftr_override __ro_after_init id_aa64isar1_override;
588
589static const struct __ftr_reg_entry {
590 u32 sys_id;
591 struct arm64_ftr_reg *reg;
592} arm64_ftr_regs[] = {
593
594
595 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
596 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1),
597 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
598 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
599 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
600 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
601 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
602
603
604 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0),
605 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
606 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
607 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
608 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4),
609 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
610 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
611 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6),
612
613
614 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
615 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
616 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
617 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
618 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
619 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
620
621
622 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
623 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,
624 &id_aa64pfr1_override),
625 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
626
627
628 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
629 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
630
631
632 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
633 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
634 &id_aa64isar1_override),
635
636
637 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
638 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1,
639 &id_aa64mmfr1_override),
640 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
641
642
643 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
644
645
646 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid),
647
648
649 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
650 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
651
652
653 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
654};
655
656static int search_cmp_ftr_reg(const void *id, const void *regp)
657{
658 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
659}
660
661
662
663
664
665
666
667
668
669
670
671static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id)
672{
673 const struct __ftr_reg_entry *ret;
674
675 ret = bsearch((const void *)(unsigned long)sys_id,
676 arm64_ftr_regs,
677 ARRAY_SIZE(arm64_ftr_regs),
678 sizeof(arm64_ftr_regs[0]),
679 search_cmp_ftr_reg);
680 if (ret)
681 return ret->reg;
682 return NULL;
683}
684
685
686
687
688
689
690
691
692static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
693{
694 struct arm64_ftr_reg *reg;
695
696 reg = get_arm64_ftr_reg_nowarn(sys_id);
697
698
699
700
701
702 WARN_ON(!reg);
703 return reg;
704}
705
706static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
707 s64 ftr_val)
708{
709 u64 mask = arm64_ftr_mask(ftrp);
710
711 reg &= ~mask;
712 reg |= (ftr_val << ftrp->shift) & mask;
713 return reg;
714}
715
716static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
717 s64 cur)
718{
719 s64 ret = 0;
720
721 switch (ftrp->type) {
722 case FTR_EXACT:
723 ret = ftrp->safe_val;
724 break;
725 case FTR_LOWER_SAFE:
726 ret = min(new, cur);
727 break;
728 case FTR_HIGHER_OR_ZERO_SAFE:
729 if (!cur || !new)
730 break;
731 fallthrough;
732 case FTR_HIGHER_SAFE:
733 ret = max(new, cur);
734 break;
735 default:
736 BUG();
737 }
738
739 return ret;
740}
741
742static void __init sort_ftr_regs(void)
743{
744 unsigned int i;
745
746 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) {
747 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg;
748 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits;
749 unsigned int j = 0;
750
751
752
753
754
755 for (; ftr_bits->width != 0; ftr_bits++, j++) {
756 unsigned int width = ftr_reg->ftr_bits[j].width;
757 unsigned int shift = ftr_reg->ftr_bits[j].shift;
758 unsigned int prev_shift;
759
760 WARN((shift + width) > 64,
761 "%s has invalid feature at shift %d\n",
762 ftr_reg->name, shift);
763
764
765
766
767
768 if (j == 0)
769 continue;
770
771 prev_shift = ftr_reg->ftr_bits[j - 1].shift;
772 WARN((shift + width) > prev_shift,
773 "%s has feature overlap at shift %d\n",
774 ftr_reg->name, shift);
775 }
776
777
778
779
780
781 if (i == 0)
782 continue;
783
784
785
786
787
788 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
789 }
790}
791
792
793
794
795
796
797
798static void init_cpu_ftr_reg(u32 sys_reg, u64 new)
799{
800 u64 val = 0;
801 u64 strict_mask = ~0x0ULL;
802 u64 user_mask = 0;
803 u64 valid_mask = 0;
804
805 const struct arm64_ftr_bits *ftrp;
806 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
807
808 if (!reg)
809 return;
810
811 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
812 u64 ftr_mask = arm64_ftr_mask(ftrp);
813 s64 ftr_new = arm64_ftr_value(ftrp, new);
814 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val);
815
816 if ((ftr_mask & reg->override->mask) == ftr_mask) {
817 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new);
818 char *str = NULL;
819
820 if (ftr_ovr != tmp) {
821
822 reg->override->mask &= ~ftr_mask;
823 reg->override->val &= ~ftr_mask;
824 tmp = ftr_ovr;
825 str = "ignoring override";
826 } else if (ftr_new != tmp) {
827
828 ftr_new = tmp;
829 str = "forced";
830 } else if (ftr_ovr == tmp) {
831
832 str = "already set";
833 }
834
835 if (str)
836 pr_warn("%s[%d:%d]: %s to %llx\n",
837 reg->name,
838 ftrp->shift + ftrp->width - 1,
839 ftrp->shift, str, tmp);
840 } else if ((ftr_mask & reg->override->val) == ftr_mask) {
841 reg->override->val &= ~ftr_mask;
842 pr_warn("%s[%d:%d]: impossible override, ignored\n",
843 reg->name,
844 ftrp->shift + ftrp->width - 1,
845 ftrp->shift);
846 }
847
848 val = arm64_ftr_set_value(ftrp, val, ftr_new);
849
850 valid_mask |= ftr_mask;
851 if (!ftrp->strict)
852 strict_mask &= ~ftr_mask;
853 if (ftrp->visible)
854 user_mask |= ftr_mask;
855 else
856 reg->user_val = arm64_ftr_set_value(ftrp,
857 reg->user_val,
858 ftrp->safe_val);
859 }
860
861 val &= valid_mask;
862
863 reg->sys_val = val;
864 reg->strict_mask = strict_mask;
865 reg->user_mask = user_mask;
866}
867
868extern const struct arm64_cpu_capabilities arm64_errata[];
869static const struct arm64_cpu_capabilities arm64_features[];
870
871static void __init
872init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
873{
874 for (; caps->matches; caps++) {
875 if (WARN(caps->capability >= ARM64_NCAPS,
876 "Invalid capability %d\n", caps->capability))
877 continue;
878 if (WARN(cpu_hwcaps_ptrs[caps->capability],
879 "Duplicate entry for capability %d\n",
880 caps->capability))
881 continue;
882 cpu_hwcaps_ptrs[caps->capability] = caps;
883 }
884}
885
886static void __init init_cpu_hwcaps_indirect_list(void)
887{
888 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
889 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
890}
891
892static void __init setup_boot_cpu_capabilities(void);
893
894static void init_32bit_cpu_features(struct cpuinfo_32bit *info)
895{
896 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
897 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1);
898 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
899 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
900 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
901 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
902 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
903 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
904 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6);
905 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
906 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
907 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
908 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
909 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4);
910 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
911 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
912 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
913 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
914 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
915 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
916 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
917}
918
919void __init init_cpu_features(struct cpuinfo_arm64 *info)
920{
921
922 sort_ftr_regs();
923
924 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
925 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
926 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
927 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
928 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
929 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
930 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
931 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
932 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
933 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
934 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
935 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
936 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
937
938 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
939 init_32bit_cpu_features(&info->aarch32);
940
941 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
942 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
943 sve_init_vq_map();
944 }
945
946 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1))
947 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid);
948
949
950
951
952
953 init_cpu_hwcaps_indirect_list();
954
955
956
957
958
959 setup_boot_cpu_capabilities();
960}
961
962static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
963{
964 const struct arm64_ftr_bits *ftrp;
965
966 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
967 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
968 s64 ftr_new = arm64_ftr_value(ftrp, new);
969
970 if (ftr_cur == ftr_new)
971 continue;
972
973 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
974 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
975 }
976
977}
978
979static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
980{
981 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
982
983 if (!regp)
984 return 0;
985
986 update_cpu_ftr_reg(regp, val);
987 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
988 return 0;
989 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
990 regp->name, boot, cpu, val);
991 return 1;
992}
993
994static void relax_cpu_ftr_reg(u32 sys_id, int field)
995{
996 const struct arm64_ftr_bits *ftrp;
997 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
998
999 if (!regp)
1000 return;
1001
1002 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) {
1003 if (ftrp->shift == field) {
1004 regp->strict_mask &= ~arm64_ftr_mask(ftrp);
1005 break;
1006 }
1007 }
1008
1009
1010 WARN_ON(!ftrp->width);
1011}
1012
1013static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info,
1014 struct cpuinfo_arm64 *boot)
1015{
1016 static bool boot_cpu_32bit_regs_overridden = false;
1017
1018 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden)
1019 return;
1020
1021 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0))
1022 return;
1023
1024 boot->aarch32 = info->aarch32;
1025 init_32bit_cpu_features(&boot->aarch32);
1026 boot_cpu_32bit_regs_overridden = true;
1027}
1028
1029static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info,
1030 struct cpuinfo_32bit *boot)
1031{
1032 int taint = 0;
1033 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1034
1035
1036
1037
1038
1039 if (!id_aa64pfr0_32bit_el1(pfr0)) {
1040 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_SMC_SHIFT);
1041 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRT_FRAC_SHIFT);
1042 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SEC_FRAC_SHIFT);
1043 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_VIRTUALIZATION_SHIFT);
1044 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_SECURITY_SHIFT);
1045 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_PROGMOD_SHIFT);
1046 }
1047
1048 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
1049 info->reg_id_dfr0, boot->reg_id_dfr0);
1050 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu,
1051 info->reg_id_dfr1, boot->reg_id_dfr1);
1052 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
1053 info->reg_id_isar0, boot->reg_id_isar0);
1054 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
1055 info->reg_id_isar1, boot->reg_id_isar1);
1056 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
1057 info->reg_id_isar2, boot->reg_id_isar2);
1058 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
1059 info->reg_id_isar3, boot->reg_id_isar3);
1060 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
1061 info->reg_id_isar4, boot->reg_id_isar4);
1062 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
1063 info->reg_id_isar5, boot->reg_id_isar5);
1064 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu,
1065 info->reg_id_isar6, boot->reg_id_isar6);
1066
1067
1068
1069
1070
1071
1072 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
1073 info->reg_id_mmfr0, boot->reg_id_mmfr0);
1074 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
1075 info->reg_id_mmfr1, boot->reg_id_mmfr1);
1076 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
1077 info->reg_id_mmfr2, boot->reg_id_mmfr2);
1078 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
1079 info->reg_id_mmfr3, boot->reg_id_mmfr3);
1080 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu,
1081 info->reg_id_mmfr4, boot->reg_id_mmfr4);
1082 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
1083 info->reg_id_mmfr5, boot->reg_id_mmfr5);
1084 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
1085 info->reg_id_pfr0, boot->reg_id_pfr0);
1086 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
1087 info->reg_id_pfr1, boot->reg_id_pfr1);
1088 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu,
1089 info->reg_id_pfr2, boot->reg_id_pfr2);
1090 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
1091 info->reg_mvfr0, boot->reg_mvfr0);
1092 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
1093 info->reg_mvfr1, boot->reg_mvfr1);
1094 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
1095 info->reg_mvfr2, boot->reg_mvfr2);
1096
1097 return taint;
1098}
1099
1100
1101
1102
1103
1104
1105void update_cpu_features(int cpu,
1106 struct cpuinfo_arm64 *info,
1107 struct cpuinfo_arm64 *boot)
1108{
1109 int taint = 0;
1110
1111
1112
1113
1114
1115
1116 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
1117 info->reg_ctr, boot->reg_ctr);
1118
1119
1120
1121
1122
1123
1124 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
1125 info->reg_dczid, boot->reg_dczid);
1126
1127
1128 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
1129 info->reg_cntfrq, boot->reg_cntfrq);
1130
1131
1132
1133
1134
1135
1136
1137 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
1138 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
1139 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
1140 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
1141
1142
1143
1144
1145 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
1146 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
1147 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
1148 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
1149
1150
1151
1152
1153
1154
1155 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
1156 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
1157 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
1158 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
1159 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
1160 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
1161
1162 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
1163 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
1164 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
1165 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
1166
1167 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
1168 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
1169
1170 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
1171 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
1172 info->reg_zcr, boot->reg_zcr);
1173
1174
1175 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
1176 !system_capabilities_finalized())
1177 sve_update_vq_map();
1178 }
1179
1180
1181
1182
1183
1184
1185 if (IS_ENABLED(CONFIG_ARM64_MTE) &&
1186 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) {
1187 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu,
1188 info->reg_gmid, boot->reg_gmid);
1189 }
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
1200 lazy_init_32bit_cpu_features(info, boot);
1201 taint |= update_32bit_cpu_features(cpu, &info->aarch32,
1202 &boot->aarch32);
1203 }
1204
1205
1206
1207
1208
1209 if (taint) {
1210 pr_warn_once("Unsupported CPU feature variation detected.\n");
1211 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1212 }
1213}
1214
1215u64 read_sanitised_ftr_reg(u32 id)
1216{
1217 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
1218
1219 if (!regp)
1220 return 0;
1221 return regp->sys_val;
1222}
1223EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg);
1224
1225#define read_sysreg_case(r) \
1226 case r: val = read_sysreg_s(r); break;
1227
1228
1229
1230
1231
1232u64 __read_sysreg_by_encoding(u32 sys_id)
1233{
1234 struct arm64_ftr_reg *regp;
1235 u64 val;
1236
1237 switch (sys_id) {
1238 read_sysreg_case(SYS_ID_PFR0_EL1);
1239 read_sysreg_case(SYS_ID_PFR1_EL1);
1240 read_sysreg_case(SYS_ID_PFR2_EL1);
1241 read_sysreg_case(SYS_ID_DFR0_EL1);
1242 read_sysreg_case(SYS_ID_DFR1_EL1);
1243 read_sysreg_case(SYS_ID_MMFR0_EL1);
1244 read_sysreg_case(SYS_ID_MMFR1_EL1);
1245 read_sysreg_case(SYS_ID_MMFR2_EL1);
1246 read_sysreg_case(SYS_ID_MMFR3_EL1);
1247 read_sysreg_case(SYS_ID_MMFR4_EL1);
1248 read_sysreg_case(SYS_ID_MMFR5_EL1);
1249 read_sysreg_case(SYS_ID_ISAR0_EL1);
1250 read_sysreg_case(SYS_ID_ISAR1_EL1);
1251 read_sysreg_case(SYS_ID_ISAR2_EL1);
1252 read_sysreg_case(SYS_ID_ISAR3_EL1);
1253 read_sysreg_case(SYS_ID_ISAR4_EL1);
1254 read_sysreg_case(SYS_ID_ISAR5_EL1);
1255 read_sysreg_case(SYS_ID_ISAR6_EL1);
1256 read_sysreg_case(SYS_MVFR0_EL1);
1257 read_sysreg_case(SYS_MVFR1_EL1);
1258 read_sysreg_case(SYS_MVFR2_EL1);
1259
1260 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
1261 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
1262 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
1263 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
1264 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
1265 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
1266 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
1267 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
1268 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
1269 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
1270
1271 read_sysreg_case(SYS_CNTFRQ_EL0);
1272 read_sysreg_case(SYS_CTR_EL0);
1273 read_sysreg_case(SYS_DCZID_EL0);
1274
1275 default:
1276 BUG();
1277 return 0;
1278 }
1279
1280 regp = get_arm64_ftr_reg(sys_id);
1281 if (regp) {
1282 val &= ~regp->override->mask;
1283 val |= (regp->override->val & regp->override->mask);
1284 }
1285
1286 return val;
1287}
1288
1289#include <linux/irqchip/arm-gic-v3.h>
1290
1291static bool
1292feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
1293{
1294 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
1295
1296 return val >= entry->min_field_value;
1297}
1298
1299static bool
1300has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
1301{
1302 u64 val;
1303
1304 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1305 if (scope == SCOPE_SYSTEM)
1306 val = read_sanitised_ftr_reg(entry->sys_reg);
1307 else
1308 val = __read_sysreg_by_encoding(entry->sys_reg);
1309
1310 return feature_matches(val, entry);
1311}
1312
1313const struct cpumask *system_32bit_el0_cpumask(void)
1314{
1315 if (!system_supports_32bit_el0())
1316 return cpu_none_mask;
1317
1318 if (static_branch_unlikely(&arm64_mismatched_32bit_el0))
1319 return cpu_32bit_el0_mask;
1320
1321 return cpu_possible_mask;
1322}
1323
1324static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope)
1325{
1326 if (!has_cpuid_feature(entry, scope))
1327 return allow_mismatched_32bit_el0;
1328
1329 if (scope == SCOPE_SYSTEM)
1330 pr_info("detected: 32-bit EL0 Support\n");
1331
1332 return true;
1333}
1334
1335static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
1336{
1337 bool has_sre;
1338
1339 if (!has_cpuid_feature(entry, scope))
1340 return false;
1341
1342 has_sre = gic_enable_sre();
1343 if (!has_sre)
1344 pr_warn_once("%s present but disabled by higher exception level\n",
1345 entry->desc);
1346
1347 return has_sre;
1348}
1349
1350static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
1351{
1352 u32 midr = read_cpuid_id();
1353
1354
1355 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
1356 MIDR_CPU_VAR_REV(0, 0),
1357 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
1358}
1359
1360static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
1361{
1362 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1363
1364 return cpuid_feature_extract_signed_field(pfr0,
1365 ID_AA64PFR0_FP_SHIFT) < 0;
1366}
1367
1368static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
1369 int scope)
1370{
1371 u64 ctr;
1372
1373 if (scope == SCOPE_SYSTEM)
1374 ctr = arm64_ftr_reg_ctrel0.sys_val;
1375 else
1376 ctr = read_cpuid_effective_cachetype();
1377
1378 return ctr & BIT(CTR_IDC_SHIFT);
1379}
1380
1381static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
1382{
1383
1384
1385
1386
1387
1388
1389 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
1390 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
1391}
1392
1393static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
1394 int scope)
1395{
1396 u64 ctr;
1397
1398 if (scope == SCOPE_SYSTEM)
1399 ctr = arm64_ftr_reg_ctrel0.sys_val;
1400 else
1401 ctr = read_cpuid_cachetype();
1402
1403 return ctr & BIT(CTR_DIC_SHIFT);
1404}
1405
1406static bool __maybe_unused
1407has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
1408{
1409
1410
1411
1412
1413
1414 if (is_kdump_kernel())
1415 return false;
1416
1417 if (cpus_have_const_cap(ARM64_WORKAROUND_NVIDIA_CARMEL_CNP))
1418 return false;
1419
1420 return has_cpuid_feature(entry, scope);
1421}
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432bool kaslr_requires_kpti(void)
1433{
1434 if (!IS_ENABLED(CONFIG_RANDOMIZE_BASE))
1435 return false;
1436
1437
1438
1439
1440
1441 if (IS_ENABLED(CONFIG_ARM64_E0PD)) {
1442 u64 mmfr2 = read_sysreg_s(SYS_ID_AA64MMFR2_EL1);
1443 if (cpuid_feature_extract_unsigned_field(mmfr2,
1444 ID_AA64MMFR2_E0PD_SHIFT))
1445 return false;
1446 }
1447
1448
1449
1450
1451
1452 if (IS_ENABLED(CONFIG_CAVIUM_ERRATUM_27456)) {
1453 extern const struct midr_range cavium_erratum_27456_cpus[];
1454
1455 if (is_midr_in_range_list(read_cpuid_id(),
1456 cavium_erratum_27456_cpus))
1457 return false;
1458 }
1459
1460 return kaslr_offset() > 0;
1461}
1462
1463static bool __meltdown_safe = true;
1464static int __kpti_forced;
1465
1466static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
1467 int scope)
1468{
1469
1470 static const struct midr_range kpti_safe_list[] = {
1471 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
1472 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
1473 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
1474 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
1475 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
1476 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1477 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
1478 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
1479 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
1480 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
1481 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
1482 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),
1483 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),
1484 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),
1485 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),
1486 { }
1487 };
1488 char const *str = "kpti command line option";
1489 bool meltdown_safe;
1490
1491 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1492
1493
1494 if (has_cpuid_feature(entry, scope))
1495 meltdown_safe = true;
1496
1497 if (!meltdown_safe)
1498 __meltdown_safe = false;
1499
1500
1501
1502
1503
1504
1505 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1506 str = "ARM64_WORKAROUND_CAVIUM_27456";
1507 __kpti_forced = -1;
1508 }
1509
1510
1511 if (kaslr_requires_kpti()) {
1512 if (!__kpti_forced) {
1513 str = "KASLR";
1514 __kpti_forced = 1;
1515 }
1516 }
1517
1518 if (cpu_mitigations_off() && !__kpti_forced) {
1519 str = "mitigations=off";
1520 __kpti_forced = -1;
1521 }
1522
1523 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1524 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1525 return false;
1526 }
1527
1528
1529 if (__kpti_forced) {
1530 pr_info_once("kernel page table isolation forced %s by %s\n",
1531 __kpti_forced > 0 ? "ON" : "OFF", str);
1532 return __kpti_forced > 0;
1533 }
1534
1535 return !meltdown_safe;
1536}
1537
1538#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1539static void __nocfi
1540kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1541{
1542 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1543 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1544 kpti_remap_fn *remap_fn;
1545
1546 int cpu = smp_processor_id();
1547
1548
1549
1550
1551
1552
1553 if (arm64_use_ng_mappings)
1554 return;
1555
1556 remap_fn = (void *)__pa_symbol(function_nocfi(idmap_kpti_install_ng_mappings));
1557
1558 cpu_install_idmap();
1559 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1560 cpu_uninstall_idmap();
1561
1562 if (!cpu)
1563 arm64_use_ng_mappings = true;
1564
1565 return;
1566}
1567#else
1568static void
1569kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1570{
1571}
1572#endif
1573
1574static int __init parse_kpti(char *str)
1575{
1576 bool enabled;
1577 int ret = strtobool(str, &enabled);
1578
1579 if (ret)
1580 return ret;
1581
1582 __kpti_forced = enabled ? 1 : -1;
1583 return 0;
1584}
1585early_param("kpti", parse_kpti);
1586
1587#ifdef CONFIG_ARM64_HW_AFDBM
1588static inline void __cpu_enable_hw_dbm(void)
1589{
1590 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1591
1592 write_sysreg(tcr, tcr_el1);
1593 isb();
1594 local_flush_tlb_all();
1595}
1596
1597static bool cpu_has_broken_dbm(void)
1598{
1599
1600 static const struct midr_range cpus[] = {
1601#ifdef CONFIG_ARM64_ERRATUM_1024718
1602 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1603
1604 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
1605#endif
1606 {},
1607 };
1608
1609 return is_midr_in_range_list(read_cpuid_id(), cpus);
1610}
1611
1612static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1613{
1614 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1615 !cpu_has_broken_dbm();
1616}
1617
1618static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1619{
1620 if (cpu_can_use_dbm(cap))
1621 __cpu_enable_hw_dbm();
1622}
1623
1624static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1625 int __unused)
1626{
1627 static bool detected = false;
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645 if (!detected && cpu_can_use_dbm(cap)) {
1646 detected = true;
1647 pr_info("detected: Hardware dirty bit management\n");
1648 }
1649
1650 return true;
1651}
1652
1653#endif
1654
1655#ifdef CONFIG_ARM64_AMU_EXTN
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666static struct cpumask amu_cpus __read_mostly;
1667
1668bool cpu_has_amu_feat(int cpu)
1669{
1670 return cpumask_test_cpu(cpu, &amu_cpus);
1671}
1672
1673int get_cpu_with_amu_feat(void)
1674{
1675 return cpumask_any(&amu_cpus);
1676}
1677
1678static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1679{
1680 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1681 pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1682 smp_processor_id());
1683 cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1684 update_freq_counters_refs();
1685 }
1686}
1687
1688static bool has_amu(const struct arm64_cpu_capabilities *cap,
1689 int __unused)
1690{
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704 return true;
1705}
1706#else
1707int get_cpu_with_amu_feat(void)
1708{
1709 return nr_cpu_ids;
1710}
1711#endif
1712
1713static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1714{
1715 return is_kernel_in_hyp_mode();
1716}
1717
1718static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1719{
1720
1721
1722
1723
1724
1725
1726
1727
1728 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1729 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1730}
1731
1732static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1733{
1734 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1735
1736
1737 WARN_ON(val & (7 << 27 | 7 << 21));
1738}
1739
1740#ifdef CONFIG_ARM64_PAN
1741static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1742{
1743
1744
1745
1746
1747 WARN_ON_ONCE(in_interrupt());
1748
1749 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1750 set_pstate_pan(1);
1751}
1752#endif
1753
1754#ifdef CONFIG_ARM64_RAS_EXTN
1755static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1756{
1757
1758 write_sysreg_s(0, SYS_DISR_EL1);
1759}
1760#endif
1761
1762#ifdef CONFIG_ARM64_PTR_AUTH
1763static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope)
1764{
1765 int boot_val, sec_val;
1766
1767
1768 WARN_ON(scope == SCOPE_SYSTEM);
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg),
1780 entry->field_pos, entry->sign);
1781 if (scope & SCOPE_BOOT_CPU)
1782 return boot_val >= entry->min_field_value;
1783
1784 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg),
1785 entry->field_pos, entry->sign);
1786 return sec_val == boot_val;
1787}
1788
1789static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry,
1790 int scope)
1791{
1792 return has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH], scope) ||
1793 has_address_auth_cpucap(cpu_hwcaps_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope);
1794}
1795
1796static bool has_generic_auth(const struct arm64_cpu_capabilities *entry,
1797 int __unused)
1798{
1799 return __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
1800 __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF);
1801}
1802#endif
1803
1804#ifdef CONFIG_ARM64_E0PD
1805static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap)
1806{
1807 if (this_cpu_has_cap(ARM64_HAS_E0PD))
1808 sysreg_clear_set(tcr_el1, 0, TCR_E0PD1);
1809}
1810#endif
1811
1812#ifdef CONFIG_ARM64_PSEUDO_NMI
1813static bool enable_pseudo_nmi;
1814
1815static int __init early_enable_pseudo_nmi(char *p)
1816{
1817 return strtobool(p, &enable_pseudo_nmi);
1818}
1819early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1820
1821static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1822 int scope)
1823{
1824 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1825}
1826#endif
1827
1828#ifdef CONFIG_ARM64_BTI
1829static void bti_enable(const struct arm64_cpu_capabilities *__unused)
1830{
1831
1832
1833
1834
1835
1836
1837
1838 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1);
1839 isb();
1840}
1841#endif
1842
1843#ifdef CONFIG_ARM64_MTE
1844static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap)
1845{
1846
1847
1848
1849
1850 if (!test_and_set_bit(PG_mte_tagged, &ZERO_PAGE(0)->flags))
1851 mte_clear_page_tags(lm_alias(empty_zero_page));
1852
1853 kasan_init_hw_tags_cpu();
1854}
1855#endif
1856
1857#ifdef CONFIG_KVM
1858static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused)
1859{
1860 if (kvm_get_mode() != KVM_MODE_PROTECTED)
1861 return false;
1862
1863 if (is_kernel_in_hyp_mode()) {
1864 pr_warn("Protected KVM not available with VHE\n");
1865 return false;
1866 }
1867
1868 return true;
1869}
1870#endif
1871
1872
1873static bool
1874cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
1875{
1876 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
1877}
1878
1879static bool
1880cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
1881{
1882 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
1883}
1884
1885static bool
1886cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap)
1887{
1888 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT);
1889}
1890
1891static const struct arm64_cpu_capabilities arm64_features[] = {
1892 {
1893 .desc = "GIC system register CPU interface",
1894 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1895 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1896 .matches = has_useable_gicv3_cpuif,
1897 .sys_reg = SYS_ID_AA64PFR0_EL1,
1898 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1899 .sign = FTR_UNSIGNED,
1900 .min_field_value = 1,
1901 },
1902#ifdef CONFIG_ARM64_PAN
1903 {
1904 .desc = "Privileged Access Never",
1905 .capability = ARM64_HAS_PAN,
1906 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1907 .matches = has_cpuid_feature,
1908 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1909 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1910 .sign = FTR_UNSIGNED,
1911 .min_field_value = 1,
1912 .cpu_enable = cpu_enable_pan,
1913 },
1914#endif
1915#ifdef CONFIG_ARM64_EPAN
1916 {
1917 .desc = "Enhanced Privileged Access Never",
1918 .capability = ARM64_HAS_EPAN,
1919 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1920 .matches = has_cpuid_feature,
1921 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1922 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1923 .sign = FTR_UNSIGNED,
1924 .min_field_value = 3,
1925 },
1926#endif
1927#ifdef CONFIG_ARM64_LSE_ATOMICS
1928 {
1929 .desc = "LSE atomic instructions",
1930 .capability = ARM64_HAS_LSE_ATOMICS,
1931 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1932 .matches = has_cpuid_feature,
1933 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1934 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1935 .sign = FTR_UNSIGNED,
1936 .min_field_value = 2,
1937 },
1938#endif
1939 {
1940 .desc = "Software prefetching using PRFM",
1941 .capability = ARM64_HAS_NO_HW_PREFETCH,
1942 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1943 .matches = has_no_hw_prefetch,
1944 },
1945 {
1946 .desc = "Virtualization Host Extensions",
1947 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1948 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1949 .matches = runs_at_el2,
1950 .cpu_enable = cpu_copy_el2regs,
1951 },
1952 {
1953 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
1954 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1955 .matches = has_32bit_el0,
1956 .sys_reg = SYS_ID_AA64PFR0_EL1,
1957 .sign = FTR_UNSIGNED,
1958 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1959 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1960 },
1961#ifdef CONFIG_KVM
1962 {
1963 .desc = "32-bit EL1 Support",
1964 .capability = ARM64_HAS_32BIT_EL1,
1965 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1966 .matches = has_cpuid_feature,
1967 .sys_reg = SYS_ID_AA64PFR0_EL1,
1968 .sign = FTR_UNSIGNED,
1969 .field_pos = ID_AA64PFR0_EL1_SHIFT,
1970 .min_field_value = ID_AA64PFR0_EL1_32BIT_64BIT,
1971 },
1972 {
1973 .desc = "Protected KVM",
1974 .capability = ARM64_KVM_PROTECTED_MODE,
1975 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1976 .matches = is_kvm_protected_mode,
1977 },
1978#endif
1979 {
1980 .desc = "Kernel page table isolation (KPTI)",
1981 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1982 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1983
1984
1985
1986
1987
1988 .sys_reg = SYS_ID_AA64PFR0_EL1,
1989 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1990 .min_field_value = 1,
1991 .matches = unmap_kernel_at_el0,
1992 .cpu_enable = kpti_install_ng_mappings,
1993 },
1994 {
1995
1996 .capability = ARM64_HAS_NO_FPSIMD,
1997 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1998 .min_field_value = 0,
1999 .matches = has_no_fpsimd,
2000 },
2001#ifdef CONFIG_ARM64_PMEM
2002 {
2003 .desc = "Data cache clean to Point of Persistence",
2004 .capability = ARM64_HAS_DCPOP,
2005 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2006 .matches = has_cpuid_feature,
2007 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2008 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2009 .min_field_value = 1,
2010 },
2011 {
2012 .desc = "Data cache clean to Point of Deep Persistence",
2013 .capability = ARM64_HAS_DCPODP,
2014 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2015 .matches = has_cpuid_feature,
2016 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2017 .sign = FTR_UNSIGNED,
2018 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
2019 .min_field_value = 2,
2020 },
2021#endif
2022#ifdef CONFIG_ARM64_SVE
2023 {
2024 .desc = "Scalable Vector Extension",
2025 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2026 .capability = ARM64_SVE,
2027 .sys_reg = SYS_ID_AA64PFR0_EL1,
2028 .sign = FTR_UNSIGNED,
2029 .field_pos = ID_AA64PFR0_SVE_SHIFT,
2030 .min_field_value = ID_AA64PFR0_SVE,
2031 .matches = has_cpuid_feature,
2032 .cpu_enable = sve_kernel_enable,
2033 },
2034#endif
2035#ifdef CONFIG_ARM64_RAS_EXTN
2036 {
2037 .desc = "RAS Extension Support",
2038 .capability = ARM64_HAS_RAS_EXTN,
2039 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2040 .matches = has_cpuid_feature,
2041 .sys_reg = SYS_ID_AA64PFR0_EL1,
2042 .sign = FTR_UNSIGNED,
2043 .field_pos = ID_AA64PFR0_RAS_SHIFT,
2044 .min_field_value = ID_AA64PFR0_RAS_V1,
2045 .cpu_enable = cpu_clear_disr,
2046 },
2047#endif
2048#ifdef CONFIG_ARM64_AMU_EXTN
2049 {
2050
2051
2052
2053
2054
2055
2056 .capability = ARM64_HAS_AMU_EXTN,
2057 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2058 .matches = has_amu,
2059 .sys_reg = SYS_ID_AA64PFR0_EL1,
2060 .sign = FTR_UNSIGNED,
2061 .field_pos = ID_AA64PFR0_AMU_SHIFT,
2062 .min_field_value = ID_AA64PFR0_AMU,
2063 .cpu_enable = cpu_amu_enable,
2064 },
2065#endif
2066 {
2067 .desc = "Data cache clean to the PoU not required for I/D coherence",
2068 .capability = ARM64_HAS_CACHE_IDC,
2069 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2070 .matches = has_cache_idc,
2071 .cpu_enable = cpu_emulate_effective_ctr,
2072 },
2073 {
2074 .desc = "Instruction cache invalidation not required for I/D coherence",
2075 .capability = ARM64_HAS_CACHE_DIC,
2076 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2077 .matches = has_cache_dic,
2078 },
2079 {
2080 .desc = "Stage-2 Force Write-Back",
2081 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2082 .capability = ARM64_HAS_STAGE2_FWB,
2083 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2084 .sign = FTR_UNSIGNED,
2085 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
2086 .min_field_value = 1,
2087 .matches = has_cpuid_feature,
2088 .cpu_enable = cpu_has_fwb,
2089 },
2090 {
2091 .desc = "ARMv8.4 Translation Table Level",
2092 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2093 .capability = ARM64_HAS_ARMv8_4_TTL,
2094 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2095 .sign = FTR_UNSIGNED,
2096 .field_pos = ID_AA64MMFR2_TTL_SHIFT,
2097 .min_field_value = 1,
2098 .matches = has_cpuid_feature,
2099 },
2100 {
2101 .desc = "TLB range maintenance instructions",
2102 .capability = ARM64_HAS_TLB_RANGE,
2103 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2104 .matches = has_cpuid_feature,
2105 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2106 .field_pos = ID_AA64ISAR0_TLB_SHIFT,
2107 .sign = FTR_UNSIGNED,
2108 .min_field_value = ID_AA64ISAR0_TLB_RANGE,
2109 },
2110#ifdef CONFIG_ARM64_HW_AFDBM
2111 {
2112
2113
2114
2115
2116
2117
2118
2119
2120 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
2121 .capability = ARM64_HW_DBM,
2122 .sys_reg = SYS_ID_AA64MMFR1_EL1,
2123 .sign = FTR_UNSIGNED,
2124 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
2125 .min_field_value = 2,
2126 .matches = has_hw_dbm,
2127 .cpu_enable = cpu_enable_hw_dbm,
2128 },
2129#endif
2130 {
2131 .desc = "CRC32 instructions",
2132 .capability = ARM64_HAS_CRC32,
2133 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2134 .matches = has_cpuid_feature,
2135 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2136 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
2137 .min_field_value = 1,
2138 },
2139 {
2140 .desc = "Speculative Store Bypassing Safe (SSBS)",
2141 .capability = ARM64_SSBS,
2142 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2143 .matches = has_cpuid_feature,
2144 .sys_reg = SYS_ID_AA64PFR1_EL1,
2145 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
2146 .sign = FTR_UNSIGNED,
2147 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
2148 },
2149#ifdef CONFIG_ARM64_CNP
2150 {
2151 .desc = "Common not Private translations",
2152 .capability = ARM64_HAS_CNP,
2153 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2154 .matches = has_useable_cnp,
2155 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2156 .sign = FTR_UNSIGNED,
2157 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
2158 .min_field_value = 1,
2159 .cpu_enable = cpu_enable_cnp,
2160 },
2161#endif
2162 {
2163 .desc = "Speculation barrier (SB)",
2164 .capability = ARM64_HAS_SB,
2165 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2166 .matches = has_cpuid_feature,
2167 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2168 .field_pos = ID_AA64ISAR1_SB_SHIFT,
2169 .sign = FTR_UNSIGNED,
2170 .min_field_value = 1,
2171 },
2172#ifdef CONFIG_ARM64_PTR_AUTH
2173 {
2174 .desc = "Address authentication (architected algorithm)",
2175 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
2176 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2177 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2178 .sign = FTR_UNSIGNED,
2179 .field_pos = ID_AA64ISAR1_APA_SHIFT,
2180 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
2181 .matches = has_address_auth_cpucap,
2182 },
2183 {
2184 .desc = "Address authentication (IMP DEF algorithm)",
2185 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
2186 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2187 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2188 .sign = FTR_UNSIGNED,
2189 .field_pos = ID_AA64ISAR1_API_SHIFT,
2190 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
2191 .matches = has_address_auth_cpucap,
2192 },
2193 {
2194 .capability = ARM64_HAS_ADDRESS_AUTH,
2195 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
2196 .matches = has_address_auth_metacap,
2197 },
2198 {
2199 .desc = "Generic authentication (architected algorithm)",
2200 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
2201 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2202 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2203 .sign = FTR_UNSIGNED,
2204 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
2205 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
2206 .matches = has_cpuid_feature,
2207 },
2208 {
2209 .desc = "Generic authentication (IMP DEF algorithm)",
2210 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
2211 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2212 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2213 .sign = FTR_UNSIGNED,
2214 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
2215 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
2216 .matches = has_cpuid_feature,
2217 },
2218 {
2219 .capability = ARM64_HAS_GENERIC_AUTH,
2220 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2221 .matches = has_generic_auth,
2222 },
2223#endif
2224#ifdef CONFIG_ARM64_PSEUDO_NMI
2225 {
2226
2227
2228
2229 .desc = "IRQ priority masking",
2230 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
2231 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2232 .matches = can_use_gic_priorities,
2233 .sys_reg = SYS_ID_AA64PFR0_EL1,
2234 .field_pos = ID_AA64PFR0_GIC_SHIFT,
2235 .sign = FTR_UNSIGNED,
2236 .min_field_value = 1,
2237 },
2238#endif
2239#ifdef CONFIG_ARM64_E0PD
2240 {
2241 .desc = "E0PD",
2242 .capability = ARM64_HAS_E0PD,
2243 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2244 .sys_reg = SYS_ID_AA64MMFR2_EL1,
2245 .sign = FTR_UNSIGNED,
2246 .field_pos = ID_AA64MMFR2_E0PD_SHIFT,
2247 .matches = has_cpuid_feature,
2248 .min_field_value = 1,
2249 .cpu_enable = cpu_enable_e0pd,
2250 },
2251#endif
2252#ifdef CONFIG_ARCH_RANDOM
2253 {
2254 .desc = "Random Number Generator",
2255 .capability = ARM64_HAS_RNG,
2256 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2257 .matches = has_cpuid_feature,
2258 .sys_reg = SYS_ID_AA64ISAR0_EL1,
2259 .field_pos = ID_AA64ISAR0_RNDR_SHIFT,
2260 .sign = FTR_UNSIGNED,
2261 .min_field_value = 1,
2262 },
2263#endif
2264#ifdef CONFIG_ARM64_BTI
2265 {
2266 .desc = "Branch Target Identification",
2267 .capability = ARM64_BTI,
2268#ifdef CONFIG_ARM64_BTI_KERNEL
2269 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2270#else
2271 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2272#endif
2273 .matches = has_cpuid_feature,
2274 .cpu_enable = bti_enable,
2275 .sys_reg = SYS_ID_AA64PFR1_EL1,
2276 .field_pos = ID_AA64PFR1_BT_SHIFT,
2277 .min_field_value = ID_AA64PFR1_BT_BTI,
2278 .sign = FTR_UNSIGNED,
2279 },
2280#endif
2281#ifdef CONFIG_ARM64_MTE
2282 {
2283 .desc = "Memory Tagging Extension",
2284 .capability = ARM64_MTE,
2285 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2286 .matches = has_cpuid_feature,
2287 .sys_reg = SYS_ID_AA64PFR1_EL1,
2288 .field_pos = ID_AA64PFR1_MTE_SHIFT,
2289 .min_field_value = ID_AA64PFR1_MTE,
2290 .sign = FTR_UNSIGNED,
2291 .cpu_enable = cpu_enable_mte,
2292 },
2293#endif
2294 {
2295 .desc = "RCpc load-acquire (LDAPR)",
2296 .capability = ARM64_HAS_LDAPR,
2297 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2298 .sys_reg = SYS_ID_AA64ISAR1_EL1,
2299 .sign = FTR_UNSIGNED,
2300 .field_pos = ID_AA64ISAR1_LRCPC_SHIFT,
2301 .matches = has_cpuid_feature,
2302 .min_field_value = 1,
2303 },
2304 {},
2305};
2306
2307#define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2308 .matches = has_cpuid_feature, \
2309 .sys_reg = reg, \
2310 .field_pos = field, \
2311 .sign = s, \
2312 .min_field_value = min_value,
2313
2314#define __HWCAP_CAP(name, cap_type, cap) \
2315 .desc = name, \
2316 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
2317 .hwcap_type = cap_type, \
2318 .hwcap = cap, \
2319
2320#define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
2321 { \
2322 __HWCAP_CAP(#cap, cap_type, cap) \
2323 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
2324 }
2325
2326#define HWCAP_MULTI_CAP(list, cap_type, cap) \
2327 { \
2328 __HWCAP_CAP(#cap, cap_type, cap) \
2329 .matches = cpucap_multi_entry_cap_matches, \
2330 .match_list = list, \
2331 }
2332
2333#define HWCAP_CAP_MATCH(match, cap_type, cap) \
2334 { \
2335 __HWCAP_CAP(#cap, cap_type, cap) \
2336 .matches = match, \
2337 }
2338
2339#ifdef CONFIG_ARM64_PTR_AUTH
2340static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
2341 {
2342 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
2343 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
2344 },
2345 {
2346 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
2347 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
2348 },
2349 {},
2350};
2351
2352static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
2353 {
2354 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
2355 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
2356 },
2357 {
2358 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
2359 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
2360 },
2361 {},
2362};
2363#endif
2364
2365static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
2366 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
2367 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
2368 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
2369 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
2370 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
2371 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
2372 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
2373 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
2374 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
2375 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
2376 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
2377 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
2378 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
2379 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
2380 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
2381 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG),
2382 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
2383 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
2384 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
2385 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
2386 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
2387 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
2388 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
2389 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
2390 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
2391 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
2392 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
2393 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
2394 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
2395 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_BF16_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_BF16),
2396 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DGH_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DGH),
2397 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_I8MM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_I8MM),
2398 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
2399#ifdef CONFIG_ARM64_SVE
2400 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
2401 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
2402 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
2403 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
2404 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
2405 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BF16_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BF16, CAP_HWCAP, KERNEL_HWCAP_SVEBF16),
2406 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
2407 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
2408 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_I8MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_I8MM, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM),
2409 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F32MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F32MM, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM),
2410 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_F64MM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_F64MM, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM),
2411#endif
2412 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
2413#ifdef CONFIG_ARM64_BTI
2414 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_BT_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_BT_BTI, CAP_HWCAP, KERNEL_HWCAP_BTI),
2415#endif
2416#ifdef CONFIG_ARM64_PTR_AUTH
2417 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
2418 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
2419#endif
2420#ifdef CONFIG_ARM64_MTE
2421 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
2422#endif
2423 {},
2424};
2425
2426#ifdef CONFIG_COMPAT
2427static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
2428{
2429
2430
2431
2432
2433
2434 u32 mvfr1;
2435
2436 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
2437 if (scope == SCOPE_SYSTEM)
2438 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
2439 else
2440 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
2441
2442 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
2443 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
2444 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
2445}
2446#endif
2447
2448static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
2449#ifdef CONFIG_COMPAT
2450 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
2451 HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
2452
2453 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
2454 HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
2455 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
2456 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
2457 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
2458 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
2459 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
2460#endif
2461 {},
2462};
2463
2464static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2465{
2466 switch (cap->hwcap_type) {
2467 case CAP_HWCAP:
2468 cpu_set_feature(cap->hwcap);
2469 break;
2470#ifdef CONFIG_COMPAT
2471 case CAP_COMPAT_HWCAP:
2472 compat_elf_hwcap |= (u32)cap->hwcap;
2473 break;
2474 case CAP_COMPAT_HWCAP2:
2475 compat_elf_hwcap2 |= (u32)cap->hwcap;
2476 break;
2477#endif
2478 default:
2479 WARN_ON(1);
2480 break;
2481 }
2482}
2483
2484
2485static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
2486{
2487 bool rc;
2488
2489 switch (cap->hwcap_type) {
2490 case CAP_HWCAP:
2491 rc = cpu_have_feature(cap->hwcap);
2492 break;
2493#ifdef CONFIG_COMPAT
2494 case CAP_COMPAT_HWCAP:
2495 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
2496 break;
2497 case CAP_COMPAT_HWCAP2:
2498 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
2499 break;
2500#endif
2501 default:
2502 WARN_ON(1);
2503 rc = false;
2504 }
2505
2506 return rc;
2507}
2508
2509static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
2510{
2511
2512 cpu_set_named_feature(CPUID);
2513 for (; hwcaps->matches; hwcaps++)
2514 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
2515 cap_set_elf_hwcap(hwcaps);
2516}
2517
2518static void update_cpu_capabilities(u16 scope_mask)
2519{
2520 int i;
2521 const struct arm64_cpu_capabilities *caps;
2522
2523 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2524 for (i = 0; i < ARM64_NCAPS; i++) {
2525 caps = cpu_hwcaps_ptrs[i];
2526 if (!caps || !(caps->type & scope_mask) ||
2527 cpus_have_cap(caps->capability) ||
2528 !caps->matches(caps, cpucap_default_scope(caps)))
2529 continue;
2530
2531 if (caps->desc)
2532 pr_info("detected: %s\n", caps->desc);
2533 cpus_set_cap(caps->capability);
2534
2535 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
2536 set_bit(caps->capability, boot_capabilities);
2537 }
2538}
2539
2540
2541
2542
2543
2544static int cpu_enable_non_boot_scope_capabilities(void *__unused)
2545{
2546 int i;
2547 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
2548
2549 for_each_available_cap(i) {
2550 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
2551
2552 if (WARN_ON(!cap))
2553 continue;
2554
2555 if (!(cap->type & non_boot_scope))
2556 continue;
2557
2558 if (cap->cpu_enable)
2559 cap->cpu_enable(cap);
2560 }
2561 return 0;
2562}
2563
2564
2565
2566
2567
2568static void __init enable_cpu_capabilities(u16 scope_mask)
2569{
2570 int i;
2571 const struct arm64_cpu_capabilities *caps;
2572 bool boot_scope;
2573
2574 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2575 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
2576
2577 for (i = 0; i < ARM64_NCAPS; i++) {
2578 unsigned int num;
2579
2580 caps = cpu_hwcaps_ptrs[i];
2581 if (!caps || !(caps->type & scope_mask))
2582 continue;
2583 num = caps->capability;
2584 if (!cpus_have_cap(num))
2585 continue;
2586
2587
2588 static_branch_enable(&cpu_hwcap_keys[num]);
2589
2590 if (boot_scope && caps->cpu_enable)
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600 caps->cpu_enable(caps);
2601 }
2602
2603
2604
2605
2606
2607
2608
2609 if (!boot_scope)
2610 stop_machine(cpu_enable_non_boot_scope_capabilities,
2611 NULL, cpu_online_mask);
2612}
2613
2614
2615
2616
2617
2618
2619static void verify_local_cpu_caps(u16 scope_mask)
2620{
2621 int i;
2622 bool cpu_has_cap, system_has_cap;
2623 const struct arm64_cpu_capabilities *caps;
2624
2625 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
2626
2627 for (i = 0; i < ARM64_NCAPS; i++) {
2628 caps = cpu_hwcaps_ptrs[i];
2629 if (!caps || !(caps->type & scope_mask))
2630 continue;
2631
2632 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
2633 system_has_cap = cpus_have_cap(caps->capability);
2634
2635 if (system_has_cap) {
2636
2637
2638
2639
2640 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
2641 break;
2642
2643
2644
2645
2646
2647
2648 if (caps->cpu_enable)
2649 caps->cpu_enable(caps);
2650 } else {
2651
2652
2653
2654
2655 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
2656 break;
2657 }
2658 }
2659
2660 if (i < ARM64_NCAPS) {
2661 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2662 smp_processor_id(), caps->capability,
2663 caps->desc, system_has_cap, cpu_has_cap);
2664
2665 if (cpucap_panic_on_conflict(caps))
2666 cpu_panic_kernel();
2667 else
2668 cpu_die_early();
2669 }
2670}
2671
2672
2673
2674
2675
2676static void check_early_cpu_features(void)
2677{
2678 verify_cpu_asid_bits();
2679
2680 verify_local_cpu_caps(SCOPE_BOOT_CPU);
2681}
2682
2683static void
2684__verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2685{
2686
2687 for (; caps->matches; caps++)
2688 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2689 pr_crit("CPU%d: missing HWCAP: %s\n",
2690 smp_processor_id(), caps->desc);
2691 cpu_die_early();
2692 }
2693}
2694
2695static void verify_local_elf_hwcaps(void)
2696{
2697 __verify_local_elf_hwcaps(arm64_elf_hwcaps);
2698
2699 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1)))
2700 __verify_local_elf_hwcaps(compat_elf_hwcaps);
2701}
2702
2703static void verify_sve_features(void)
2704{
2705 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2706 u64 zcr = read_zcr_features();
2707
2708 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2709 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2710
2711 if (len < safe_len || sve_verify_vq_map()) {
2712 pr_crit("CPU%d: SVE: vector length support mismatch\n",
2713 smp_processor_id());
2714 cpu_die_early();
2715 }
2716
2717
2718}
2719
2720static void verify_hyp_capabilities(void)
2721{
2722 u64 safe_mmfr1, mmfr0, mmfr1;
2723 int parange, ipa_max;
2724 unsigned int safe_vmid_bits, vmid_bits;
2725
2726 if (!IS_ENABLED(CONFIG_KVM))
2727 return;
2728
2729 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
2730 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
2731 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
2732
2733
2734 safe_vmid_bits = get_vmid_bits(safe_mmfr1);
2735 vmid_bits = get_vmid_bits(mmfr1);
2736 if (vmid_bits < safe_vmid_bits) {
2737 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id());
2738 cpu_die_early();
2739 }
2740
2741
2742 parange = cpuid_feature_extract_unsigned_field(mmfr0,
2743 ID_AA64MMFR0_PARANGE_SHIFT);
2744 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
2745 if (ipa_max < get_kvm_ipa_limit()) {
2746 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());
2747 cpu_die_early();
2748 }
2749}
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759static void verify_local_cpu_capabilities(void)
2760{
2761
2762
2763
2764
2765
2766 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2767 verify_local_elf_hwcaps();
2768
2769 if (system_supports_sve())
2770 verify_sve_features();
2771
2772 if (is_hyp_mode_available())
2773 verify_hyp_capabilities();
2774}
2775
2776void check_local_cpu_capabilities(void)
2777{
2778
2779
2780
2781
2782 check_early_cpu_features();
2783
2784
2785
2786
2787
2788
2789
2790 if (!system_capabilities_finalized())
2791 update_cpu_capabilities(SCOPE_LOCAL_CPU);
2792 else
2793 verify_local_cpu_capabilities();
2794}
2795
2796static void __init setup_boot_cpu_capabilities(void)
2797{
2798
2799 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2800
2801 enable_cpu_capabilities(SCOPE_BOOT_CPU);
2802}
2803
2804bool this_cpu_has_cap(unsigned int n)
2805{
2806 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2807 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2808
2809 if (cap)
2810 return cap->matches(cap, SCOPE_LOCAL_CPU);
2811 }
2812
2813 return false;
2814}
2815
2816
2817
2818
2819
2820
2821
2822static bool __maybe_unused __system_matches_cap(unsigned int n)
2823{
2824 if (n < ARM64_NCAPS) {
2825 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2826
2827 if (cap)
2828 return cap->matches(cap, SCOPE_SYSTEM);
2829 }
2830 return false;
2831}
2832
2833void cpu_set_feature(unsigned int num)
2834{
2835 WARN_ON(num >= MAX_CPU_FEATURES);
2836 elf_hwcap |= BIT(num);
2837}
2838EXPORT_SYMBOL_GPL(cpu_set_feature);
2839
2840bool cpu_have_feature(unsigned int num)
2841{
2842 WARN_ON(num >= MAX_CPU_FEATURES);
2843 return elf_hwcap & BIT(num);
2844}
2845EXPORT_SYMBOL_GPL(cpu_have_feature);
2846
2847unsigned long cpu_get_elf_hwcap(void)
2848{
2849
2850
2851
2852
2853
2854 return lower_32_bits(elf_hwcap);
2855}
2856
2857unsigned long cpu_get_elf_hwcap2(void)
2858{
2859 return upper_32_bits(elf_hwcap);
2860}
2861
2862static void __init setup_system_capabilities(void)
2863{
2864
2865
2866
2867
2868
2869
2870 update_cpu_capabilities(SCOPE_SYSTEM);
2871 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2872}
2873
2874void __init setup_cpu_features(void)
2875{
2876 u32 cwg;
2877
2878 setup_system_capabilities();
2879 setup_elf_hwcaps(arm64_elf_hwcaps);
2880
2881 if (system_supports_32bit_el0())
2882 setup_elf_hwcaps(compat_elf_hwcaps);
2883
2884 if (system_uses_ttbr0_pan())
2885 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2886
2887 sve_setup();
2888 minsigstksz_setup();
2889
2890
2891 finalize_system_capabilities();
2892
2893
2894
2895
2896 cwg = cache_type_cwg();
2897 if (!cwg)
2898 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2899 ARCH_DMA_MINALIGN);
2900}
2901
2902static int enable_mismatched_32bit_el0(unsigned int cpu)
2903{
2904 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
2905 bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0);
2906
2907 if (cpu_32bit) {
2908 cpumask_set_cpu(cpu, cpu_32bit_el0_mask);
2909 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0);
2910 setup_elf_hwcaps(compat_elf_hwcaps);
2911 }
2912
2913 return 0;
2914}
2915
2916static int __init init_32bit_el0_mask(void)
2917{
2918 if (!allow_mismatched_32bit_el0)
2919 return 0;
2920
2921 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL))
2922 return -ENOMEM;
2923
2924 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
2925 "arm64/mismatched_32bit_el0:online",
2926 enable_mismatched_32bit_el0, NULL);
2927}
2928subsys_initcall_sync(init_32bit_el0_mask);
2929
2930static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2931{
2932 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2933}
2934
2935
2936
2937
2938
2939
2940
2941static inline bool __attribute_const__ is_emulated(u32 id)
2942{
2943 return (sys_reg_Op0(id) == 0x3 &&
2944 sys_reg_CRn(id) == 0x0 &&
2945 sys_reg_Op1(id) == 0x0 &&
2946 (sys_reg_CRm(id) == 0 ||
2947 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2948}
2949
2950
2951
2952
2953
2954static inline int emulate_id_reg(u32 id, u64 *valp)
2955{
2956 switch (id) {
2957 case SYS_MIDR_EL1:
2958 *valp = read_cpuid_id();
2959 break;
2960 case SYS_MPIDR_EL1:
2961 *valp = SYS_MPIDR_SAFE_VAL;
2962 break;
2963 case SYS_REVIDR_EL1:
2964
2965 *valp = 0;
2966 break;
2967 default:
2968 return -EINVAL;
2969 }
2970
2971 return 0;
2972}
2973
2974static int emulate_sys_reg(u32 id, u64 *valp)
2975{
2976 struct arm64_ftr_reg *regp;
2977
2978 if (!is_emulated(id))
2979 return -EINVAL;
2980
2981 if (sys_reg_CRm(id) == 0)
2982 return emulate_id_reg(id, valp);
2983
2984 regp = get_arm64_ftr_reg_nowarn(id);
2985 if (regp)
2986 *valp = arm64_ftr_reg_user_value(regp);
2987 else
2988
2989
2990
2991
2992 *valp = 0;
2993 return 0;
2994}
2995
2996int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2997{
2998 int rc;
2999 u64 val;
3000
3001 rc = emulate_sys_reg(sys_reg, &val);
3002 if (!rc) {
3003 pt_regs_write_reg(regs, rt, val);
3004 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
3005 }
3006 return rc;
3007}
3008
3009static int emulate_mrs(struct pt_regs *regs, u32 insn)
3010{
3011 u32 sys_reg, rt;
3012
3013
3014
3015
3016
3017 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
3018 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
3019 return do_emulate_mrs(regs, sys_reg, rt);
3020}
3021
3022static struct undef_hook mrs_hook = {
3023 .instr_mask = 0xffff0000,
3024 .instr_val = 0xd5380000,
3025 .pstate_mask = PSR_AA32_MODE_MASK,
3026 .pstate_val = PSR_MODE_EL0t,
3027 .fn = emulate_mrs,
3028};
3029
3030static int __init enable_mrs_emulation(void)
3031{
3032 register_undef_hook(&mrs_hook);
3033 return 0;
3034}
3035
3036core_initcall(enable_mrs_emulation);
3037
3038enum mitigation_state arm64_get_meltdown_state(void)
3039{
3040 if (__meltdown_safe)
3041 return SPECTRE_UNAFFECTED;
3042
3043 if (arm64_kernel_unmapped_at_el0())
3044 return SPECTRE_MITIGATED;
3045
3046 return SPECTRE_VULNERABLE;
3047}
3048
3049ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
3050 char *buf)
3051{
3052 switch (arm64_get_meltdown_state()) {
3053 case SPECTRE_UNAFFECTED:
3054 return sprintf(buf, "Not affected\n");
3055
3056 case SPECTRE_MITIGATED:
3057 return sprintf(buf, "Mitigation: PTI\n");
3058
3059 default:
3060 return sprintf(buf, "Vulnerable\n");
3061 }
3062}
3063