linux/arch/arm/mach-omap2/powerdomains54xx_data.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * OMAP54XX Power domains framework
   4 *
   5 * Copyright (C) 2013 Texas Instruments, Inc.
   6 *
   7 * Abhijit Pagare (abhijitpagare@ti.com)
   8 * Benoit Cousson (b-cousson@ti.com)
   9 * Paul Walmsley (paul@pwsan.com)
  10 *
  11 * This file is automatically generated from the OMAP hardware databases.
  12 * We respectfully ask that any modifications to this file be coordinated
  13 * with the public linux-omap@vger.kernel.org mailing list and the
  14 * authors above to ensure that the autogeneration scripts are kept
  15 * up-to-date with the file contents.
  16 */
  17
  18#include <linux/kernel.h>
  19#include <linux/init.h>
  20
  21#include "powerdomain.h"
  22
  23#include "prcm-common.h"
  24#include "prcm44xx.h"
  25#include "prm54xx.h"
  26#include "prcm_mpu54xx.h"
  27
  28/* core_54xx_pwrdm: CORE power domain */
  29static struct powerdomain core_54xx_pwrdm = {
  30        .name             = "core_pwrdm",
  31        .voltdm           = { .name = "core" },
  32        .prcm_offs        = OMAP54XX_PRM_CORE_INST,
  33        .prcm_partition   = OMAP54XX_PRM_PARTITION,
  34        .pwrsts           = PWRSTS_RET_ON,
  35        .pwrsts_logic_ret = PWRSTS_RET,
  36        .banks            = 5,
  37        .pwrsts_mem_ret = {
  38                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
  39                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
  40                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
  41                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
  42                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
  43        },
  44        .pwrsts_mem_on  = {
  45                [0] = PWRSTS_OFF_RET,   /* core_nret_bank */
  46                [1] = PWRSTS_OFF_RET,   /* core_ocmram */
  47                [2] = PWRSTS_OFF_RET,   /* core_other_bank */
  48                [3] = PWRSTS_OFF_RET,   /* ipu_l2ram */
  49                [4] = PWRSTS_OFF_RET,   /* ipu_unicache */
  50        },
  51        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  52};
  53
  54/* abe_54xx_pwrdm: Audio back end power domain */
  55static struct powerdomain abe_54xx_pwrdm = {
  56        .name             = "abe_pwrdm",
  57        .voltdm           = { .name = "core" },
  58        .prcm_offs        = OMAP54XX_PRM_ABE_INST,
  59        .prcm_partition   = OMAP54XX_PRM_PARTITION,
  60        .pwrsts           = PWRSTS_OFF_RET_ON,
  61        .pwrsts_logic_ret = PWRSTS_OFF,
  62        .banks            = 2,
  63        .pwrsts_mem_ret = {
  64                [0] = PWRSTS_OFF_RET,   /* aessmem */
  65                [1] = PWRSTS_OFF_RET,   /* periphmem */
  66        },
  67        .pwrsts_mem_on  = {
  68                [0] = PWRSTS_OFF_RET,   /* aessmem */
  69                [1] = PWRSTS_OFF_RET,   /* periphmem */
  70        },
  71        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  72};
  73
  74/* coreaon_54xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
  75static struct powerdomain coreaon_54xx_pwrdm = {
  76        .name             = "coreaon_pwrdm",
  77        .voltdm           = { .name = "core" },
  78        .prcm_offs        = OMAP54XX_PRM_COREAON_INST,
  79        .prcm_partition   = OMAP54XX_PRM_PARTITION,
  80        .pwrsts           = PWRSTS_ON,
  81};
  82
  83/* dss_54xx_pwrdm: Display subsystem power domain */
  84static struct powerdomain dss_54xx_pwrdm = {
  85        .name             = "dss_pwrdm",
  86        .voltdm           = { .name = "core" },
  87        .prcm_offs        = OMAP54XX_PRM_DSS_INST,
  88        .prcm_partition   = OMAP54XX_PRM_PARTITION,
  89        .pwrsts           = PWRSTS_OFF_RET_ON,
  90        .pwrsts_logic_ret = PWRSTS_OFF,
  91        .banks            = 1,
  92        .pwrsts_mem_ret = {
  93                [0] = PWRSTS_OFF_RET,   /* dss_mem */
  94        },
  95        .pwrsts_mem_on  = {
  96                [0] = PWRSTS_OFF_RET,   /* dss_mem */
  97        },
  98        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  99};
 100
 101/* cpu0_54xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 102static struct powerdomain cpu0_54xx_pwrdm = {
 103        .name             = "cpu0_pwrdm",
 104        .voltdm           = { .name = "mpu" },
 105        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C0_INST,
 106        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 107        .pwrsts           = PWRSTS_RET_ON,
 108        .pwrsts_logic_ret = PWRSTS_RET,
 109        .banks            = 1,
 110        .pwrsts_mem_ret = {
 111                [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
 112        },
 113        .pwrsts_mem_on  = {
 114                [0] = PWRSTS_ON,        /* cpu0_l1 */
 115        },
 116};
 117
 118/* cpu1_54xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 119static struct powerdomain cpu1_54xx_pwrdm = {
 120        .name             = "cpu1_pwrdm",
 121        .voltdm           = { .name = "mpu" },
 122        .prcm_offs        = OMAP54XX_PRCM_MPU_PRM_C1_INST,
 123        .prcm_partition   = OMAP54XX_PRCM_MPU_PARTITION,
 124        .pwrsts           = PWRSTS_RET_ON,
 125        .pwrsts_logic_ret = PWRSTS_RET,
 126        .banks            = 1,
 127        .pwrsts_mem_ret = {
 128                [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
 129        },
 130        .pwrsts_mem_on  = {
 131                [0] = PWRSTS_ON,        /* cpu1_l1 */
 132        },
 133};
 134
 135/* emu_54xx_pwrdm: Emulation power domain */
 136static struct powerdomain emu_54xx_pwrdm = {
 137        .name             = "emu_pwrdm",
 138        .voltdm           = { .name = "wkup" },
 139        .prcm_offs        = OMAP54XX_PRM_EMU_INST,
 140        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 141        .pwrsts           = PWRSTS_OFF_ON,
 142        .banks            = 1,
 143        .pwrsts_mem_ret = {
 144                [0] = PWRSTS_OFF_RET,   /* emu_bank */
 145        },
 146        .pwrsts_mem_on  = {
 147                [0] = PWRSTS_OFF_RET,   /* emu_bank */
 148        },
 149};
 150
 151/* mpu_54xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 152static struct powerdomain mpu_54xx_pwrdm = {
 153        .name             = "mpu_pwrdm",
 154        .voltdm           = { .name = "mpu" },
 155        .prcm_offs        = OMAP54XX_PRM_MPU_INST,
 156        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 157        .pwrsts           = PWRSTS_RET_ON,
 158        .pwrsts_logic_ret = PWRSTS_RET,
 159        .banks            = 2,
 160        .pwrsts_mem_ret = {
 161                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
 162                [1] = PWRSTS_RET,       /* mpu_ram */
 163        },
 164        .pwrsts_mem_on  = {
 165                [0] = PWRSTS_OFF_RET,   /* mpu_l2 */
 166                [1] = PWRSTS_OFF_RET,   /* mpu_ram */
 167        },
 168};
 169
 170/* custefuse_54xx_pwrdm: Customer efuse controller power domain */
 171static struct powerdomain custefuse_54xx_pwrdm = {
 172        .name             = "custefuse_pwrdm",
 173        .voltdm           = { .name = "core" },
 174        .prcm_offs        = OMAP54XX_PRM_CUSTEFUSE_INST,
 175        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 176        .pwrsts           = PWRSTS_OFF_ON,
 177        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 178};
 179
 180/* dsp_54xx_pwrdm: Tesla processor power domain */
 181static struct powerdomain dsp_54xx_pwrdm = {
 182        .name             = "dsp_pwrdm",
 183        .voltdm           = { .name = "mm" },
 184        .prcm_offs        = OMAP54XX_PRM_DSP_INST,
 185        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 186        .pwrsts           = PWRSTS_OFF_RET_ON,
 187        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 188        .banks            = 3,
 189        .pwrsts_mem_ret = {
 190                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
 191                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
 192                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
 193        },
 194        .pwrsts_mem_on  = {
 195                [0] = PWRSTS_OFF_RET,   /* dsp_edma */
 196                [1] = PWRSTS_OFF_RET,   /* dsp_l1 */
 197                [2] = PWRSTS_OFF_RET,   /* dsp_l2 */
 198        },
 199        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 200};
 201
 202/* cam_54xx_pwrdm: Camera subsystem power domain */
 203static struct powerdomain cam_54xx_pwrdm = {
 204        .name             = "cam_pwrdm",
 205        .voltdm           = { .name = "core" },
 206        .prcm_offs        = OMAP54XX_PRM_CAM_INST,
 207        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 208        .pwrsts           = PWRSTS_OFF_ON,
 209        .banks            = 1,
 210        .pwrsts_mem_ret = {
 211                [0] = PWRSTS_OFF_RET,   /* cam_mem */
 212        },
 213        .pwrsts_mem_on  = {
 214                [0] = PWRSTS_OFF_RET,   /* cam_mem */
 215        },
 216        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 217};
 218
 219/* l3init_54xx_pwrdm: L3 initators pheripherals power domain  */
 220static struct powerdomain l3init_54xx_pwrdm = {
 221        .name             = "l3init_pwrdm",
 222        .voltdm           = { .name = "core" },
 223        .prcm_offs        = OMAP54XX_PRM_L3INIT_INST,
 224        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 225        .pwrsts           = PWRSTS_RET_ON,
 226        .pwrsts_logic_ret = PWRSTS_OFF_RET,
 227        .banks            = 2,
 228        .pwrsts_mem_ret = {
 229                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
 230                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
 231        },
 232        .pwrsts_mem_on  = {
 233                [0] = PWRSTS_OFF_RET,   /* l3init_bank1 */
 234                [1] = PWRSTS_OFF_RET,   /* l3init_bank2 */
 235        },
 236        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 237};
 238
 239/* gpu_54xx_pwrdm: 3D accelerator power domain */
 240static struct powerdomain gpu_54xx_pwrdm = {
 241        .name             = "gpu_pwrdm",
 242        .voltdm           = { .name = "mm" },
 243        .prcm_offs        = OMAP54XX_PRM_GPU_INST,
 244        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 245        .pwrsts           = PWRSTS_OFF_ON,
 246        .banks            = 1,
 247        .pwrsts_mem_ret = {
 248                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
 249        },
 250        .pwrsts_mem_on  = {
 251                [0] = PWRSTS_OFF_RET,   /* gpu_mem */
 252        },
 253        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 254};
 255
 256/* wkupaon_54xx_pwrdm: Wake-up power domain */
 257static struct powerdomain wkupaon_54xx_pwrdm = {
 258        .name             = "wkupaon_pwrdm",
 259        .voltdm           = { .name = "wkup" },
 260        .prcm_offs        = OMAP54XX_PRM_WKUPAON_INST,
 261        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 262        .pwrsts           = PWRSTS_ON,
 263        .banks            = 1,
 264        .pwrsts_mem_ret = {
 265        },
 266        .pwrsts_mem_on  = {
 267                [0] = PWRSTS_ON,        /* wkup_bank */
 268        },
 269};
 270
 271/* iva_54xx_pwrdm: IVA-HD power domain */
 272static struct powerdomain iva_54xx_pwrdm = {
 273        .name             = "iva_pwrdm",
 274        .voltdm           = { .name = "mm" },
 275        .prcm_offs        = OMAP54XX_PRM_IVA_INST,
 276        .prcm_partition   = OMAP54XX_PRM_PARTITION,
 277        .pwrsts           = PWRSTS_OFF_RET_ON,
 278        .pwrsts_logic_ret = PWRSTS_OFF,
 279        .banks            = 4,
 280        .pwrsts_mem_ret = {
 281                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
 282                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
 283                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
 284                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
 285        },
 286        .pwrsts_mem_on  = {
 287                [0] = PWRSTS_OFF_RET,   /* hwa_mem */
 288                [1] = PWRSTS_OFF_RET,   /* sl2_mem */
 289                [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
 290                [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
 291        },
 292        .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 293};
 294
 295/*
 296 * The following power domains are not under SW control
 297 *
 298 * mpuaon
 299 * mmaon
 300 */
 301
 302/* As powerdomains are added or removed above, this list must also be changed */
 303static struct powerdomain *powerdomains_omap54xx[] __initdata = {
 304        &core_54xx_pwrdm,
 305        &abe_54xx_pwrdm,
 306        &coreaon_54xx_pwrdm,
 307        &dss_54xx_pwrdm,
 308        &cpu0_54xx_pwrdm,
 309        &cpu1_54xx_pwrdm,
 310        &emu_54xx_pwrdm,
 311        &mpu_54xx_pwrdm,
 312        &custefuse_54xx_pwrdm,
 313        &dsp_54xx_pwrdm,
 314        &cam_54xx_pwrdm,
 315        &l3init_54xx_pwrdm,
 316        &gpu_54xx_pwrdm,
 317        &wkupaon_54xx_pwrdm,
 318        &iva_54xx_pwrdm,
 319        NULL
 320};
 321
 322void __init omap54xx_powerdomains_init(void)
 323{
 324        pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
 325        pwrdm_register_pwrdms(powerdomains_omap54xx);
 326        pwrdm_complete_init();
 327}
 328
The original LXR software by the LXR community, this experimental version by lxr@linux.no.