LXR linux/arch/arm/mach-omap2/omap4-sar-layout.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
   4 *
   5 * Copyright (C) 2011 Texas Instruments, Inc.
   6 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
   7 */
   8#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
   9#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
  10
  11/*
  12 * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
  13 */
  14#define SAR_BANK1_OFFSET                0x0000
  15#define SAR_BANK2_OFFSET                0x1000
  16#define SAR_BANK3_OFFSET                0x2000
  17#define SAR_BANK4_OFFSET                0x3000
  18
  19/* Scratch pad memory offsets from SAR_BANK1 */
  20#define SCU_OFFSET0                             0xfe4
  21#define SCU_OFFSET1                             0xfe8
  22#define OMAP_TYPE_OFFSET                        0xfec
  23#define L2X0_SAVE_OFFSET0                       0xff0
  24#define L2X0_SAVE_OFFSET1                       0xff4
  25#define L2X0_AUXCTRL_OFFSET                     0xff8
  26#define L2X0_PREFETCH_CTRL_OFFSET               0xffc
  27
  28/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK1 */
  29#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
  30#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET           0xa08
  31#define OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET     0xe00
  32#define OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET     0xe04
  33
  34#define SAR_BACKUP_STATUS_OFFSET                (SAR_BANK3_OFFSET + 0x500)
  35#define SAR_SECURE_RAM_SIZE_OFFSET              (SAR_BANK3_OFFSET + 0x504)
  36#define SAR_SECRAM_SAVED_AT_OFFSET              (SAR_BANK3_OFFSET + 0x508)
  37
  38/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
  39#define WAKEUPGENENB_OFFSET_CPU0                (SAR_BANK3_OFFSET + 0x684)
  40#define WAKEUPGENENB_SECURE_OFFSET_CPU0         (SAR_BANK3_OFFSET + 0x694)
  41#define WAKEUPGENENB_OFFSET_CPU1                (SAR_BANK3_OFFSET + 0x6a4)
  42#define WAKEUPGENENB_SECURE_OFFSET_CPU1         (SAR_BANK3_OFFSET + 0x6b4)
  43#define AUXCOREBOOT0_OFFSET                     (SAR_BANK3_OFFSET + 0x6c4)
  44#define AUXCOREBOOT1_OFFSET                     (SAR_BANK3_OFFSET + 0x6c8)
  45#define PTMSYNCREQ_MASK_OFFSET                  (SAR_BANK3_OFFSET + 0x6cc)
  46#define PTMSYNCREQ_EN_OFFSET                    (SAR_BANK3_OFFSET + 0x6d0)
  47#define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
  48
  49/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
  50#define OMAP5_WAKEUPGENENB_OFFSET_CPU0          (SAR_BANK3_OFFSET + 0x9dc)
  51#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x9f0)
  52#define OMAP5_WAKEUPGENENB_OFFSET_CPU1          (SAR_BANK3_OFFSET + 0xa04)
  53#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0xa18)
  54#define OMAP5_AUXCOREBOOT0_OFFSET               (SAR_BANK3_OFFSET + 0xa2c)
  55#define OMAP5_AUXCOREBOOT1_OFFSET               (SAR_BANK3_OFFSET + 0x930)
  56#define OMAP5_AMBA_IF_MODE_OFFSET               (SAR_BANK3_OFFSET + 0xa34)
  57#define OMAP5_SAR_BACKUP_STATUS_OFFSET          (SAR_BANK3_OFFSET + 0x800)
  58
  59#endif
  60