1/* 2 * AM33XX Power Management register bits 3 * 4 * This file is automatically generated from the AM33XX hardware databases. 5 * Vaibhav Hiremath <hvaibhav@ti.com> 6 * 7 * Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/ 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation version 2. 12 * 13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 14 * kind, whether express or implied; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 20#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 21#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 22 23#define AM33XX_CLKOUT2DIV_SHIFT 3 24#define AM33XX_CLKOUT2DIV_WIDTH 3 25#define AM33XX_CLKOUT2EN_SHIFT 7 26#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) 27#define AM33XX_CLKSEL_0_0_SHIFT 0 28#define AM33XX_CLKSEL_0_0_WIDTH 1 29#define AM33XX_CLKSEL_0_0_MASK (1 << 0) 30#define AM33XX_CLKSEL_0_1_MASK (3 << 0) 31#define AM33XX_CLKSEL_0_2_MASK (7 << 0) 32#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) 33#define AM33XX_CLKTRCTRL_SHIFT 0 34#define AM33XX_CLKTRCTRL_MASK (0x3 << 0) 35#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 36#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 37#define AM33XX_DPLL_DIV_MASK (0x7f << 0) 38#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) 39#define AM33XX_DPLL_EN_MASK (0x7 << 0) 40#define AM33XX_DPLL_MULT_MASK (0x7ff << 8) 41#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) 42#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 43#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 44#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 45#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 46#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 47#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 48#define AM33XX_IDLEST_SHIFT 16 49#define AM33XX_IDLEST_MASK (0x3 << 16) 50#define AM33XX_MODULEMODE_SHIFT 0 51#define AM33XX_MODULEMODE_MASK (0x3 << 0) 52#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 53#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 54#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 55#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 56#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 57#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 58#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 59#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 60#define AM33XX_STM_PMD_CLKSEL_SHIFT 22 61#define AM33XX_STM_PMD_CLKSEL_WIDTH 2 62#define AM33XX_ST_DPLL_CLK_MASK (1 << 0) 63#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 64#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 65#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 66#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 67#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 68#endif 69