LXR linux/arch/arm/mach-omap1/pm.h

   1/*
   2 * arch/arm/mach-omap1/pm.h
   3 *
   4 * Header file for OMAP1 Power Management Routines
   5 *
   6 * Author: MontaVista Software, Inc.
   7 *         support@mvista.com
   8 *
   9 * Copyright 2002 MontaVista Software Inc.
  10 *
  11 * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
  12 *
  13 * This program is free software; you can redistribute it and/or modify it
  14 * under the terms of the GNU General Public License as published by the
  15 * Free Software Foundation; either version 2 of the License, or (at your
  16 * option) any later version.
  17 *
  18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 *
  29 * You should have received a copy of the GNU General Public License along
  30 * with this program; if not, write to the Free Software Foundation, Inc.,
  31 * 675 Mass Ave, Cambridge, MA 02139, USA.
  32 */
  33
  34#ifndef __ARCH_ARM_MACH_OMAP1_PM_H
  35#define __ARCH_ARM_MACH_OMAP1_PM_H
  36
  37/*
  38 * ----------------------------------------------------------------------------
  39 * Register and offset definitions to be used in PM assembler code
  40 * ----------------------------------------------------------------------------
  41 */
  42#define CLKGEN_REG_ASM_BASE             OMAP1_IO_ADDRESS(0xfffece00)
  43#define ARM_IDLECT1_ASM_OFFSET          0x04
  44#define ARM_IDLECT2_ASM_OFFSET          0x08
  45
  46#define TCMIF_ASM_BASE                  OMAP1_IO_ADDRESS(0xfffecc00)
  47#define EMIFS_CONFIG_ASM_OFFSET         0x0c
  48#define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
  49
  50/*
  51 * ----------------------------------------------------------------------------
  52 * Power management bitmasks
  53 * ----------------------------------------------------------------------------
  54 */
  55#define IDLE_WAIT_CYCLES                0x00000fff
  56#define PERIPHERAL_ENABLE               0x2
  57
  58#define SELF_REFRESH_MODE               0x0c000001
  59#define IDLE_EMIFS_REQUEST              0xc
  60#define MODEM_32K_EN                    0x1
  61#define PER_EN                          0x1
  62
  63#define CPU_SUSPEND_SIZE                200
  64#define ULPD_LOW_PWR_EN                 0x0001
  65#define ULPD_DEEP_SLEEP_TRANSITION_EN   0x0010
  66#define ULPD_SETUP_ANALOG_CELL_3_VAL    0
  67#define ULPD_POWER_CTRL_REG_VAL         0x0219
  68
  69#define DSP_IDLE_DELAY                  10
  70#define DSP_IDLE                        0x0040
  71#define DSP_RST                         0x0004
  72#define DSP_ENABLE                      0x0002
  73#define SUFFICIENT_DSP_RESET_TIME       1000
  74#define DEFAULT_MPUI_CONFIG             0x05cf
  75#define ENABLE_XORCLK                   0x2
  76#define DSP_CLOCK_ENABLE                0x2000
  77#define DSP_IDLE_MODE                   0x2
  78#define TC_IDLE_REQUEST                 (0x0000000c)
  79
  80#define IRQ_LEVEL2                      (1<<0)
  81#define IRQ_KEYBOARD                    (1<<1)
  82#define IRQ_UART2                       (1<<15)
  83
  84#define PDE_BIT                         0x08
  85#define PWD_EN_BIT                      0x04
  86#define EN_PERCK_BIT                    0x04
  87
  88#define OMAP1510_DEEP_SLEEP_REQUEST     0x0ec7
  89#define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
  90#define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
  91#define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
  92
  93/* Both big sleep and deep sleep use same values. Difference is in ULPD. */
  94#define OMAP1610_IDLECT1_SLEEP_VAL      0x13c7
  95#define OMAP1610_IDLECT2_SLEEP_VAL      0x09c7
  96#define OMAP1610_IDLECT3_VAL            0x3f
  97#define OMAP1610_IDLECT3_SLEEP_ORMASK   0x2c
  98#define OMAP1610_IDLECT3                0xfffece24
  99#define OMAP1610_IDLE_LOOP_REQUEST      0x0400
 100
 101#define OMAP7XX_IDLECT1_SLEEP_VAL       0x16c7
 102#define OMAP7XX_IDLECT2_SLEEP_VAL       0x09c7
 103#define OMAP7XX_IDLECT3_VAL             0x3f
 104#define OMAP7XX_IDLECT3         0xfffece24
 105#define OMAP7XX_IDLE_LOOP_REQUEST       0x0C00
 106
 107#if     !defined(CONFIG_ARCH_OMAP730) && \
 108        !defined(CONFIG_ARCH_OMAP850) && \
 109        !defined(CONFIG_ARCH_OMAP15XX) && \
 110        !defined(CONFIG_ARCH_OMAP16XX)
 111#warning "Power management for this processor not implemented yet"
 112#endif
 113
 114#ifndef __ASSEMBLER__
 115
 116#include <linux/clk.h>
 117
 118extern struct kset power_subsys;
 119
 120extern void prevent_idle_sleep(void);
 121extern void allow_idle_sleep(void);
 122
 123extern void omap1_pm_idle(void);
 124extern void omap1_pm_suspend(void);
 125
 126extern void omap7xx_cpu_suspend(unsigned long, unsigned long);
 127extern void omap1510_cpu_suspend(unsigned long, unsigned long);
 128extern void omap1610_cpu_suspend(unsigned long, unsigned long);
 129extern void omap7xx_idle_loop_suspend(void);
 130extern void omap1510_idle_loop_suspend(void);
 131extern void omap1610_idle_loop_suspend(void);
 132
 133extern unsigned int omap7xx_cpu_suspend_sz;
 134extern unsigned int omap1510_cpu_suspend_sz;
 135extern unsigned int omap1610_cpu_suspend_sz;
 136extern unsigned int omap7xx_idle_loop_suspend_sz;
 137extern unsigned int omap1510_idle_loop_suspend_sz;
 138extern unsigned int omap1610_idle_loop_suspend_sz;
 139
 140#ifdef CONFIG_OMAP_SERIAL_WAKE
 141extern void omap_serial_wake_trigger(int enable);
 142#else
 143#define omap_serial_wakeup_init()       {}
 144#define omap_serial_wake_trigger(x)     {}
 145#endif  /* CONFIG_OMAP_SERIAL_WAKE */
 146
 147#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
 148#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
 149#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
 150
 151#define DSP_SAVE(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x] = __raw_readw(x)
 152#define DSP_RESTORE(x) __raw_writew((dsp_sleep_save[DSP_SLEEP_SAVE_##x]), (x))
 153#define DSP_SHOW(x) dsp_sleep_save[DSP_SLEEP_SAVE_##x]
 154
 155#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
 156#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
 157#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
 158
 159#define MPUI7XX_SAVE(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x] = omap_readl(x)
 160#define MPUI7XX_RESTORE(x) omap_writel((mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]), (x))
 161#define MPUI7XX_SHOW(x) mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_##x]
 162
 163#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
 164#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
 165#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
 166
 167#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
 168#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
 169#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
 170
 171/*
 172 * List of global OMAP registers to preserve.
 173 * More ones like CP and general purpose register values are preserved
 174 * with the stack pointer in sleep.S.
 175 */
 176
 177enum arm_save_state {
 178        ARM_SLEEP_SAVE_START = 0,
 179        /*
 180         * MPU control registers 32 bits
 181         */
 182        ARM_SLEEP_SAVE_ARM_CKCTL,
 183        ARM_SLEEP_SAVE_ARM_IDLECT1,
 184        ARM_SLEEP_SAVE_ARM_IDLECT2,
 185        ARM_SLEEP_SAVE_ARM_IDLECT3,
 186        ARM_SLEEP_SAVE_ARM_EWUPCT,
 187        ARM_SLEEP_SAVE_ARM_RSTCT1,
 188        ARM_SLEEP_SAVE_ARM_RSTCT2,
 189        ARM_SLEEP_SAVE_ARM_SYSST,
 190        ARM_SLEEP_SAVE_SIZE
 191};
 192
 193enum dsp_save_state {
 194        DSP_SLEEP_SAVE_START = 0,
 195        /*
 196         * DSP registers 16 bits
 197         */
 198        DSP_SLEEP_SAVE_DSP_IDLECT2,
 199        DSP_SLEEP_SAVE_SIZE
 200};
 201
 202enum ulpd_save_state {
 203        ULPD_SLEEP_SAVE_START = 0,
 204        /*
 205         * ULPD registers 16 bits
 206         */
 207        ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
 208        ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
 209        ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
 210        ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
 211        ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
 212        ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
 213        ULPD_SLEEP_SAVE_SIZE
 214};
 215
 216enum mpui1510_save_state {
 217        MPUI1510_SLEEP_SAVE_START = 0,
 218        /*
 219         * MPUI registers 32 bits
 220         */
 221        MPUI1510_SLEEP_SAVE_MPUI_CTRL,
 222        MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 223        MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 224        MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
 225        MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 226        MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
 227        MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
 228        MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
 229#if defined(CONFIG_ARCH_OMAP15XX)
 230        MPUI1510_SLEEP_SAVE_SIZE
 231#else
 232        MPUI1510_SLEEP_SAVE_SIZE = 0
 233#endif
 234};
 235
 236enum mpui7xx_save_state {
 237        MPUI7XX_SLEEP_SAVE_START = 0,
 238        /*
 239         * MPUI registers 32 bits
 240         */
 241        MPUI7XX_SLEEP_SAVE_MPUI_CTRL,
 242        MPUI7XX_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 243        MPUI7XX_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 244        MPUI7XX_SLEEP_SAVE_MPUI_DSP_STATUS,
 245        MPUI7XX_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 246        MPUI7XX_SLEEP_SAVE_EMIFS_CONFIG,
 247        MPUI7XX_SLEEP_SAVE_OMAP_IH1_MIR,
 248        MPUI7XX_SLEEP_SAVE_OMAP_IH2_0_MIR,
 249        MPUI7XX_SLEEP_SAVE_OMAP_IH2_1_MIR,
 250#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
 251        MPUI7XX_SLEEP_SAVE_SIZE
 252#else
 253        MPUI7XX_SLEEP_SAVE_SIZE = 0
 254#endif
 255};
 256
 257enum mpui1610_save_state {
 258        MPUI1610_SLEEP_SAVE_START = 0,
 259        /*
 260         * MPUI registers 32 bits
 261         */
 262        MPUI1610_SLEEP_SAVE_MPUI_CTRL,
 263        MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
 264        MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
 265        MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
 266        MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
 267        MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
 268        MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
 269        MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
 270        MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
 271        MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
 272        MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
 273#if defined(CONFIG_ARCH_OMAP16XX)
 274        MPUI1610_SLEEP_SAVE_SIZE
 275#else
 276        MPUI1610_SLEEP_SAVE_SIZE = 0
 277#endif
 278};
 279
 280#endif /* ASSEMBLER */
 281#endif /* __ASM_ARCH_OMAP_PM_H */
 282