LXR linux/arch/arm/mach-davinci/clock.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * TI DaVinci clock definitions
   4 *
   5 * Copyright (C) 2006-2007 Texas Instruments.
   6 * Copyright (C) 2008-2009 Deep Root Systems, LLC
   7 */
   8
   9#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
  10#define __ARCH_ARM_DAVINCI_CLOCK_H
  11
  12/* PLL/Reset register offsets */
  13#define PLLCTL          0x100
  14#define PLLCTL_PLLEN    BIT(0)
  15#define PLLCTL_PLLPWRDN BIT(1)
  16#define PLLCTL_PLLRST   BIT(3)
  17#define PLLCTL_PLLDIS   BIT(4)
  18#define PLLCTL_PLLENSRC BIT(5)
  19#define PLLCTL_CLKMODE  BIT(8)
  20
  21#define PLLM            0x110
  22#define PLLM_PLLM_MASK  0xff
  23
  24#define PREDIV          0x114
  25#define PLLDIV1         0x118
  26#define PLLDIV2         0x11c
  27#define PLLDIV3         0x120
  28#define POSTDIV         0x128
  29#define BPDIV           0x12c
  30#define PLLCMD          0x138
  31#define PLLSTAT         0x13c
  32#define PLLALNCTL       0x140
  33#define PLLDCHANGE      0x144
  34#define PLLCKEN         0x148
  35#define PLLCKSTAT       0x14c
  36#define PLLSYSTAT       0x150
  37#define PLLDIV4         0x160
  38#define PLLDIV5         0x164
  39#define PLLDIV6         0x168
  40#define PLLDIV7         0x16c
  41#define PLLDIV8         0x170
  42#define PLLDIV9         0x174
  43#define PLLDIV_EN       BIT(15)
  44#define PLLDIV_RATIO_MASK 0x1f
  45
  46/*
  47 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  48 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
  49 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
  50 * is ~25MHz. Units are micro seconds.
  51 */
  52#define PLL_BYPASS_TIME         1
  53/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
  54#define PLL_RESET_TIME          1
  55/*
  56 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
  57 * Units are micro seconds.
  58 */
  59#define PLL_LOCK_TIME           20
  60
  61#endif
  62