linux/drivers/usb/mtu3/mtu3_core.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * mtu3_core.c - hardware access layer and gadget init/exit of
   4 *                     MediaTek usb3 Dual-Role Controller Driver
   5 *
   6 * Copyright (C) 2016 MediaTek Inc.
   7 *
   8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
   9 */
  10
  11#include <linux/dma-mapping.h>
  12#include <linux/kernel.h>
  13#include <linux/module.h>
  14#include <linux/of_address.h>
  15#include <linux/of_irq.h>
  16#include <linux/platform_device.h>
  17
  18#include "mtu3.h"
  19#include "mtu3_dr.h"
  20#include "mtu3_debug.h"
  21#include "mtu3_trace.h"
  22
  23static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
  24{
  25        struct mtu3_fifo_info *fifo = mep->fifo;
  26        u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
  27        u32 start_bit;
  28
  29        /* ensure that @mep->fifo_seg_size is power of two */
  30        num_bits = roundup_pow_of_two(num_bits);
  31        if (num_bits > fifo->limit)
  32                return -EINVAL;
  33
  34        mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
  35        num_bits = num_bits * (mep->slot + 1);
  36        start_bit = bitmap_find_next_zero_area(fifo->bitmap,
  37                        fifo->limit, 0, num_bits, 0);
  38        if (start_bit >= fifo->limit)
  39                return -EOVERFLOW;
  40
  41        bitmap_set(fifo->bitmap, start_bit, num_bits);
  42        mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
  43        mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
  44
  45        dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
  46                __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
  47
  48        return mep->fifo_addr;
  49}
  50
  51static void ep_fifo_free(struct mtu3_ep *mep)
  52{
  53        struct mtu3_fifo_info *fifo = mep->fifo;
  54        u32 addr = mep->fifo_addr;
  55        u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
  56        u32 start_bit;
  57
  58        if (unlikely(addr < fifo->base || bits > fifo->limit))
  59                return;
  60
  61        start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
  62        bitmap_clear(fifo->bitmap, start_bit, bits);
  63        mep->fifo_size = 0;
  64        mep->fifo_seg_size = 0;
  65
  66        dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
  67                __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
  68}
  69
  70/* enable/disable U3D SS function */
  71static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
  72{
  73        /* If usb3_en==0, LTSSM will go to SS.Disable state */
  74        if (enable)
  75                mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
  76        else
  77                mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
  78
  79        dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
  80}
  81
  82/* set/clear U3D HS device soft connect */
  83static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
  84{
  85        if (enable) {
  86                mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
  87                        SOFT_CONN | SUSPENDM_ENABLE);
  88        } else {
  89                mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
  90                        SOFT_CONN | SUSPENDM_ENABLE);
  91        }
  92        dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
  93}
  94
  95/* only port0 of U2/U3 supports device mode */
  96static int mtu3_device_enable(struct mtu3 *mtu)
  97{
  98        void __iomem *ibase = mtu->ippc_base;
  99        u32 check_clk = 0;
 100
 101        mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 102
 103        if (mtu->is_u3_ip) {
 104                check_clk = SSUSB_U3_MAC_RST_B_STS;
 105                mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
 106                        (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
 107                        SSUSB_U3_PORT_HOST_SEL));
 108        }
 109        mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
 110                (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
 111                SSUSB_U2_PORT_HOST_SEL));
 112
 113        if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
 114                mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
 115                if (mtu->is_u3_ip)
 116                        mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
 117                                     SSUSB_U3_PORT_DUAL_MODE);
 118        }
 119
 120        return ssusb_check_clocks(mtu->ssusb, check_clk);
 121}
 122
 123static void mtu3_device_disable(struct mtu3 *mtu)
 124{
 125        void __iomem *ibase = mtu->ippc_base;
 126
 127        if (mtu->is_u3_ip)
 128                mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
 129                        (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
 130
 131        mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
 132                SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
 133
 134        if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
 135                mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
 136                if (mtu->is_u3_ip)
 137                        mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
 138                                     SSUSB_U3_PORT_DUAL_MODE);
 139        }
 140
 141        mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 142}
 143
 144/* reset U3D's device module. */
 145static void mtu3_device_reset(struct mtu3 *mtu)
 146{
 147        void __iomem *ibase = mtu->ippc_base;
 148
 149        mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
 150        udelay(1);
 151        mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
 152}
 153
 154static void mtu3_intr_status_clear(struct mtu3 *mtu)
 155{
 156        void __iomem *mbase = mtu->mac_base;
 157
 158        /* Clear EP0 and Tx/Rx EPn interrupts status */
 159        mtu3_writel(mbase, U3D_EPISR, ~0x0);
 160        /* Clear U2 USB common interrupts status */
 161        mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
 162        /* Clear U3 LTSSM interrupts status */
 163        mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
 164        /* Clear speed change interrupt status */
 165        mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
 166        /* Clear QMU interrupt status */
 167        mtu3_writel(mbase, U3D_QISAR0, ~0x0);
 168}
 169
 170/* disable all interrupts */
 171static void mtu3_intr_disable(struct mtu3 *mtu)
 172{
 173        /* Disable level 1 interrupts */
 174        mtu3_writel(mtu->mac_base, U3D_LV1IECR, ~0x0);
 175        /* Disable endpoint interrupts */
 176        mtu3_writel(mtu->mac_base, U3D_EPIECR, ~0x0);
 177        mtu3_intr_status_clear(mtu);
 178}
 179
 180/* enable system global interrupt */
 181static void mtu3_intr_enable(struct mtu3 *mtu)
 182{
 183        void __iomem *mbase = mtu->mac_base;
 184        u32 value;
 185
 186        /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
 187        value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
 188        mtu3_writel(mbase, U3D_LV1IESR, value);
 189
 190        /* Enable U2 common USB interrupts */
 191        value = SUSPEND_INTR | RESUME_INTR | RESET_INTR;
 192        mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
 193
 194        if (mtu->is_u3_ip) {
 195                /* Enable U3 LTSSM interrupts */
 196                value = HOT_RST_INTR | WARM_RST_INTR |
 197                        ENTER_U3_INTR | EXIT_U3_INTR;
 198                mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
 199        }
 200
 201        /* Enable QMU interrupts. */
 202        value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
 203                        RXQ_LENERR_INT | RXQ_ZLPERR_INT;
 204        mtu3_writel(mbase, U3D_QIESR1, value);
 205
 206        /* Enable speed change interrupt */
 207        mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
 208}
 209
 210static void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed)
 211{
 212        void __iomem *mbase = mtu->mac_base;
 213
 214        if (speed > mtu->max_speed)
 215                speed = mtu->max_speed;
 216
 217        switch (speed) {
 218        case USB_SPEED_FULL:
 219                /* disable U3 SS function */
 220                mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
 221                /* disable HS function */
 222                mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
 223                break;
 224        case USB_SPEED_HIGH:
 225                mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
 226                /* HS/FS detected by HW */
 227                mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
 228                break;
 229        case USB_SPEED_SUPER:
 230                mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
 231                mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
 232                             SSUSB_U3_PORT_SSP_SPEED);
 233                break;
 234        case USB_SPEED_SUPER_PLUS:
 235                mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
 236                mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
 237                             SSUSB_U3_PORT_SSP_SPEED);
 238                break;
 239        default:
 240                dev_err(mtu->dev, "invalid speed: %s\n",
 241                        usb_speed_string(speed));
 242                return;
 243        }
 244
 245        mtu->speed = speed;
 246        dev_dbg(mtu->dev, "set speed: %s\n", usb_speed_string(speed));
 247}
 248
 249/* CSR registers will be reset to default value if port is disabled */
 250static void mtu3_csr_init(struct mtu3 *mtu)
 251{
 252        void __iomem *mbase = mtu->mac_base;
 253
 254        if (mtu->is_u3_ip) {
 255                /* disable LGO_U1/U2 by default */
 256                mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
 257                                SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
 258                /* enable accept LGO_U1/U2 link command from host */
 259                mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
 260                                SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
 261                /* device responses to u3_exit from host automatically */
 262                mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
 263                /* automatically build U2 link when U3 detect fail */
 264                mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
 265                /* auto clear SOFT_CONN when clear USB3_EN if work as HS */
 266                mtu3_setbits(mbase, U3D_U3U2_SWITCH_CTRL, SOFTCON_CLR_AUTO_EN);
 267        }
 268
 269        /* delay about 0.1us from detecting reset to send chirp-K */
 270        mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
 271        /* enable automatical HWRW from L1 */
 272        mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, LPM_HRWE);
 273}
 274
 275/* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
 276static void mtu3_ep_reset(struct mtu3_ep *mep)
 277{
 278        struct mtu3 *mtu = mep->mtu;
 279        u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
 280
 281        mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
 282        mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
 283}
 284
 285/* set/clear the stall and toggle bits for non-ep0 */
 286void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
 287{
 288        struct mtu3 *mtu = mep->mtu;
 289        void __iomem *mbase = mtu->mac_base;
 290        u8 epnum = mep->epnum;
 291        u32 csr;
 292
 293        if (mep->is_in) {       /* TX */
 294                csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
 295                if (set)
 296                        csr |= TX_SENDSTALL;
 297                else
 298                        csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
 299                mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
 300        } else {        /* RX */
 301                csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
 302                if (set)
 303                        csr |= RX_SENDSTALL;
 304                else
 305                        csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
 306                mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
 307        }
 308
 309        if (!set) {
 310                mtu3_ep_reset(mep);
 311                mep->flags &= ~MTU3_EP_STALL;
 312        } else {
 313                mep->flags |= MTU3_EP_STALL;
 314        }
 315
 316        dev_dbg(mtu->dev, "%s: %s\n", mep->name,
 317                set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
 318}
 319
 320void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
 321{
 322        if (mtu->is_u3_ip && mtu->speed >= USB_SPEED_SUPER)
 323                mtu3_ss_func_set(mtu, is_on);
 324        else
 325                mtu3_hs_softconn_set(mtu, is_on);
 326
 327        dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
 328                usb_speed_string(mtu->speed), is_on ? "+" : "-");
 329}
 330
 331void mtu3_start(struct mtu3 *mtu)
 332{
 333        void __iomem *mbase = mtu->mac_base;
 334
 335        dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
 336                mtu3_readl(mbase, U3D_DEVICE_CONTROL));
 337
 338        mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 339        if (mtu->is_u3_ip)
 340                mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
 341
 342        mtu3_clrbits(mtu->ippc_base, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
 343
 344        mtu3_csr_init(mtu);
 345        mtu3_set_speed(mtu, mtu->speed);
 346
 347        /* Initialize the default interrupts */
 348        mtu3_intr_enable(mtu);
 349        mtu->is_active = 1;
 350
 351        if (mtu->softconnect)
 352                mtu3_dev_on_off(mtu, 1);
 353}
 354
 355void mtu3_stop(struct mtu3 *mtu)
 356{
 357        dev_dbg(mtu->dev, "%s\n", __func__);
 358
 359        mtu3_intr_disable(mtu);
 360
 361        if (mtu->softconnect)
 362                mtu3_dev_on_off(mtu, 0);
 363
 364        mtu->is_active = 0;
 365
 366        if (mtu->is_u3_ip)
 367                mtu3_setbits(mtu->ippc_base, SSUSB_U3_CTRL(0), SSUSB_U3_PORT_PDN);
 368
 369        mtu3_setbits(mtu->ippc_base, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_PDN);
 370        mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
 371}
 372
 373/* for non-ep0 */
 374int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
 375                        int interval, int burst, int mult)
 376{
 377        void __iomem *mbase = mtu->mac_base;
 378        bool gen2cp = mtu->gen2cp;
 379        int epnum = mep->epnum;
 380        u32 csr0, csr1, csr2;
 381        int fifo_sgsz, fifo_addr;
 382        int num_pkts;
 383
 384        fifo_addr = ep_fifo_alloc(mep, mep->maxp);
 385        if (fifo_addr < 0) {
 386                dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
 387                return -ENOMEM;
 388        }
 389        fifo_sgsz = ilog2(mep->fifo_seg_size);
 390        dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
 391                mep->fifo_seg_size, mep->fifo_size);
 392
 393        if (mep->is_in) {
 394                csr0 = TX_TXMAXPKTSZ(mep->maxp);
 395                csr0 |= TX_DMAREQEN;
 396
 397                num_pkts = (burst + 1) * (mult + 1) - 1;
 398                csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
 399                csr1 |= TX_MAX_PKT(gen2cp, num_pkts) | TX_MULT(gen2cp, mult);
 400
 401                csr2 = TX_FIFOADDR(fifo_addr >> 4);
 402                csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
 403
 404                switch (mep->type) {
 405                case USB_ENDPOINT_XFER_BULK:
 406                        csr1 |= TX_TYPE(TYPE_BULK);
 407                        break;
 408                case USB_ENDPOINT_XFER_ISOC:
 409                        csr1 |= TX_TYPE(TYPE_ISO);
 410                        csr2 |= TX_BINTERVAL(interval);
 411                        break;
 412                case USB_ENDPOINT_XFER_INT:
 413                        csr1 |= TX_TYPE(TYPE_INT);
 414                        csr2 |= TX_BINTERVAL(interval);
 415                        break;
 416                }
 417
 418                /* Enable QMU Done interrupt */
 419                mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
 420
 421                mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
 422                mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
 423                mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
 424
 425                dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
 426                        epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
 427                        mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
 428                        mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
 429        } else {
 430                csr0 = RX_RXMAXPKTSZ(mep->maxp);
 431                csr0 |= RX_DMAREQEN;
 432
 433                num_pkts = (burst + 1) * (mult + 1) - 1;
 434                csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
 435                csr1 |= RX_MAX_PKT(gen2cp, num_pkts) | RX_MULT(gen2cp, mult);
 436
 437                csr2 = RX_FIFOADDR(fifo_addr >> 4);
 438                csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
 439
 440                switch (mep->type) {
 441                case USB_ENDPOINT_XFER_BULK:
 442                        csr1 |= RX_TYPE(TYPE_BULK);
 443                        break;
 444                case USB_ENDPOINT_XFER_ISOC:
 445                        csr1 |= RX_TYPE(TYPE_ISO);
 446                        csr2 |= RX_BINTERVAL(interval);
 447                        break;
 448                case USB_ENDPOINT_XFER_INT:
 449                        csr1 |= RX_TYPE(TYPE_INT);
 450                        csr2 |= RX_BINTERVAL(interval);
 451                        break;
 452                }
 453
 454                /*Enable QMU Done interrupt */
 455                mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
 456
 457                mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
 458                mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
 459                mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
 460
 461                dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
 462                        epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
 463                        mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
 464                        mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
 465        }
 466
 467        dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
 468        dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
 469                __func__, mep->name, mep->fifo_addr, mep->fifo_size,
 470                fifo_sgsz, mep->fifo_seg_size);
 471
 472        return 0;
 473}
 474
 475/* for non-ep0 */
 476void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
 477{
 478        void __iomem *mbase = mtu->mac_base;
 479        int epnum = mep->epnum;
 480
 481        if (mep->is_in) {
 482                mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
 483                mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
 484                mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
 485                mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
 486        } else {
 487                mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
 488                mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
 489                mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
 490                mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
 491        }
 492
 493        mtu3_ep_reset(mep);
 494        ep_fifo_free(mep);
 495
 496        dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
 497}
 498
 499/*
 500 * Two scenarios:
 501 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
 502 *      are separated;
 503 * 2. when supports only HS, the fifo is shared for all EPs, and
 504 *      the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
 505 *      the total fifo size of non-ep0, and ep0's is fixed to 64B,
 506 *      so the total fifo size is 64B + @EPNTXFFSZ;
 507 *      Due to the first 64B should be reserved for EP0, non-ep0's fifo
 508 *      starts from offset 64 and are divided into two equal parts for
 509 *      TX or RX EPs for simplification.
 510 */
 511static void get_ep_fifo_config(struct mtu3 *mtu)
 512{
 513        struct mtu3_fifo_info *tx_fifo;
 514        struct mtu3_fifo_info *rx_fifo;
 515        u32 fifosize;
 516
 517        if (mtu->is_u3_ip) {
 518                fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
 519                tx_fifo = &mtu->tx_fifo;
 520                tx_fifo->base = 0;
 521                tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
 522                bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 523
 524                fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
 525                rx_fifo = &mtu->rx_fifo;
 526                rx_fifo->base = 0;
 527                rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
 528                bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 529                mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
 530        } else {
 531                fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
 532                tx_fifo = &mtu->tx_fifo;
 533                tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
 534                tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
 535                bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 536
 537                rx_fifo = &mtu->rx_fifo;
 538                rx_fifo->base =
 539                        tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
 540                rx_fifo->limit = tx_fifo->limit;
 541                bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
 542                mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
 543        }
 544
 545        dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
 546                __func__, tx_fifo->base, tx_fifo->limit,
 547                rx_fifo->base, rx_fifo->limit);
 548}
 549
 550static void mtu3_ep0_setup(struct mtu3 *mtu)
 551{
 552        u32 maxpacket = mtu->g.ep0->maxpacket;
 553        u32 csr;
 554
 555        dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
 556
 557        csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
 558        csr &= ~EP0_MAXPKTSZ_MSK;
 559        csr |= EP0_MAXPKTSZ(maxpacket);
 560        csr &= EP0_W1C_BITS;
 561        mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
 562
 563        /* Enable EP0 interrupt */
 564        mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR | SETUPENDISR);
 565}
 566
 567static int mtu3_mem_alloc(struct mtu3 *mtu)
 568{
 569        void __iomem *mbase = mtu->mac_base;
 570        struct mtu3_ep *ep_array;
 571        int in_ep_num, out_ep_num;
 572        u32 cap_epinfo;
 573        int ret;
 574        int i;
 575
 576        cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
 577        in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
 578        out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
 579
 580        dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
 581                 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
 582                 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
 583
 584        /* one for ep0, another is reserved */
 585        mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
 586        ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
 587        if (ep_array == NULL)
 588                return -ENOMEM;
 589
 590        mtu->ep_array = ep_array;
 591        mtu->in_eps = ep_array;
 592        mtu->out_eps = &ep_array[mtu->num_eps];
 593        /* ep0 uses in_eps[0], out_eps[0] is reserved */
 594        mtu->ep0 = mtu->in_eps;
 595        mtu->ep0->mtu = mtu;
 596        mtu->ep0->epnum = 0;
 597
 598        for (i = 1; i < mtu->num_eps; i++) {
 599                struct mtu3_ep *mep = mtu->in_eps + i;
 600
 601                mep->fifo = &mtu->tx_fifo;
 602                mep = mtu->out_eps + i;
 603                mep->fifo = &mtu->rx_fifo;
 604        }
 605
 606        get_ep_fifo_config(mtu);
 607
 608        ret = mtu3_qmu_init(mtu);
 609        if (ret)
 610                kfree(mtu->ep_array);
 611
 612        return ret;
 613}
 614
 615static void mtu3_mem_free(struct mtu3 *mtu)
 616{
 617        mtu3_qmu_exit(mtu);
 618        kfree(mtu->ep_array);
 619}
 620
 621static void mtu3_regs_init(struct mtu3 *mtu)
 622{
 623        void __iomem *mbase = mtu->mac_base;
 624
 625        /* be sure interrupts are disabled before registration of ISR */
 626        mtu3_intr_disable(mtu);
 627
 628        mtu3_csr_init(mtu);
 629
 630        /* U2/U3 detected by HW */
 631        mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
 632        /* vbus detected by HW */
 633        mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
 634        /* use new QMU format when HW version >= 0x1003 */
 635        if (mtu->gen2cp)
 636                mtu3_writel(mbase, U3D_QFCR, ~0x0);
 637}
 638
 639static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
 640{
 641        void __iomem *mbase = mtu->mac_base;
 642        enum usb_device_speed udev_speed;
 643        u32 maxpkt = 64;
 644        u32 link;
 645        u32 speed;
 646
 647        link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
 648        link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
 649        mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
 650        dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
 651
 652        if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
 653                return IRQ_NONE;
 654
 655        speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
 656
 657        switch (speed) {
 658        case MTU3_SPEED_FULL:
 659                udev_speed = USB_SPEED_FULL;
 660                /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
 661                mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
 662                                | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
 663                mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
 664                                LPM_BESL_STALL | LPM_BESLD_STALL);
 665                break;
 666        case MTU3_SPEED_HIGH:
 667                udev_speed = USB_SPEED_HIGH;
 668                /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
 669                mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
 670                                | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
 671                mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
 672                                LPM_BESL_STALL | LPM_BESLD_STALL);
 673                break;
 674        case MTU3_SPEED_SUPER:
 675                udev_speed = USB_SPEED_SUPER;
 676                maxpkt = 512;
 677                break;
 678        case MTU3_SPEED_SUPER_PLUS:
 679                udev_speed = USB_SPEED_SUPER_PLUS;
 680                maxpkt = 512;
 681                break;
 682        default:
 683                udev_speed = USB_SPEED_UNKNOWN;
 684                break;
 685        }
 686        dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
 687        mtu3_dbg_trace(mtu->dev, "link speed %s",
 688                       usb_speed_string(udev_speed));
 689
 690        mtu->g.speed = udev_speed;
 691        mtu->g.ep0->maxpacket = maxpkt;
 692        mtu->ep0_state = MU3D_EP0_STATE_SETUP;
 693
 694        if (udev_speed == USB_SPEED_UNKNOWN)
 695                mtu3_gadget_disconnect(mtu);
 696        else
 697                mtu3_ep0_setup(mtu);
 698
 699        return IRQ_HANDLED;
 700}
 701
 702static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
 703{
 704        void __iomem *mbase = mtu->mac_base;
 705        u32 ltssm;
 706
 707        ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
 708        ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
 709        mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
 710        dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
 711        trace_mtu3_u3_ltssm_isr(ltssm);
 712
 713        if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
 714                mtu3_gadget_reset(mtu);
 715
 716        if (ltssm & VBUS_FALL_INTR) {
 717                mtu3_ss_func_set(mtu, false);
 718                mtu3_gadget_reset(mtu);
 719        }
 720
 721        if (ltssm & VBUS_RISE_INTR)
 722                mtu3_ss_func_set(mtu, true);
 723
 724        if (ltssm & EXIT_U3_INTR)
 725                mtu3_gadget_resume(mtu);
 726
 727        if (ltssm & ENTER_U3_INTR)
 728                mtu3_gadget_suspend(mtu);
 729
 730        return IRQ_HANDLED;
 731}
 732
 733static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
 734{
 735        void __iomem *mbase = mtu->mac_base;
 736        u32 u2comm;
 737
 738        u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
 739        u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
 740        mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
 741        dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
 742        trace_mtu3_u2_common_isr(u2comm);
 743
 744        if (u2comm & SUSPEND_INTR)
 745                mtu3_gadget_suspend(mtu);
 746
 747        if (u2comm & RESUME_INTR)
 748                mtu3_gadget_resume(mtu);
 749
 750        if (u2comm & RESET_INTR)
 751                mtu3_gadget_reset(mtu);
 752
 753        return IRQ_HANDLED;
 754}
 755
 756static irqreturn_t mtu3_irq(int irq, void *data)
 757{
 758        struct mtu3 *mtu = (struct mtu3 *)data;
 759        unsigned long flags;
 760        u32 level1;
 761
 762        spin_lock_irqsave(&mtu->lock, flags);
 763
 764        /* U3D_LV1ISR is RU */
 765        level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
 766        level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
 767
 768        if (level1 & EP_CTRL_INTR)
 769                mtu3_link_isr(mtu);
 770
 771        if (level1 & MAC2_INTR)
 772                mtu3_u2_common_isr(mtu);
 773
 774        if (level1 & MAC3_INTR)
 775                mtu3_u3_ltssm_isr(mtu);
 776
 777        if (level1 & BMU_INTR)
 778                mtu3_ep0_isr(mtu);
 779
 780        if (level1 & QMU_INTR)
 781                mtu3_qmu_isr(mtu);
 782
 783        spin_unlock_irqrestore(&mtu->lock, flags);
 784
 785        return IRQ_HANDLED;
 786}
 787
 788static void mtu3_check_params(struct mtu3 *mtu)
 789{
 790        /* check the max_speed parameter */
 791        switch (mtu->max_speed) {
 792        case USB_SPEED_FULL:
 793        case USB_SPEED_HIGH:
 794        case USB_SPEED_SUPER:
 795        case USB_SPEED_SUPER_PLUS:
 796                break;
 797        default:
 798                dev_err(mtu->dev, "invalid max_speed: %s\n",
 799                        usb_speed_string(mtu->max_speed));
 800                fallthrough;
 801        case USB_SPEED_UNKNOWN:
 802                /* default as SSP */
 803                mtu->max_speed = USB_SPEED_SUPER_PLUS;
 804                break;
 805        }
 806
 807        if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
 808                mtu->max_speed = USB_SPEED_HIGH;
 809
 810        mtu->speed = mtu->max_speed;
 811
 812        dev_info(mtu->dev, "max_speed: %s\n",
 813                 usb_speed_string(mtu->max_speed));
 814}
 815
 816static int mtu3_hw_init(struct mtu3 *mtu)
 817{
 818        u32 value;
 819        int ret;
 820
 821        value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_TRUNK_VERS);
 822        mtu->hw_version = IP_TRUNK_VERS(value);
 823        mtu->gen2cp = !!(mtu->hw_version >= MTU3_TRUNK_VERS_1003);
 824
 825        value = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
 826        mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(value);
 827
 828        dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
 829                mtu->is_u3_ip ? "U3" : "U2");
 830
 831        mtu3_check_params(mtu);
 832
 833        mtu3_device_reset(mtu);
 834
 835        ret = mtu3_device_enable(mtu);
 836        if (ret) {
 837                dev_err(mtu->dev, "device enable failed %d\n", ret);
 838                return ret;
 839        }
 840
 841        ret = mtu3_mem_alloc(mtu);
 842        if (ret)
 843                return -ENOMEM;
 844
 845        mtu3_regs_init(mtu);
 846
 847        return 0;
 848}
 849
 850static void mtu3_hw_exit(struct mtu3 *mtu)
 851{
 852        mtu3_device_disable(mtu);
 853        mtu3_mem_free(mtu);
 854}
 855
 856/*
 857 * we set 32-bit DMA mask by default, here check whether the controller
 858 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
 859 */
 860static int mtu3_set_dma_mask(struct mtu3 *mtu)
 861{
 862        struct device *dev = mtu->dev;
 863        bool is_36bit = false;
 864        int ret = 0;
 865        u32 value;
 866
 867        value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
 868        if (value & DMA_ADDR_36BIT) {
 869                is_36bit = true;
 870                ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
 871                /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
 872                if (ret) {
 873                        is_36bit = false;
 874                        ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
 875                }
 876        }
 877        dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
 878
 879        return ret;
 880}
 881
 882int ssusb_gadget_init(struct ssusb_mtk *ssusb)
 883{
 884        struct device *dev = ssusb->dev;
 885        struct platform_device *pdev = to_platform_device(dev);
 886        struct mtu3 *mtu = NULL;
 887        int ret = -ENOMEM;
 888
 889        mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
 890        if (mtu == NULL)
 891                return -ENOMEM;
 892
 893        mtu->irq = platform_get_irq(pdev, 0);
 894        if (mtu->irq < 0)
 895                return mtu->irq;
 896        dev_info(dev, "irq %d\n", mtu->irq);
 897
 898        mtu->mac_base = devm_platform_ioremap_resource_byname(pdev, "mac");
 899        if (IS_ERR(mtu->mac_base)) {
 900                dev_err(dev, "error mapping memory for dev mac\n");
 901                return PTR_ERR(mtu->mac_base);
 902        }
 903
 904        spin_lock_init(&mtu->lock);
 905        mtu->dev = dev;
 906        mtu->ippc_base = ssusb->ippc_base;
 907        ssusb->mac_base = mtu->mac_base;
 908        ssusb->u3d = mtu;
 909        mtu->ssusb = ssusb;
 910        mtu->max_speed = usb_get_maximum_speed(dev);
 911
 912        dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
 913                mtu->mac_base, mtu->ippc_base);
 914
 915        ret = mtu3_hw_init(mtu);
 916        if (ret) {
 917                dev_err(dev, "mtu3 hw init failed:%d\n", ret);
 918                return ret;
 919        }
 920
 921        ret = mtu3_set_dma_mask(mtu);
 922        if (ret) {
 923                dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
 924                goto dma_mask_err;
 925        }
 926
 927        ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
 928        if (ret) {
 929                dev_err(dev, "request irq %d failed!\n", mtu->irq);
 930                goto irq_err;
 931        }
 932
 933        device_init_wakeup(dev, true);
 934
 935        /* power down device IP for power saving by default */
 936        mtu3_stop(mtu);
 937
 938        ret = mtu3_gadget_setup(mtu);
 939        if (ret) {
 940                dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
 941                goto gadget_err;
 942        }
 943
 944        ssusb_dev_debugfs_init(ssusb);
 945
 946        dev_dbg(dev, " %s() done...\n", __func__);
 947
 948        return 0;
 949
 950gadget_err:
 951        device_init_wakeup(dev, false);
 952
 953dma_mask_err:
 954irq_err:
 955        mtu3_hw_exit(mtu);
 956        ssusb->u3d = NULL;
 957        dev_err(dev, " %s() fail...\n", __func__);
 958
 959        return ret;
 960}
 961
 962void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
 963{
 964        struct mtu3 *mtu = ssusb->u3d;
 965
 966        mtu3_gadget_cleanup(mtu);
 967        device_init_wakeup(ssusb->dev, false);
 968        mtu3_hw_exit(mtu);
 969}
 970