linux/drivers/usb/dwc3/ep0.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4 *
   5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6 *
   7 * Authors: Felipe Balbi <balbi@ti.com>,
   8 *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9 */
  10
  11#include <linux/kernel.h>
  12#include <linux/slab.h>
  13#include <linux/spinlock.h>
  14#include <linux/platform_device.h>
  15#include <linux/pm_runtime.h>
  16#include <linux/interrupt.h>
  17#include <linux/io.h>
  18#include <linux/list.h>
  19#include <linux/dma-mapping.h>
  20
  21#include <linux/usb/ch9.h>
  22#include <linux/usb/gadget.h>
  23#include <linux/usb/composite.h>
  24
  25#include "core.h"
  26#include "debug.h"
  27#include "gadget.h"
  28#include "io.h"
  29
  30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                struct dwc3_ep *dep, struct dwc3_request *req);
  33
  34static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  35                dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  36{
  37        struct dwc3_trb                 *trb;
  38        struct dwc3                     *dwc;
  39
  40        dwc = dep->dwc;
  41        trb = &dwc->ep0_trb[dep->trb_enqueue];
  42
  43        if (chain)
  44                dep->trb_enqueue++;
  45
  46        trb->bpl = lower_32_bits(buf_dma);
  47        trb->bph = upper_32_bits(buf_dma);
  48        trb->size = len;
  49        trb->ctrl = type;
  50
  51        trb->ctrl |= (DWC3_TRB_CTRL_HWO
  52                        | DWC3_TRB_CTRL_ISP_IMI);
  53
  54        if (chain)
  55                trb->ctrl |= DWC3_TRB_CTRL_CHN;
  56        else
  57                trb->ctrl |= (DWC3_TRB_CTRL_IOC
  58                                | DWC3_TRB_CTRL_LST);
  59
  60        trace_dwc3_prepare_trb(dep, trb);
  61}
  62
  63static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  64{
  65        struct dwc3_gadget_ep_cmd_params params;
  66        struct dwc3                     *dwc;
  67        int                             ret;
  68
  69        if (dep->flags & DWC3_EP_TRANSFER_STARTED)
  70                return 0;
  71
  72        dwc = dep->dwc;
  73
  74        memset(&params, 0, sizeof(params));
  75        params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  76        params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  77
  78        ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  79        if (ret < 0)
  80                return ret;
  81
  82        dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  83
  84        return 0;
  85}
  86
  87static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  88                struct dwc3_request *req)
  89{
  90        struct dwc3             *dwc = dep->dwc;
  91
  92        req->request.actual     = 0;
  93        req->request.status     = -EINPROGRESS;
  94        req->epnum              = dep->number;
  95
  96        list_add_tail(&req->list, &dep->pending_list);
  97
  98        /*
  99         * Gadget driver might not be quick enough to queue a request
 100         * before we get a Transfer Not Ready event on this endpoint.
 101         *
 102         * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 103         * flag is set, it's telling us that as soon as Gadget queues the
 104         * required request, we should kick the transfer here because the
 105         * IRQ we were waiting for is long gone.
 106         */
 107        if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 108                unsigned int direction;
 109
 110                direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 111
 112                if (dwc->ep0state != EP0_DATA_PHASE) {
 113                        dev_WARN(dwc->dev, "Unexpected pending request\n");
 114                        return 0;
 115                }
 116
 117                __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 118
 119                dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 120                                DWC3_EP0_DIR_IN);
 121
 122                return 0;
 123        }
 124
 125        /*
 126         * In case gadget driver asked us to delay the STATUS phase,
 127         * handle it here.
 128         */
 129        if (dwc->delayed_status) {
 130                unsigned int direction;
 131
 132                direction = !dwc->ep0_expect_in;
 133                dwc->delayed_status = false;
 134                usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
 135
 136                if (dwc->ep0state == EP0_STATUS_PHASE)
 137                        __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 138
 139                return 0;
 140        }
 141
 142        /*
 143         * Unfortunately we have uncovered a limitation wrt the Data Phase.
 144         *
 145         * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 146         * come before issueing Start Transfer command, but if we do, we will
 147         * miss situations where the host starts another SETUP phase instead of
 148         * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 149         * Layer Compliance Suite.
 150         *
 151         * The problem surfaces due to the fact that in case of back-to-back
 152         * SETUP packets there will be no XferNotReady(DATA) generated and we
 153         * will be stuck waiting for XferNotReady(DATA) forever.
 154         *
 155         * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 156         * it tells us to start Data Phase right away. It also mentions that if
 157         * we receive a SETUP phase instead of the DATA phase, core will issue
 158         * XferComplete for the DATA phase, before actually initiating it in
 159         * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 160         * can only be used to print some debugging logs, as the core expects
 161         * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 162         * just so it completes right away, without transferring anything and,
 163         * only then, we can go back to the SETUP phase.
 164         *
 165         * Because of this scenario, SNPS decided to change the programming
 166         * model of control transfers and support on-demand transfers only for
 167         * the STATUS phase. To fix the issue we have now, we will always wait
 168         * for gadget driver to queue the DATA phase's struct usb_request, then
 169         * start it right away.
 170         *
 171         * If we're actually in a 2-stage transfer, we will wait for
 172         * XferNotReady(STATUS).
 173         */
 174        if (dwc->three_stage_setup) {
 175                unsigned int direction;
 176
 177                direction = dwc->ep0_expect_in;
 178                dwc->ep0state = EP0_DATA_PHASE;
 179
 180                __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 181
 182                dep->flags &= ~DWC3_EP0_DIR_IN;
 183        }
 184
 185        return 0;
 186}
 187
 188int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 189                gfp_t gfp_flags)
 190{
 191        struct dwc3_request             *req = to_dwc3_request(request);
 192        struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 193        struct dwc3                     *dwc = dep->dwc;
 194
 195        unsigned long                   flags;
 196
 197        int                             ret;
 198
 199        spin_lock_irqsave(&dwc->lock, flags);
 200        if (!dep->endpoint.desc || !dwc->pullups_connected) {
 201                dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 202                                dep->name);
 203                ret = -ESHUTDOWN;
 204                goto out;
 205        }
 206
 207        /* we share one TRB for ep0/1 */
 208        if (!list_empty(&dep->pending_list)) {
 209                ret = -EBUSY;
 210                goto out;
 211        }
 212
 213        ret = __dwc3_gadget_ep0_queue(dep, req);
 214
 215out:
 216        spin_unlock_irqrestore(&dwc->lock, flags);
 217
 218        return ret;
 219}
 220
 221static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 222{
 223        struct dwc3_ep          *dep;
 224
 225        /* reinitialize physical ep1 */
 226        dep = dwc->eps[1];
 227        dep->flags = DWC3_EP_ENABLED;
 228
 229        /* stall is always issued on EP0 */
 230        dep = dwc->eps[0];
 231        __dwc3_gadget_ep_set_halt(dep, 1, false);
 232        dep->flags = DWC3_EP_ENABLED;
 233        dwc->delayed_status = false;
 234
 235        if (!list_empty(&dep->pending_list)) {
 236                struct dwc3_request     *req;
 237
 238                req = next_request(&dep->pending_list);
 239                dwc3_gadget_giveback(dep, req, -ECONNRESET);
 240        }
 241
 242        dwc->ep0state = EP0_SETUP_PHASE;
 243        dwc3_ep0_out_start(dwc);
 244}
 245
 246int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 247{
 248        struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 249        struct dwc3                     *dwc = dep->dwc;
 250
 251        dwc3_ep0_stall_and_restart(dwc);
 252
 253        return 0;
 254}
 255
 256int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 257{
 258        struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 259        struct dwc3                     *dwc = dep->dwc;
 260        unsigned long                   flags;
 261        int                             ret;
 262
 263        spin_lock_irqsave(&dwc->lock, flags);
 264        ret = __dwc3_gadget_ep0_set_halt(ep, value);
 265        spin_unlock_irqrestore(&dwc->lock, flags);
 266
 267        return ret;
 268}
 269
 270void dwc3_ep0_out_start(struct dwc3 *dwc)
 271{
 272        struct dwc3_ep                  *dep;
 273        int                             ret;
 274
 275        complete(&dwc->ep0_in_setup);
 276
 277        dep = dwc->eps[0];
 278        dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 279                        DWC3_TRBCTL_CONTROL_SETUP, false);
 280        ret = dwc3_ep0_start_trans(dep);
 281        WARN_ON(ret < 0);
 282}
 283
 284static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 285{
 286        struct dwc3_ep          *dep;
 287        u32                     windex = le16_to_cpu(wIndex_le);
 288        u32                     epnum;
 289
 290        epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 291        if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 292                epnum |= 1;
 293
 294        dep = dwc->eps[epnum];
 295        if (dep == NULL)
 296                return NULL;
 297
 298        if (dep->flags & DWC3_EP_ENABLED)
 299                return dep;
 300
 301        return NULL;
 302}
 303
 304static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 305{
 306}
 307/*
 308 * ch 9.4.5
 309 */
 310static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 311                struct usb_ctrlrequest *ctrl)
 312{
 313        struct dwc3_ep          *dep;
 314        u32                     recip;
 315        u32                     value;
 316        u32                     reg;
 317        u16                     usb_status = 0;
 318        __le16                  *response_pkt;
 319
 320        /* We don't support PTM_STATUS */
 321        value = le16_to_cpu(ctrl->wValue);
 322        if (value != 0)
 323                return -EINVAL;
 324
 325        recip = ctrl->bRequestType & USB_RECIP_MASK;
 326        switch (recip) {
 327        case USB_RECIP_DEVICE:
 328                /*
 329                 * LTM will be set once we know how to set this in HW.
 330                 */
 331                usb_status |= dwc->gadget->is_selfpowered;
 332
 333                if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 334                    (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 335                        reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 336                        if (reg & DWC3_DCTL_INITU1ENA)
 337                                usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 338                        if (reg & DWC3_DCTL_INITU2ENA)
 339                                usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 340                }
 341
 342                break;
 343
 344        case USB_RECIP_INTERFACE:
 345                /*
 346                 * Function Remote Wake Capable D0
 347                 * Function Remote Wakeup       D1
 348                 */
 349                break;
 350
 351        case USB_RECIP_ENDPOINT:
 352                dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 353                if (!dep)
 354                        return -EINVAL;
 355
 356                if (dep->flags & DWC3_EP_STALL)
 357                        usb_status = 1 << USB_ENDPOINT_HALT;
 358                break;
 359        default:
 360                return -EINVAL;
 361        }
 362
 363        response_pkt = (__le16 *) dwc->setup_buf;
 364        *response_pkt = cpu_to_le16(usb_status);
 365
 366        dep = dwc->eps[0];
 367        dwc->ep0_usb_req.dep = dep;
 368        dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 369        dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 370        dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 371
 372        return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 373}
 374
 375static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 376                int set)
 377{
 378        u32 reg;
 379
 380        if (state != USB_STATE_CONFIGURED)
 381                return -EINVAL;
 382        if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 383                        (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 384                return -EINVAL;
 385        if (set && dwc->dis_u1_entry_quirk)
 386                return -EINVAL;
 387
 388        reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 389        if (set)
 390                reg |= DWC3_DCTL_INITU1ENA;
 391        else
 392                reg &= ~DWC3_DCTL_INITU1ENA;
 393        dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 394
 395        return 0;
 396}
 397
 398static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 399                int set)
 400{
 401        u32 reg;
 402
 403
 404        if (state != USB_STATE_CONFIGURED)
 405                return -EINVAL;
 406        if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 407                        (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 408                return -EINVAL;
 409        if (set && dwc->dis_u2_entry_quirk)
 410                return -EINVAL;
 411
 412        reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 413        if (set)
 414                reg |= DWC3_DCTL_INITU2ENA;
 415        else
 416                reg &= ~DWC3_DCTL_INITU2ENA;
 417        dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 418
 419        return 0;
 420}
 421
 422static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 423                u32 wIndex, int set)
 424{
 425        if ((wIndex & 0xff) != 0)
 426                return -EINVAL;
 427        if (!set)
 428                return -EINVAL;
 429
 430        switch (wIndex >> 8) {
 431        case USB_TEST_J:
 432        case USB_TEST_K:
 433        case USB_TEST_SE0_NAK:
 434        case USB_TEST_PACKET:
 435        case USB_TEST_FORCE_ENABLE:
 436                dwc->test_mode_nr = wIndex >> 8;
 437                dwc->test_mode = true;
 438                break;
 439        default:
 440                return -EINVAL;
 441        }
 442
 443        return 0;
 444}
 445
 446static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 447                struct usb_ctrlrequest *ctrl, int set)
 448{
 449        enum usb_device_state   state;
 450        u32                     wValue;
 451        u32                     wIndex;
 452        int                     ret = 0;
 453
 454        wValue = le16_to_cpu(ctrl->wValue);
 455        wIndex = le16_to_cpu(ctrl->wIndex);
 456        state = dwc->gadget->state;
 457
 458        switch (wValue) {
 459        case USB_DEVICE_REMOTE_WAKEUP:
 460                break;
 461        /*
 462         * 9.4.1 says only only for SS, in AddressState only for
 463         * default control pipe
 464         */
 465        case USB_DEVICE_U1_ENABLE:
 466                ret = dwc3_ep0_handle_u1(dwc, state, set);
 467                break;
 468        case USB_DEVICE_U2_ENABLE:
 469                ret = dwc3_ep0_handle_u2(dwc, state, set);
 470                break;
 471        case USB_DEVICE_LTM_ENABLE:
 472                ret = -EINVAL;
 473                break;
 474        case USB_DEVICE_TEST_MODE:
 475                ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 476                break;
 477        default:
 478                ret = -EINVAL;
 479        }
 480
 481        return ret;
 482}
 483
 484static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 485                struct usb_ctrlrequest *ctrl, int set)
 486{
 487        u32                     wValue;
 488        int                     ret = 0;
 489
 490        wValue = le16_to_cpu(ctrl->wValue);
 491
 492        switch (wValue) {
 493        case USB_INTRF_FUNC_SUSPEND:
 494                /*
 495                 * REVISIT: Ideally we would enable some low power mode here,
 496                 * however it's unclear what we should be doing here.
 497                 *
 498                 * For now, we're not doing anything, just making sure we return
 499                 * 0 so USB Command Verifier tests pass without any errors.
 500                 */
 501                break;
 502        default:
 503                ret = -EINVAL;
 504        }
 505
 506        return ret;
 507}
 508
 509static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 510                struct usb_ctrlrequest *ctrl, int set)
 511{
 512        struct dwc3_ep          *dep;
 513        u32                     wValue;
 514        int                     ret;
 515
 516        wValue = le16_to_cpu(ctrl->wValue);
 517
 518        switch (wValue) {
 519        case USB_ENDPOINT_HALT:
 520                dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 521                if (!dep)
 522                        return -EINVAL;
 523
 524                if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 525                        break;
 526
 527                ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 528                if (ret)
 529                        return -EINVAL;
 530
 531                /* ClearFeature(Halt) may need delayed status */
 532                if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
 533                        return USB_GADGET_DELAYED_STATUS;
 534
 535                break;
 536        default:
 537                return -EINVAL;
 538        }
 539
 540        return 0;
 541}
 542
 543static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 544                struct usb_ctrlrequest *ctrl, int set)
 545{
 546        u32                     recip;
 547        int                     ret;
 548
 549        recip = ctrl->bRequestType & USB_RECIP_MASK;
 550
 551        switch (recip) {
 552        case USB_RECIP_DEVICE:
 553                ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 554                break;
 555        case USB_RECIP_INTERFACE:
 556                ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 557                break;
 558        case USB_RECIP_ENDPOINT:
 559                ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 560                break;
 561        default:
 562                ret = -EINVAL;
 563        }
 564
 565        return ret;
 566}
 567
 568static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 569{
 570        enum usb_device_state state = dwc->gadget->state;
 571        u32 addr;
 572        u32 reg;
 573
 574        addr = le16_to_cpu(ctrl->wValue);
 575        if (addr > 127) {
 576                dev_err(dwc->dev, "invalid device address %d\n", addr);
 577                return -EINVAL;
 578        }
 579
 580        if (state == USB_STATE_CONFIGURED) {
 581                dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 582                return -EINVAL;
 583        }
 584
 585        reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 586        reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 587        reg |= DWC3_DCFG_DEVADDR(addr);
 588        dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 589
 590        if (addr)
 591                usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
 592        else
 593                usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
 594
 595        return 0;
 596}
 597
 598static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 599{
 600        int ret = -EINVAL;
 601
 602        if (dwc->async_callbacks) {
 603                spin_unlock(&dwc->lock);
 604                ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
 605                spin_lock(&dwc->lock);
 606        }
 607        return ret;
 608}
 609
 610static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 611{
 612        enum usb_device_state state = dwc->gadget->state;
 613        u32 cfg;
 614        int ret;
 615        u32 reg;
 616
 617        cfg = le16_to_cpu(ctrl->wValue);
 618
 619        switch (state) {
 620        case USB_STATE_DEFAULT:
 621                return -EINVAL;
 622
 623        case USB_STATE_ADDRESS:
 624                ret = dwc3_ep0_delegate_req(dwc, ctrl);
 625                /* if the cfg matches and the cfg is non zero */
 626                if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 627
 628                        /*
 629                         * only change state if set_config has already
 630                         * been processed. If gadget driver returns
 631                         * USB_GADGET_DELAYED_STATUS, we will wait
 632                         * to change the state on the next usb_ep_queue()
 633                         */
 634                        if (ret == 0)
 635                                usb_gadget_set_state(dwc->gadget,
 636                                                USB_STATE_CONFIGURED);
 637
 638                        /*
 639                         * Enable transition to U1/U2 state when
 640                         * nothing is pending from application.
 641                         */
 642                        reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 643                        if (!dwc->dis_u1_entry_quirk)
 644                                reg |= DWC3_DCTL_ACCEPTU1ENA;
 645                        if (!dwc->dis_u2_entry_quirk)
 646                                reg |= DWC3_DCTL_ACCEPTU2ENA;
 647                        dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 648                }
 649                break;
 650
 651        case USB_STATE_CONFIGURED:
 652                ret = dwc3_ep0_delegate_req(dwc, ctrl);
 653                if (!cfg && !ret)
 654                        usb_gadget_set_state(dwc->gadget,
 655                                        USB_STATE_ADDRESS);
 656                break;
 657        default:
 658                ret = -EINVAL;
 659        }
 660        return ret;
 661}
 662
 663static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 664{
 665        struct dwc3_ep  *dep = to_dwc3_ep(ep);
 666        struct dwc3     *dwc = dep->dwc;
 667
 668        u32             param = 0;
 669        u32             reg;
 670
 671        struct timing {
 672                u8      u1sel;
 673                u8      u1pel;
 674                __le16  u2sel;
 675                __le16  u2pel;
 676        } __packed timing;
 677
 678        int             ret;
 679
 680        memcpy(&timing, req->buf, sizeof(timing));
 681
 682        dwc->u1sel = timing.u1sel;
 683        dwc->u1pel = timing.u1pel;
 684        dwc->u2sel = le16_to_cpu(timing.u2sel);
 685        dwc->u2pel = le16_to_cpu(timing.u2pel);
 686
 687        reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 688        if (reg & DWC3_DCTL_INITU2ENA)
 689                param = dwc->u2pel;
 690        if (reg & DWC3_DCTL_INITU1ENA)
 691                param = dwc->u1pel;
 692
 693        /*
 694         * According to Synopsys Databook, if parameter is
 695         * greater than 125, a value of zero should be
 696         * programmed in the register.
 697         */
 698        if (param > 125)
 699                param = 0;
 700
 701        /* now that we have the time, issue DGCMD Set Sel */
 702        ret = dwc3_send_gadget_generic_command(dwc,
 703                        DWC3_DGCMD_SET_PERIODIC_PAR, param);
 704        WARN_ON(ret < 0);
 705}
 706
 707static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 708{
 709        struct dwc3_ep  *dep;
 710        enum usb_device_state state = dwc->gadget->state;
 711        u16             wLength;
 712
 713        if (state == USB_STATE_DEFAULT)
 714                return -EINVAL;
 715
 716        wLength = le16_to_cpu(ctrl->wLength);
 717
 718        if (wLength != 6) {
 719                dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 720                                wLength);
 721                return -EINVAL;
 722        }
 723
 724        /*
 725         * To handle Set SEL we need to receive 6 bytes from Host. So let's
 726         * queue a usb_request for 6 bytes.
 727         *
 728         * Remember, though, this controller can't handle non-wMaxPacketSize
 729         * aligned transfers on the OUT direction, so we queue a request for
 730         * wMaxPacketSize instead.
 731         */
 732        dep = dwc->eps[0];
 733        dwc->ep0_usb_req.dep = dep;
 734        dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 735        dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 736        dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 737
 738        return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 739}
 740
 741static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 742{
 743        u16             wLength;
 744        u16             wValue;
 745        u16             wIndex;
 746
 747        wValue = le16_to_cpu(ctrl->wValue);
 748        wLength = le16_to_cpu(ctrl->wLength);
 749        wIndex = le16_to_cpu(ctrl->wIndex);
 750
 751        if (wIndex || wLength)
 752                return -EINVAL;
 753
 754        dwc->gadget->isoch_delay = wValue;
 755
 756        return 0;
 757}
 758
 759static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 760{
 761        int ret;
 762
 763        switch (ctrl->bRequest) {
 764        case USB_REQ_GET_STATUS:
 765                ret = dwc3_ep0_handle_status(dwc, ctrl);
 766                break;
 767        case USB_REQ_CLEAR_FEATURE:
 768                ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 769                break;
 770        case USB_REQ_SET_FEATURE:
 771                ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 772                break;
 773        case USB_REQ_SET_ADDRESS:
 774                ret = dwc3_ep0_set_address(dwc, ctrl);
 775                break;
 776        case USB_REQ_SET_CONFIGURATION:
 777                ret = dwc3_ep0_set_config(dwc, ctrl);
 778                break;
 779        case USB_REQ_SET_SEL:
 780                ret = dwc3_ep0_set_sel(dwc, ctrl);
 781                break;
 782        case USB_REQ_SET_ISOCH_DELAY:
 783                ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 784                break;
 785        default:
 786                ret = dwc3_ep0_delegate_req(dwc, ctrl);
 787                break;
 788        }
 789
 790        return ret;
 791}
 792
 793static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 794                const struct dwc3_event_depevt *event)
 795{
 796        struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 797        int ret = -EINVAL;
 798        u32 len;
 799
 800        if (!dwc->gadget_driver)
 801                goto out;
 802
 803        trace_dwc3_ctrl_req(ctrl);
 804
 805        len = le16_to_cpu(ctrl->wLength);
 806        if (!len) {
 807                dwc->three_stage_setup = false;
 808                dwc->ep0_expect_in = false;
 809                dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 810        } else {
 811                dwc->three_stage_setup = true;
 812                dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 813                dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 814        }
 815
 816        if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 817                ret = dwc3_ep0_std_request(dwc, ctrl);
 818        else
 819                ret = dwc3_ep0_delegate_req(dwc, ctrl);
 820
 821        if (ret == USB_GADGET_DELAYED_STATUS)
 822                dwc->delayed_status = true;
 823
 824out:
 825        if (ret < 0)
 826                dwc3_ep0_stall_and_restart(dwc);
 827}
 828
 829static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 830                const struct dwc3_event_depevt *event)
 831{
 832        struct dwc3_request     *r;
 833        struct usb_request      *ur;
 834        struct dwc3_trb         *trb;
 835        struct dwc3_ep          *ep0;
 836        u32                     transferred = 0;
 837        u32                     status;
 838        u32                     length;
 839        u8                      epnum;
 840
 841        epnum = event->endpoint_number;
 842        ep0 = dwc->eps[0];
 843
 844        dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 845        trb = dwc->ep0_trb;
 846        trace_dwc3_complete_trb(ep0, trb);
 847
 848        r = next_request(&ep0->pending_list);
 849        if (!r)
 850                return;
 851
 852        status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 853        if (status == DWC3_TRBSTS_SETUP_PENDING) {
 854                dwc->setup_packet_pending = true;
 855                if (r)
 856                        dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 857
 858                return;
 859        }
 860
 861        ur = &r->request;
 862
 863        length = trb->size & DWC3_TRB_SIZE_MASK;
 864        transferred = ur->length - length;
 865        ur->actual += transferred;
 866
 867        if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 868             ur->length && ur->zero) || dwc->ep0_bounced) {
 869                trb++;
 870                trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 871                trace_dwc3_complete_trb(ep0, trb);
 872
 873                if (r->direction)
 874                        dwc->eps[1]->trb_enqueue = 0;
 875                else
 876                        dwc->eps[0]->trb_enqueue = 0;
 877
 878                dwc->ep0_bounced = false;
 879        }
 880
 881        if ((epnum & 1) && ur->actual < ur->length)
 882                dwc3_ep0_stall_and_restart(dwc);
 883        else
 884                dwc3_gadget_giveback(ep0, r, 0);
 885}
 886
 887static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 888                const struct dwc3_event_depevt *event)
 889{
 890        struct dwc3_request     *r;
 891        struct dwc3_ep          *dep;
 892        struct dwc3_trb         *trb;
 893        u32                     status;
 894
 895        dep = dwc->eps[0];
 896        trb = dwc->ep0_trb;
 897
 898        trace_dwc3_complete_trb(dep, trb);
 899
 900        if (!list_empty(&dep->pending_list)) {
 901                r = next_request(&dep->pending_list);
 902
 903                dwc3_gadget_giveback(dep, r, 0);
 904        }
 905
 906        if (dwc->test_mode) {
 907                int ret;
 908
 909                ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 910                if (ret < 0) {
 911                        dev_err(dwc->dev, "invalid test #%d\n",
 912                                        dwc->test_mode_nr);
 913                        dwc3_ep0_stall_and_restart(dwc);
 914                        return;
 915                }
 916        }
 917
 918        status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 919        if (status == DWC3_TRBSTS_SETUP_PENDING)
 920                dwc->setup_packet_pending = true;
 921
 922        dwc->ep0state = EP0_SETUP_PHASE;
 923        dwc3_ep0_out_start(dwc);
 924}
 925
 926static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 927                        const struct dwc3_event_depevt *event)
 928{
 929        struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 930
 931        dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 932        dep->resource_index = 0;
 933        dwc->setup_packet_pending = false;
 934
 935        switch (dwc->ep0state) {
 936        case EP0_SETUP_PHASE:
 937                dwc3_ep0_inspect_setup(dwc, event);
 938                break;
 939
 940        case EP0_DATA_PHASE:
 941                dwc3_ep0_complete_data(dwc, event);
 942                break;
 943
 944        case EP0_STATUS_PHASE:
 945                dwc3_ep0_complete_status(dwc, event);
 946                break;
 947        default:
 948                WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 949        }
 950}
 951
 952static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 953                struct dwc3_ep *dep, struct dwc3_request *req)
 954{
 955        unsigned int            trb_length = 0;
 956        int                     ret;
 957
 958        req->direction = !!dep->number;
 959
 960        if (req->request.length == 0) {
 961                if (!req->direction)
 962                        trb_length = dep->endpoint.maxpacket;
 963
 964                dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 965                                DWC3_TRBCTL_CONTROL_DATA, false);
 966                ret = dwc3_ep0_start_trans(dep);
 967        } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 968                        && (dep->number == 0)) {
 969                u32     maxpacket;
 970                u32     rem;
 971
 972                ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 973                                &req->request, dep->number);
 974                if (ret)
 975                        return;
 976
 977                maxpacket = dep->endpoint.maxpacket;
 978                rem = req->request.length % maxpacket;
 979                dwc->ep0_bounced = true;
 980
 981                /* prepare normal TRB */
 982                dwc3_ep0_prepare_one_trb(dep, req->request.dma,
 983                                         req->request.length,
 984                                         DWC3_TRBCTL_CONTROL_DATA,
 985                                         true);
 986
 987                req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
 988
 989                /* Now prepare one extra TRB to align transfer size */
 990                dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
 991                                         maxpacket - rem,
 992                                         DWC3_TRBCTL_CONTROL_DATA,
 993                                         false);
 994                ret = dwc3_ep0_start_trans(dep);
 995        } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
 996                   req->request.length && req->request.zero) {
 997
 998                ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 999                                &req->request, dep->number);
1000                if (ret)
1001                        return;
1002
1003                /* prepare normal TRB */
1004                dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1005                                         req->request.length,
1006                                         DWC3_TRBCTL_CONTROL_DATA,
1007                                         true);
1008
1009                req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1010
1011                if (!req->direction)
1012                        trb_length = dep->endpoint.maxpacket;
1013
1014                /* Now prepare one extra TRB to align transfer size */
1015                dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1016                                         trb_length, DWC3_TRBCTL_CONTROL_DATA,
1017                                         false);
1018                ret = dwc3_ep0_start_trans(dep);
1019        } else {
1020                ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1021                                &req->request, dep->number);
1022                if (ret)
1023                        return;
1024
1025                dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1026                                req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1027                                false);
1028
1029                req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1030
1031                ret = dwc3_ep0_start_trans(dep);
1032        }
1033
1034        WARN_ON(ret < 0);
1035}
1036
1037static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1038{
1039        struct dwc3             *dwc = dep->dwc;
1040        u32                     type;
1041
1042        type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1043                : DWC3_TRBCTL_CONTROL_STATUS2;
1044
1045        dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1046        return dwc3_ep0_start_trans(dep);
1047}
1048
1049static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1050{
1051        WARN_ON(dwc3_ep0_start_control_status(dep));
1052}
1053
1054static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1055                const struct dwc3_event_depevt *event)
1056{
1057        struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1058
1059        __dwc3_ep0_do_control_status(dwc, dep);
1060}
1061
1062void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1063{
1064        unsigned int direction = !dwc->ep0_expect_in;
1065
1066        dwc->delayed_status = false;
1067
1068        if (dwc->ep0state != EP0_STATUS_PHASE)
1069                return;
1070
1071        __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1072}
1073
1074static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1075{
1076        struct dwc3_gadget_ep_cmd_params params;
1077        u32                     cmd;
1078        int                     ret;
1079
1080        if (!dep->resource_index)
1081                return;
1082
1083        cmd = DWC3_DEPCMD_ENDTRANSFER;
1084        cmd |= DWC3_DEPCMD_CMDIOC;
1085        cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1086        memset(&params, 0, sizeof(params));
1087        ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1088        WARN_ON_ONCE(ret);
1089        dep->resource_index = 0;
1090}
1091
1092static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1093                const struct dwc3_event_depevt *event)
1094{
1095        switch (event->status) {
1096        case DEPEVT_STATUS_CONTROL_DATA:
1097                /*
1098                 * We already have a DATA transfer in the controller's cache,
1099                 * if we receive a XferNotReady(DATA) we will ignore it, unless
1100                 * it's for the wrong direction.
1101                 *
1102                 * In that case, we must issue END_TRANSFER command to the Data
1103                 * Phase we already have started and issue SetStall on the
1104                 * control endpoint.
1105                 */
1106                if (dwc->ep0_expect_in != event->endpoint_number) {
1107                        struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1108
1109                        dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1110                        dwc3_ep0_end_control_data(dwc, dep);
1111                        dwc3_ep0_stall_and_restart(dwc);
1112                        return;
1113                }
1114
1115                break;
1116
1117        case DEPEVT_STATUS_CONTROL_STATUS:
1118                if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1119                        return;
1120
1121                dwc->ep0state = EP0_STATUS_PHASE;
1122
1123                if (dwc->delayed_status) {
1124                        struct dwc3_ep *dep = dwc->eps[0];
1125
1126                        WARN_ON_ONCE(event->endpoint_number != 1);
1127                        /*
1128                         * We should handle the delay STATUS phase here if the
1129                         * request for handling delay STATUS has been queued
1130                         * into the list.
1131                         */
1132                        if (!list_empty(&dep->pending_list)) {
1133                                dwc->delayed_status = false;
1134                                usb_gadget_set_state(dwc->gadget,
1135                                                     USB_STATE_CONFIGURED);
1136                                dwc3_ep0_do_control_status(dwc, event);
1137                        }
1138
1139                        return;
1140                }
1141
1142                dwc3_ep0_do_control_status(dwc, event);
1143        }
1144}
1145
1146void dwc3_ep0_interrupt(struct dwc3 *dwc,
1147                const struct dwc3_event_depevt *event)
1148{
1149        struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1150        u8              cmd;
1151
1152        switch (event->endpoint_event) {
1153        case DWC3_DEPEVT_XFERCOMPLETE:
1154                dwc3_ep0_xfer_complete(dwc, event);
1155                break;
1156
1157        case DWC3_DEPEVT_XFERNOTREADY:
1158                dwc3_ep0_xfernotready(dwc, event);
1159                break;
1160
1161        case DWC3_DEPEVT_XFERINPROGRESS:
1162        case DWC3_DEPEVT_RXTXFIFOEVT:
1163        case DWC3_DEPEVT_STREAMEVT:
1164                break;
1165        case DWC3_DEPEVT_EPCMDCMPLT:
1166                cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1167
1168                if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1169                        dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1170                        dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1171                }
1172                break;
1173        }
1174}
1175