linux/drivers/usb/dwc3/core.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * core.c - DesignWare USB3 DRD Controller Core file
   4 *
   5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6 *
   7 * Authors: Felipe Balbi <balbi@ti.com>,
   8 *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9 */
  10
  11#include <linux/clk.h>
  12#include <linux/version.h>
  13#include <linux/module.h>
  14#include <linux/kernel.h>
  15#include <linux/slab.h>
  16#include <linux/spinlock.h>
  17#include <linux/platform_device.h>
  18#include <linux/pm_runtime.h>
  19#include <linux/interrupt.h>
  20#include <linux/ioport.h>
  21#include <linux/io.h>
  22#include <linux/list.h>
  23#include <linux/delay.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/of.h>
  26#include <linux/acpi.h>
  27#include <linux/pinctrl/consumer.h>
  28#include <linux/reset.h>
  29
  30#include <linux/usb/ch9.h>
  31#include <linux/usb/gadget.h>
  32#include <linux/usb/of.h>
  33#include <linux/usb/otg.h>
  34
  35#include "core.h"
  36#include "gadget.h"
  37#include "io.h"
  38
  39#include "debug.h"
  40
  41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43/**
  44 * dwc3_get_dr_mode - Validates and sets dr_mode
  45 * @dwc: pointer to our context structure
  46 */
  47static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48{
  49        enum usb_dr_mode mode;
  50        struct device *dev = dwc->dev;
  51        unsigned int hw_mode;
  52
  53        if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56        mode = dwc->dr_mode;
  57        hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59        switch (hw_mode) {
  60        case DWC3_GHWPARAMS0_MODE_GADGET:
  61                if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                        dev_err(dev,
  63                                "Controller does not support host mode.\n");
  64                        return -EINVAL;
  65                }
  66                mode = USB_DR_MODE_PERIPHERAL;
  67                break;
  68        case DWC3_GHWPARAMS0_MODE_HOST:
  69                if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                        dev_err(dev,
  71                                "Controller does not support device mode.\n");
  72                        return -EINVAL;
  73                }
  74                mode = USB_DR_MODE_HOST;
  75                break;
  76        default:
  77                if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                        mode = USB_DR_MODE_HOST;
  79                else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                        mode = USB_DR_MODE_PERIPHERAL;
  81
  82                /*
  83                 * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                 * mode. If the controller supports DRD but the dr_mode is not
  85                 * specified or set to OTG, then set the mode to peripheral.
  86                 */
  87                if (mode == USB_DR_MODE_OTG &&
  88                    (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  89                     !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  90                    !DWC3_VER_IS_PRIOR(DWC3, 330A))
  91                        mode = USB_DR_MODE_PERIPHERAL;
  92        }
  93
  94        if (mode != dwc->dr_mode) {
  95                dev_warn(dev,
  96                         "Configuration mismatch. dr_mode forced to %s\n",
  97                         mode == USB_DR_MODE_HOST ? "host" : "gadget");
  98
  99                dwc->dr_mode = mode;
 100        }
 101
 102        return 0;
 103}
 104
 105void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 106{
 107        u32 reg;
 108
 109        reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 110        reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 111        reg |= DWC3_GCTL_PRTCAPDIR(mode);
 112        dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 113
 114        dwc->current_dr_role = mode;
 115}
 116
 117static int dwc3_core_soft_reset(struct dwc3 *dwc);
 118
 119static void __dwc3_set_mode(struct work_struct *work)
 120{
 121        struct dwc3 *dwc = work_to_dwc(work);
 122        unsigned long flags;
 123        int ret;
 124        u32 reg;
 125
 126        mutex_lock(&dwc->mutex);
 127
 128        pm_runtime_get_sync(dwc->dev);
 129
 130        if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 131                dwc3_otg_update(dwc, 0);
 132
 133        if (!dwc->desired_dr_role)
 134                goto out;
 135
 136        if (dwc->desired_dr_role == dwc->current_dr_role)
 137                goto out;
 138
 139        if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 140                goto out;
 141
 142        switch (dwc->current_dr_role) {
 143        case DWC3_GCTL_PRTCAP_HOST:
 144                dwc3_host_exit(dwc);
 145                break;
 146        case DWC3_GCTL_PRTCAP_DEVICE:
 147                dwc3_gadget_exit(dwc);
 148                dwc3_event_buffers_cleanup(dwc);
 149                break;
 150        case DWC3_GCTL_PRTCAP_OTG:
 151                dwc3_otg_exit(dwc);
 152                spin_lock_irqsave(&dwc->lock, flags);
 153                dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 154                spin_unlock_irqrestore(&dwc->lock, flags);
 155                dwc3_otg_update(dwc, 1);
 156                break;
 157        default:
 158                break;
 159        }
 160
 161        /* For DRD host or device mode only */
 162        if (dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG) {
 163                reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 164                reg |= DWC3_GCTL_CORESOFTRESET;
 165                dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 166
 167                /*
 168                 * Wait for internal clocks to synchronized. DWC_usb31 and
 169                 * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 170                 * keep it consistent across different IPs, let's wait up to
 171                 * 100ms before clearing GCTL.CORESOFTRESET.
 172                 */
 173                msleep(100);
 174
 175                reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 176                reg &= ~DWC3_GCTL_CORESOFTRESET;
 177                dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 178        }
 179
 180        spin_lock_irqsave(&dwc->lock, flags);
 181
 182        dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 183
 184        spin_unlock_irqrestore(&dwc->lock, flags);
 185
 186        switch (dwc->desired_dr_role) {
 187        case DWC3_GCTL_PRTCAP_HOST:
 188                ret = dwc3_host_init(dwc);
 189                if (ret) {
 190                        dev_err(dwc->dev, "failed to initialize host\n");
 191                } else {
 192                        if (dwc->usb2_phy)
 193                                otg_set_vbus(dwc->usb2_phy->otg, true);
 194                        phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 195                        phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 196                        if (dwc->dis_split_quirk) {
 197                                reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 198                                reg |= DWC3_GUCTL3_SPLITDISABLE;
 199                                dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 200                        }
 201                }
 202                break;
 203        case DWC3_GCTL_PRTCAP_DEVICE:
 204                dwc3_core_soft_reset(dwc);
 205
 206                dwc3_event_buffers_setup(dwc);
 207
 208                if (dwc->usb2_phy)
 209                        otg_set_vbus(dwc->usb2_phy->otg, false);
 210                phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 211                phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 212
 213                ret = dwc3_gadget_init(dwc);
 214                if (ret)
 215                        dev_err(dwc->dev, "failed to initialize peripheral\n");
 216                break;
 217        case DWC3_GCTL_PRTCAP_OTG:
 218                dwc3_otg_init(dwc);
 219                dwc3_otg_update(dwc, 0);
 220                break;
 221        default:
 222                break;
 223        }
 224
 225out:
 226        pm_runtime_mark_last_busy(dwc->dev);
 227        pm_runtime_put_autosuspend(dwc->dev);
 228        mutex_unlock(&dwc->mutex);
 229}
 230
 231void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 232{
 233        unsigned long flags;
 234
 235        if (dwc->dr_mode != USB_DR_MODE_OTG)
 236                return;
 237
 238        spin_lock_irqsave(&dwc->lock, flags);
 239        dwc->desired_dr_role = mode;
 240        spin_unlock_irqrestore(&dwc->lock, flags);
 241
 242        queue_work(system_freezable_wq, &dwc->drd_work);
 243}
 244
 245u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 246{
 247        struct dwc3             *dwc = dep->dwc;
 248        u32                     reg;
 249
 250        dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 251                        DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 252                        DWC3_GDBGFIFOSPACE_TYPE(type));
 253
 254        reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 255
 256        return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 257}
 258
 259/**
 260 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 261 * @dwc: pointer to our context structure
 262 */
 263static int dwc3_core_soft_reset(struct dwc3 *dwc)
 264{
 265        u32             reg;
 266        int             retries = 1000;
 267        int             ret;
 268
 269        usb_phy_init(dwc->usb2_phy);
 270        usb_phy_init(dwc->usb3_phy);
 271        ret = phy_init(dwc->usb2_generic_phy);
 272        if (ret < 0)
 273                return ret;
 274
 275        ret = phy_init(dwc->usb3_generic_phy);
 276        if (ret < 0) {
 277                phy_exit(dwc->usb2_generic_phy);
 278                return ret;
 279        }
 280
 281        /*
 282         * We're resetting only the device side because, if we're in host mode,
 283         * XHCI driver will reset the host block. If dwc3 was configured for
 284         * host-only mode, then we can return early.
 285         */
 286        if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 287                return 0;
 288
 289        reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 290        reg |= DWC3_DCTL_CSFTRST;
 291        dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 292
 293        /*
 294         * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 295         * is cleared only after all the clocks are synchronized. This can
 296         * take a little more than 50ms. Set the polling rate at 20ms
 297         * for 10 times instead.
 298         */
 299        if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 300                retries = 10;
 301
 302        do {
 303                reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 304                if (!(reg & DWC3_DCTL_CSFTRST))
 305                        goto done;
 306
 307                if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 308                        msleep(20);
 309                else
 310                        udelay(1);
 311        } while (--retries);
 312
 313        phy_exit(dwc->usb3_generic_phy);
 314        phy_exit(dwc->usb2_generic_phy);
 315
 316        return -ETIMEDOUT;
 317
 318done:
 319        /*
 320         * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 321         * is cleared, we must wait at least 50ms before accessing the PHY
 322         * domain (synchronization delay).
 323         */
 324        if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 325                msleep(50);
 326
 327        return 0;
 328}
 329
 330/*
 331 * dwc3_frame_length_adjustment - Adjusts frame length if required
 332 * @dwc3: Pointer to our controller context structure
 333 */
 334static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 335{
 336        u32 reg;
 337        u32 dft;
 338
 339        if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 340                return;
 341
 342        if (dwc->fladj == 0)
 343                return;
 344
 345        reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 346        dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 347        if (dft != dwc->fladj) {
 348                reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 349                reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 350                dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 351        }
 352}
 353
 354/**
 355 * dwc3_free_one_event_buffer - Frees one event buffer
 356 * @dwc: Pointer to our controller context structure
 357 * @evt: Pointer to event buffer to be freed
 358 */
 359static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 360                struct dwc3_event_buffer *evt)
 361{
 362        dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 363}
 364
 365/**
 366 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 367 * @dwc: Pointer to our controller context structure
 368 * @length: size of the event buffer
 369 *
 370 * Returns a pointer to the allocated event buffer structure on success
 371 * otherwise ERR_PTR(errno).
 372 */
 373static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 374                unsigned length)
 375{
 376        struct dwc3_event_buffer        *evt;
 377
 378        evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 379        if (!evt)
 380                return ERR_PTR(-ENOMEM);
 381
 382        evt->dwc        = dwc;
 383        evt->length     = length;
 384        evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 385        if (!evt->cache)
 386                return ERR_PTR(-ENOMEM);
 387
 388        evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 389                        &evt->dma, GFP_KERNEL);
 390        if (!evt->buf)
 391                return ERR_PTR(-ENOMEM);
 392
 393        return evt;
 394}
 395
 396/**
 397 * dwc3_free_event_buffers - frees all allocated event buffers
 398 * @dwc: Pointer to our controller context structure
 399 */
 400static void dwc3_free_event_buffers(struct dwc3 *dwc)
 401{
 402        struct dwc3_event_buffer        *evt;
 403
 404        evt = dwc->ev_buf;
 405        if (evt)
 406                dwc3_free_one_event_buffer(dwc, evt);
 407}
 408
 409/**
 410 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 411 * @dwc: pointer to our controller context structure
 412 * @length: size of event buffer
 413 *
 414 * Returns 0 on success otherwise negative errno. In the error case, dwc
 415 * may contain some buffers allocated but not all which were requested.
 416 */
 417static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 418{
 419        struct dwc3_event_buffer *evt;
 420
 421        evt = dwc3_alloc_one_event_buffer(dwc, length);
 422        if (IS_ERR(evt)) {
 423                dev_err(dwc->dev, "can't allocate event buffer\n");
 424                return PTR_ERR(evt);
 425        }
 426        dwc->ev_buf = evt;
 427
 428        return 0;
 429}
 430
 431/**
 432 * dwc3_event_buffers_setup - setup our allocated event buffers
 433 * @dwc: pointer to our controller context structure
 434 *
 435 * Returns 0 on success otherwise negative errno.
 436 */
 437int dwc3_event_buffers_setup(struct dwc3 *dwc)
 438{
 439        struct dwc3_event_buffer        *evt;
 440
 441        evt = dwc->ev_buf;
 442        evt->lpos = 0;
 443        dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 444                        lower_32_bits(evt->dma));
 445        dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 446                        upper_32_bits(evt->dma));
 447        dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 448                        DWC3_GEVNTSIZ_SIZE(evt->length));
 449        dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 450
 451        return 0;
 452}
 453
 454void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 455{
 456        struct dwc3_event_buffer        *evt;
 457
 458        evt = dwc->ev_buf;
 459
 460        evt->lpos = 0;
 461
 462        dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 463        dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 464        dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 465                        | DWC3_GEVNTSIZ_SIZE(0));
 466        dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 467}
 468
 469static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 470{
 471        if (!dwc->has_hibernation)
 472                return 0;
 473
 474        if (!dwc->nr_scratch)
 475                return 0;
 476
 477        dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 478                        DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 479        if (!dwc->scratchbuf)
 480                return -ENOMEM;
 481
 482        return 0;
 483}
 484
 485static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 486{
 487        dma_addr_t scratch_addr;
 488        u32 param;
 489        int ret;
 490
 491        if (!dwc->has_hibernation)
 492                return 0;
 493
 494        if (!dwc->nr_scratch)
 495                return 0;
 496
 497         /* should never fall here */
 498        if (!WARN_ON(dwc->scratchbuf))
 499                return 0;
 500
 501        scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 502                        dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 503                        DMA_BIDIRECTIONAL);
 504        if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 505                dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 506                ret = -EFAULT;
 507                goto err0;
 508        }
 509
 510        dwc->scratch_addr = scratch_addr;
 511
 512        param = lower_32_bits(scratch_addr);
 513
 514        ret = dwc3_send_gadget_generic_command(dwc,
 515                        DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 516        if (ret < 0)
 517                goto err1;
 518
 519        param = upper_32_bits(scratch_addr);
 520
 521        ret = dwc3_send_gadget_generic_command(dwc,
 522                        DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 523        if (ret < 0)
 524                goto err1;
 525
 526        return 0;
 527
 528err1:
 529        dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 530                        DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 531
 532err0:
 533        return ret;
 534}
 535
 536static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 537{
 538        if (!dwc->has_hibernation)
 539                return;
 540
 541        if (!dwc->nr_scratch)
 542                return;
 543
 544         /* should never fall here */
 545        if (!WARN_ON(dwc->scratchbuf))
 546                return;
 547
 548        dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 549                        DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 550        kfree(dwc->scratchbuf);
 551}
 552
 553static void dwc3_core_num_eps(struct dwc3 *dwc)
 554{
 555        struct dwc3_hwparams    *parms = &dwc->hwparams;
 556
 557        dwc->num_eps = DWC3_NUM_EPS(parms);
 558}
 559
 560static void dwc3_cache_hwparams(struct dwc3 *dwc)
 561{
 562        struct dwc3_hwparams    *parms = &dwc->hwparams;
 563
 564        parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 565        parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 566        parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 567        parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 568        parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 569        parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 570        parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 571        parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 572        parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 573
 574        if (DWC3_IP_IS(DWC32))
 575                parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 576}
 577
 578static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 579{
 580        int intf;
 581        int ret = 0;
 582
 583        intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 584
 585        if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 586            (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 587             dwc->hsphy_interface &&
 588             !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 589                ret = dwc3_ulpi_init(dwc);
 590
 591        return ret;
 592}
 593
 594/**
 595 * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 596 * @dwc: Pointer to our controller context structure
 597 *
 598 * Returns 0 on success. The USB PHY interfaces are configured but not
 599 * initialized. The PHY interfaces and the PHYs get initialized together with
 600 * the core in dwc3_core_init.
 601 */
 602static int dwc3_phy_setup(struct dwc3 *dwc)
 603{
 604        unsigned int hw_mode;
 605        u32 reg;
 606
 607        hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 608
 609        reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 610
 611        /*
 612         * Make sure UX_EXIT_PX is cleared as that causes issues with some
 613         * PHYs. Also, this bit is not supposed to be used in normal operation.
 614         */
 615        reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 616
 617        /*
 618         * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 619         * to '0' during coreConsultant configuration. So default value
 620         * will be '0' when the core is reset. Application needs to set it
 621         * to '1' after the core initialization is completed.
 622         */
 623        if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 624                reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 625
 626        /*
 627         * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 628         * power-on reset, and it can be set after core initialization, which is
 629         * after device soft-reset during initialization.
 630         */
 631        if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 632                reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 633
 634        if (dwc->u2ss_inp3_quirk)
 635                reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 636
 637        if (dwc->dis_rxdet_inp3_quirk)
 638                reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 639
 640        if (dwc->req_p1p2p3_quirk)
 641                reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 642
 643        if (dwc->del_p1p2p3_quirk)
 644                reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 645
 646        if (dwc->del_phy_power_chg_quirk)
 647                reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 648
 649        if (dwc->lfps_filter_quirk)
 650                reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 651
 652        if (dwc->rx_detect_poll_quirk)
 653                reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 654
 655        if (dwc->tx_de_emphasis_quirk)
 656                reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 657
 658        if (dwc->dis_u3_susphy_quirk)
 659                reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 660
 661        if (dwc->dis_del_phy_power_chg_quirk)
 662                reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 663
 664        dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 665
 666        reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 667
 668        /* Select the HS PHY interface */
 669        switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 670        case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 671                if (dwc->hsphy_interface &&
 672                                !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 673                        reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 674                        break;
 675                } else if (dwc->hsphy_interface &&
 676                                !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 677                        reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 678                        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 679                } else {
 680                        /* Relying on default value. */
 681                        if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 682                                break;
 683                }
 684                fallthrough;
 685        case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 686        default:
 687                break;
 688        }
 689
 690        switch (dwc->hsphy_mode) {
 691        case USBPHY_INTERFACE_MODE_UTMI:
 692                reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 693                       DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 694                reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 695                       DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 696                break;
 697        case USBPHY_INTERFACE_MODE_UTMIW:
 698                reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 699                       DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 700                reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 701                       DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 702                break;
 703        default:
 704                break;
 705        }
 706
 707        /*
 708         * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 709         * '0' during coreConsultant configuration. So default value will
 710         * be '0' when the core is reset. Application needs to set it to
 711         * '1' after the core initialization is completed.
 712         */
 713        if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 714                reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 715
 716        /*
 717         * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 718         * power-on reset, and it can be set after core initialization, which is
 719         * after device soft-reset during initialization.
 720         */
 721        if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 722                reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 723
 724        if (dwc->dis_u2_susphy_quirk)
 725                reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 726
 727        if (dwc->dis_enblslpm_quirk)
 728                reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 729        else
 730                reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 731
 732        if (dwc->dis_u2_freeclk_exists_quirk)
 733                reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 734
 735        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 736
 737        return 0;
 738}
 739
 740static void dwc3_core_exit(struct dwc3 *dwc)
 741{
 742        dwc3_event_buffers_cleanup(dwc);
 743
 744        usb_phy_shutdown(dwc->usb2_phy);
 745        usb_phy_shutdown(dwc->usb3_phy);
 746        phy_exit(dwc->usb2_generic_phy);
 747        phy_exit(dwc->usb3_generic_phy);
 748
 749        usb_phy_set_suspend(dwc->usb2_phy, 1);
 750        usb_phy_set_suspend(dwc->usb3_phy, 1);
 751        phy_power_off(dwc->usb2_generic_phy);
 752        phy_power_off(dwc->usb3_generic_phy);
 753        clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 754        reset_control_assert(dwc->reset);
 755}
 756
 757static bool dwc3_core_is_valid(struct dwc3 *dwc)
 758{
 759        u32 reg;
 760
 761        reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 762        dwc->ip = DWC3_GSNPS_ID(reg);
 763
 764        /* This should read as U3 followed by revision number */
 765        if (DWC3_IP_IS(DWC3)) {
 766                dwc->revision = reg;
 767        } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 768                dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 769                dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 770        } else {
 771                return false;
 772        }
 773
 774        return true;
 775}
 776
 777static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 778{
 779        u32 hwparams4 = dwc->hwparams.hwparams4;
 780        u32 reg;
 781
 782        reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 783        reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 784
 785        switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 786        case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 787                /**
 788                 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 789                 * issue which would cause xHCI compliance tests to fail.
 790                 *
 791                 * Because of that we cannot enable clock gating on such
 792                 * configurations.
 793                 *
 794                 * Refers to:
 795                 *
 796                 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 797                 * SOF/ITP Mode Used
 798                 */
 799                if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 800                                dwc->dr_mode == USB_DR_MODE_OTG) &&
 801                                DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 802                        reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 803                else
 804                        reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 805                break;
 806        case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 807                /* enable hibernation here */
 808                dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 809
 810                /*
 811                 * REVISIT Enabling this bit so that host-mode hibernation
 812                 * will work. Device-mode hibernation is not yet implemented.
 813                 */
 814                reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 815                break;
 816        default:
 817                /* nothing */
 818                break;
 819        }
 820
 821        /* check if current dwc3 is on simulation board */
 822        if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 823                dev_info(dwc->dev, "Running with FPGA optimizations\n");
 824                dwc->is_fpga = true;
 825        }
 826
 827        WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 828                        "disable_scramble cannot be used on non-FPGA builds\n");
 829
 830        if (dwc->disable_scramble_quirk && dwc->is_fpga)
 831                reg |= DWC3_GCTL_DISSCRAMBLE;
 832        else
 833                reg &= ~DWC3_GCTL_DISSCRAMBLE;
 834
 835        if (dwc->u2exit_lfps_quirk)
 836                reg |= DWC3_GCTL_U2EXIT_LFPS;
 837
 838        /*
 839         * WORKAROUND: DWC3 revisions <1.90a have a bug
 840         * where the device can fail to connect at SuperSpeed
 841         * and falls back to high-speed mode which causes
 842         * the device to enter a Connect/Disconnect loop
 843         */
 844        if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 845                reg |= DWC3_GCTL_U2RSTECN;
 846
 847        dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 848}
 849
 850static int dwc3_core_get_phy(struct dwc3 *dwc);
 851static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 852
 853/* set global incr burst type configuration registers */
 854static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 855{
 856        struct device *dev = dwc->dev;
 857        /* incrx_mode : for INCR burst type. */
 858        bool incrx_mode;
 859        /* incrx_size : for size of INCRX burst. */
 860        u32 incrx_size;
 861        u32 *vals;
 862        u32 cfg;
 863        int ntype;
 864        int ret;
 865        int i;
 866
 867        cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 868
 869        /*
 870         * Handle property "snps,incr-burst-type-adjustment".
 871         * Get the number of value from this property:
 872         * result <= 0, means this property is not supported.
 873         * result = 1, means INCRx burst mode supported.
 874         * result > 1, means undefined length burst mode supported.
 875         */
 876        ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 877        if (ntype <= 0)
 878                return;
 879
 880        vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 881        if (!vals) {
 882                dev_err(dev, "Error to get memory\n");
 883                return;
 884        }
 885
 886        /* Get INCR burst type, and parse it */
 887        ret = device_property_read_u32_array(dev,
 888                        "snps,incr-burst-type-adjustment", vals, ntype);
 889        if (ret) {
 890                kfree(vals);
 891                dev_err(dev, "Error to get property\n");
 892                return;
 893        }
 894
 895        incrx_size = *vals;
 896
 897        if (ntype > 1) {
 898                /* INCRX (undefined length) burst mode */
 899                incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 900                for (i = 1; i < ntype; i++) {
 901                        if (vals[i] > incrx_size)
 902                                incrx_size = vals[i];
 903                }
 904        } else {
 905                /* INCRX burst mode */
 906                incrx_mode = INCRX_BURST_MODE;
 907        }
 908
 909        kfree(vals);
 910
 911        /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 912        cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 913        if (incrx_mode)
 914                cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 915        switch (incrx_size) {
 916        case 256:
 917                cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 918                break;
 919        case 128:
 920                cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 921                break;
 922        case 64:
 923                cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 924                break;
 925        case 32:
 926                cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 927                break;
 928        case 16:
 929                cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 930                break;
 931        case 8:
 932                cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 933                break;
 934        case 4:
 935                cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 936                break;
 937        case 1:
 938                break;
 939        default:
 940                dev_err(dev, "Invalid property\n");
 941                break;
 942        }
 943
 944        dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 945}
 946
 947/**
 948 * dwc3_core_init - Low-level initialization of DWC3 Core
 949 * @dwc: Pointer to our controller context structure
 950 *
 951 * Returns 0 on success otherwise negative errno.
 952 */
 953static int dwc3_core_init(struct dwc3 *dwc)
 954{
 955        unsigned int            hw_mode;
 956        u32                     reg;
 957        int                     ret;
 958
 959        hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 960
 961        /*
 962         * Write Linux Version Code to our GUID register so it's easy to figure
 963         * out which kernel version a bug was found.
 964         */
 965        dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 966
 967        ret = dwc3_phy_setup(dwc);
 968        if (ret)
 969                goto err0;
 970
 971        if (!dwc->ulpi_ready) {
 972                ret = dwc3_core_ulpi_init(dwc);
 973                if (ret)
 974                        goto err0;
 975                dwc->ulpi_ready = true;
 976        }
 977
 978        if (!dwc->phys_ready) {
 979                ret = dwc3_core_get_phy(dwc);
 980                if (ret)
 981                        goto err0a;
 982                dwc->phys_ready = true;
 983        }
 984
 985        ret = dwc3_core_soft_reset(dwc);
 986        if (ret)
 987                goto err0a;
 988
 989        if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
 990            !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
 991                if (!dwc->dis_u3_susphy_quirk) {
 992                        reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 993                        reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 994                        dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 995                }
 996
 997                if (!dwc->dis_u2_susphy_quirk) {
 998                        reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 999                        reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1000                        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1001                }
1002        }
1003
1004        dwc3_core_setup_global_control(dwc);
1005        dwc3_core_num_eps(dwc);
1006
1007        ret = dwc3_setup_scratch_buffers(dwc);
1008        if (ret)
1009                goto err1;
1010
1011        /* Adjust Frame Length */
1012        dwc3_frame_length_adjustment(dwc);
1013
1014        dwc3_set_incr_burst_type(dwc);
1015
1016        usb_phy_set_suspend(dwc->usb2_phy, 0);
1017        usb_phy_set_suspend(dwc->usb3_phy, 0);
1018        ret = phy_power_on(dwc->usb2_generic_phy);
1019        if (ret < 0)
1020                goto err2;
1021
1022        ret = phy_power_on(dwc->usb3_generic_phy);
1023        if (ret < 0)
1024                goto err3;
1025
1026        ret = dwc3_event_buffers_setup(dwc);
1027        if (ret) {
1028                dev_err(dwc->dev, "failed to setup event buffers\n");
1029                goto err4;
1030        }
1031
1032        /*
1033         * ENDXFER polling is available on version 3.10a and later of
1034         * the DWC_usb3 controller. It is NOT available in the
1035         * DWC_usb31 controller.
1036         */
1037        if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1038                reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1039                reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1040                dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1041        }
1042
1043        if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1044                reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1045
1046                /*
1047                 * Enable hardware control of sending remote wakeup
1048                 * in HS when the device is in the L1 state.
1049                 */
1050                if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1051                        reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1052
1053                if (dwc->dis_tx_ipgap_linecheck_quirk)
1054                        reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1055
1056                if (dwc->parkmode_disable_ss_quirk)
1057                        reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1058
1059                dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1060        }
1061
1062        if (dwc->dr_mode == USB_DR_MODE_HOST ||
1063            dwc->dr_mode == USB_DR_MODE_OTG) {
1064                reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1065
1066                /*
1067                 * Enable Auto retry Feature to make the controller operating in
1068                 * Host mode on seeing transaction errors(CRC errors or internal
1069                 * overrun scenerios) on IN transfers to reply to the device
1070                 * with a non-terminating retry ACK (i.e, an ACK transcation
1071                 * packet with Retry=1 & Nump != 0)
1072                 */
1073                reg |= DWC3_GUCTL_HSTINAUTORETRY;
1074
1075                dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1076        }
1077
1078        /*
1079         * Must config both number of packets and max burst settings to enable
1080         * RX and/or TX threshold.
1081         */
1082        if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1083                u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1084                u8 rx_maxburst = dwc->rx_max_burst_prd;
1085                u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1086                u8 tx_maxburst = dwc->tx_max_burst_prd;
1087
1088                if (rx_thr_num && rx_maxburst) {
1089                        reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1090                        reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1091
1092                        reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1093                        reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1094
1095                        reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1096                        reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1097
1098                        dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1099                }
1100
1101                if (tx_thr_num && tx_maxburst) {
1102                        reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1103                        reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1104
1105                        reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1106                        reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1107
1108                        reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1109                        reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1110
1111                        dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1112                }
1113        }
1114
1115        return 0;
1116
1117err4:
1118        phy_power_off(dwc->usb3_generic_phy);
1119
1120err3:
1121        phy_power_off(dwc->usb2_generic_phy);
1122
1123err2:
1124        usb_phy_set_suspend(dwc->usb2_phy, 1);
1125        usb_phy_set_suspend(dwc->usb3_phy, 1);
1126
1127err1:
1128        usb_phy_shutdown(dwc->usb2_phy);
1129        usb_phy_shutdown(dwc->usb3_phy);
1130        phy_exit(dwc->usb2_generic_phy);
1131        phy_exit(dwc->usb3_generic_phy);
1132
1133err0a:
1134        dwc3_ulpi_exit(dwc);
1135
1136err0:
1137        return ret;
1138}
1139
1140static int dwc3_core_get_phy(struct dwc3 *dwc)
1141{
1142        struct device           *dev = dwc->dev;
1143        struct device_node      *node = dev->of_node;
1144        int ret;
1145
1146        if (node) {
1147                dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1148                dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1149        } else {
1150                dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1151                dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1152        }
1153
1154        if (IS_ERR(dwc->usb2_phy)) {
1155                ret = PTR_ERR(dwc->usb2_phy);
1156                if (ret == -ENXIO || ret == -ENODEV) {
1157                        dwc->usb2_phy = NULL;
1158                } else {
1159                        return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1160                }
1161        }
1162
1163        if (IS_ERR(dwc->usb3_phy)) {
1164                ret = PTR_ERR(dwc->usb3_phy);
1165                if (ret == -ENXIO || ret == -ENODEV) {
1166                        dwc->usb3_phy = NULL;
1167                } else {
1168                        return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1169                }
1170        }
1171
1172        dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1173        if (IS_ERR(dwc->usb2_generic_phy)) {
1174                ret = PTR_ERR(dwc->usb2_generic_phy);
1175                if (ret == -ENOSYS || ret == -ENODEV) {
1176                        dwc->usb2_generic_phy = NULL;
1177                } else {
1178                        return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1179                }
1180        }
1181
1182        dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1183        if (IS_ERR(dwc->usb3_generic_phy)) {
1184                ret = PTR_ERR(dwc->usb3_generic_phy);
1185                if (ret == -ENOSYS || ret == -ENODEV) {
1186                        dwc->usb3_generic_phy = NULL;
1187                } else {
1188                        return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1189                }
1190        }
1191
1192        return 0;
1193}
1194
1195static int dwc3_core_init_mode(struct dwc3 *dwc)
1196{
1197        struct device *dev = dwc->dev;
1198        int ret;
1199
1200        switch (dwc->dr_mode) {
1201        case USB_DR_MODE_PERIPHERAL:
1202                dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1203
1204                if (dwc->usb2_phy)
1205                        otg_set_vbus(dwc->usb2_phy->otg, false);
1206                phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1207                phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1208
1209                ret = dwc3_gadget_init(dwc);
1210                if (ret)
1211                        return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1212                break;
1213        case USB_DR_MODE_HOST:
1214                dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1215
1216                if (dwc->usb2_phy)
1217                        otg_set_vbus(dwc->usb2_phy->otg, true);
1218                phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1219                phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1220
1221                ret = dwc3_host_init(dwc);
1222                if (ret)
1223                        return dev_err_probe(dev, ret, "failed to initialize host\n");
1224                break;
1225        case USB_DR_MODE_OTG:
1226                INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1227                ret = dwc3_drd_init(dwc);
1228                if (ret)
1229                        return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1230                break;
1231        default:
1232                dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1233                return -EINVAL;
1234        }
1235
1236        return 0;
1237}
1238
1239static void dwc3_core_exit_mode(struct dwc3 *dwc)
1240{
1241        switch (dwc->dr_mode) {
1242        case USB_DR_MODE_PERIPHERAL:
1243                dwc3_gadget_exit(dwc);
1244                break;
1245        case USB_DR_MODE_HOST:
1246                dwc3_host_exit(dwc);
1247                break;
1248        case USB_DR_MODE_OTG:
1249                dwc3_drd_exit(dwc);
1250                break;
1251        default:
1252                /* do nothing */
1253                break;
1254        }
1255
1256        /* de-assert DRVVBUS for HOST and OTG mode */
1257        dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1258}
1259
1260static void dwc3_get_properties(struct dwc3 *dwc)
1261{
1262        struct device           *dev = dwc->dev;
1263        u8                      lpm_nyet_threshold;
1264        u8                      tx_de_emphasis;
1265        u8                      hird_threshold;
1266        u8                      rx_thr_num_pkt_prd;
1267        u8                      rx_max_burst_prd;
1268        u8                      tx_thr_num_pkt_prd;
1269        u8                      tx_max_burst_prd;
1270        const char              *usb_psy_name;
1271        int                     ret;
1272
1273        /* default to highest possible threshold */
1274        lpm_nyet_threshold = 0xf;
1275
1276        /* default to -3.5dB de-emphasis */
1277        tx_de_emphasis = 1;
1278
1279        /*
1280         * default to assert utmi_sleep_n and use maximum allowed HIRD
1281         * threshold value of 0b1100
1282         */
1283        hird_threshold = 12;
1284
1285        dwc->maximum_speed = usb_get_maximum_speed(dev);
1286        dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1287        dwc->dr_mode = usb_get_dr_mode(dev);
1288        dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1289
1290        dwc->sysdev_is_parent = device_property_read_bool(dev,
1291                                "linux,sysdev_is_parent");
1292        if (dwc->sysdev_is_parent)
1293                dwc->sysdev = dwc->dev->parent;
1294        else
1295                dwc->sysdev = dwc->dev;
1296
1297        ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1298        if (ret >= 0) {
1299                dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1300                if (!dwc->usb_psy)
1301                        dev_err(dev, "couldn't get usb power supply\n");
1302        }
1303
1304        dwc->has_lpm_erratum = device_property_read_bool(dev,
1305                                "snps,has-lpm-erratum");
1306        device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1307                                &lpm_nyet_threshold);
1308        dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1309                                "snps,is-utmi-l1-suspend");
1310        device_property_read_u8(dev, "snps,hird-threshold",
1311                                &hird_threshold);
1312        dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1313                                "snps,dis-start-transfer-quirk");
1314        dwc->usb3_lpm_capable = device_property_read_bool(dev,
1315                                "snps,usb3_lpm_capable");
1316        dwc->usb2_lpm_disable = device_property_read_bool(dev,
1317                                "snps,usb2-lpm-disable");
1318        dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1319                                "snps,usb2-gadget-lpm-disable");
1320        device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1321                                &rx_thr_num_pkt_prd);
1322        device_property_read_u8(dev, "snps,rx-max-burst-prd",
1323                                &rx_max_burst_prd);
1324        device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1325                                &tx_thr_num_pkt_prd);
1326        device_property_read_u8(dev, "snps,tx-max-burst-prd",
1327                                &tx_max_burst_prd);
1328
1329        dwc->disable_scramble_quirk = device_property_read_bool(dev,
1330                                "snps,disable_scramble_quirk");
1331        dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1332                                "snps,u2exit_lfps_quirk");
1333        dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1334                                "snps,u2ss_inp3_quirk");
1335        dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1336                                "snps,req_p1p2p3_quirk");
1337        dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1338                                "snps,del_p1p2p3_quirk");
1339        dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1340                                "snps,del_phy_power_chg_quirk");
1341        dwc->lfps_filter_quirk = device_property_read_bool(dev,
1342                                "snps,lfps_filter_quirk");
1343        dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1344                                "snps,rx_detect_poll_quirk");
1345        dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1346                                "snps,dis_u3_susphy_quirk");
1347        dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1348                                "snps,dis_u2_susphy_quirk");
1349        dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1350                                "snps,dis_enblslpm_quirk");
1351        dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1352                                "snps,dis-u1-entry-quirk");
1353        dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1354                                "snps,dis-u2-entry-quirk");
1355        dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1356                                "snps,dis_rxdet_inp3_quirk");
1357        dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1358                                "snps,dis-u2-freeclk-exists-quirk");
1359        dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1360                                "snps,dis-del-phy-power-chg-quirk");
1361        dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1362                                "snps,dis-tx-ipgap-linecheck-quirk");
1363        dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1364                                "snps,parkmode-disable-ss-quirk");
1365
1366        dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1367                                "snps,tx_de_emphasis_quirk");
1368        device_property_read_u8(dev, "snps,tx_de_emphasis",
1369                                &tx_de_emphasis);
1370        device_property_read_string(dev, "snps,hsphy_interface",
1371                                    &dwc->hsphy_interface);
1372        device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1373                                 &dwc->fladj);
1374
1375        dwc->dis_metastability_quirk = device_property_read_bool(dev,
1376                                "snps,dis_metastability_quirk");
1377
1378        dwc->dis_split_quirk = device_property_read_bool(dev,
1379                                "snps,dis-split-quirk");
1380
1381        dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1382        dwc->tx_de_emphasis = tx_de_emphasis;
1383
1384        dwc->hird_threshold = hird_threshold;
1385
1386        dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1387        dwc->rx_max_burst_prd = rx_max_burst_prd;
1388
1389        dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1390        dwc->tx_max_burst_prd = tx_max_burst_prd;
1391
1392        dwc->imod_interval = 0;
1393}
1394
1395/* check whether the core supports IMOD */
1396bool dwc3_has_imod(struct dwc3 *dwc)
1397{
1398        return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1399                DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1400                DWC3_IP_IS(DWC32);
1401}
1402
1403static void dwc3_check_params(struct dwc3 *dwc)
1404{
1405        struct device *dev = dwc->dev;
1406        unsigned int hwparam_gen =
1407                DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1408
1409        /* Check for proper value of imod_interval */
1410        if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1411                dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1412                dwc->imod_interval = 0;
1413        }
1414
1415        /*
1416         * Workaround for STAR 9000961433 which affects only version
1417         * 3.00a of the DWC_usb3 core. This prevents the controller
1418         * interrupt from being masked while handling events. IMOD
1419         * allows us to work around this issue. Enable it for the
1420         * affected version.
1421         */
1422        if (!dwc->imod_interval &&
1423            DWC3_VER_IS(DWC3, 300A))
1424                dwc->imod_interval = 1;
1425
1426        /* Check the maximum_speed parameter */
1427        switch (dwc->maximum_speed) {
1428        case USB_SPEED_FULL:
1429        case USB_SPEED_HIGH:
1430                break;
1431        case USB_SPEED_SUPER:
1432                if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1433                        dev_warn(dev, "UDC doesn't support Gen 1\n");
1434                break;
1435        case USB_SPEED_SUPER_PLUS:
1436                if ((DWC3_IP_IS(DWC32) &&
1437                     hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1438                    (!DWC3_IP_IS(DWC32) &&
1439                     hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1440                        dev_warn(dev, "UDC doesn't support SSP\n");
1441                break;
1442        default:
1443                dev_err(dev, "invalid maximum_speed parameter %d\n",
1444                        dwc->maximum_speed);
1445                fallthrough;
1446        case USB_SPEED_UNKNOWN:
1447                switch (hwparam_gen) {
1448                case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1449                        dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1450                        break;
1451                case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1452                        if (DWC3_IP_IS(DWC32))
1453                                dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1454                        else
1455                                dwc->maximum_speed = USB_SPEED_SUPER;
1456                        break;
1457                case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1458                        dwc->maximum_speed = USB_SPEED_HIGH;
1459                        break;
1460                default:
1461                        dwc->maximum_speed = USB_SPEED_SUPER;
1462                        break;
1463                }
1464                break;
1465        }
1466
1467        /*
1468         * Currently the controller does not have visibility into the HW
1469         * parameter to determine the maximum number of lanes the HW supports.
1470         * If the number of lanes is not specified in the device property, then
1471         * set the default to support dual-lane for DWC_usb32 and single-lane
1472         * for DWC_usb31 for super-speed-plus.
1473         */
1474        if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1475                switch (dwc->max_ssp_rate) {
1476                case USB_SSP_GEN_2x1:
1477                        if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1478                                dev_warn(dev, "UDC only supports Gen 1\n");
1479                        break;
1480                case USB_SSP_GEN_1x2:
1481                case USB_SSP_GEN_2x2:
1482                        if (DWC3_IP_IS(DWC31))
1483                                dev_warn(dev, "UDC only supports single lane\n");
1484                        break;
1485                case USB_SSP_GEN_UNKNOWN:
1486                default:
1487                        switch (hwparam_gen) {
1488                        case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1489                                if (DWC3_IP_IS(DWC32))
1490                                        dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1491                                else
1492                                        dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1493                                break;
1494                        case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1495                                if (DWC3_IP_IS(DWC32))
1496                                        dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1497                                break;
1498                        }
1499                        break;
1500                }
1501        }
1502}
1503
1504static int dwc3_probe(struct platform_device *pdev)
1505{
1506        struct device           *dev = &pdev->dev;
1507        struct resource         *res, dwc_res;
1508        struct dwc3             *dwc;
1509
1510        int                     ret;
1511
1512        void __iomem            *regs;
1513
1514        dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1515        if (!dwc)
1516                return -ENOMEM;
1517
1518        dwc->dev = dev;
1519
1520        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1521        if (!res) {
1522                dev_err(dev, "missing memory resource\n");
1523                return -ENODEV;
1524        }
1525
1526        dwc->xhci_resources[0].start = res->start;
1527        dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1528                                        DWC3_XHCI_REGS_END;
1529        dwc->xhci_resources[0].flags = res->flags;
1530        dwc->xhci_resources[0].name = res->name;
1531
1532        /*
1533         * Request memory region but exclude xHCI regs,
1534         * since it will be requested by the xhci-plat driver.
1535         */
1536        dwc_res = *res;
1537        dwc_res.start += DWC3_GLOBALS_REGS_START;
1538
1539        regs = devm_ioremap_resource(dev, &dwc_res);
1540        if (IS_ERR(regs))
1541                return PTR_ERR(regs);
1542
1543        dwc->regs       = regs;
1544        dwc->regs_size  = resource_size(&dwc_res);
1545
1546        dwc3_get_properties(dwc);
1547
1548        ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1549        if (ret)
1550                return ret;
1551
1552        dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1553        if (IS_ERR(dwc->reset))
1554                return PTR_ERR(dwc->reset);
1555
1556        if (dev->of_node) {
1557                ret = devm_clk_bulk_get_all(dev, &dwc->clks);
1558                if (ret == -EPROBE_DEFER)
1559                        return ret;
1560                /*
1561                 * Clocks are optional, but new DT platforms should support all
1562                 * clocks as required by the DT-binding.
1563                 */
1564                if (ret < 0)
1565                        dwc->num_clks = 0;
1566                else
1567                        dwc->num_clks = ret;
1568
1569        }
1570
1571        ret = reset_control_deassert(dwc->reset);
1572        if (ret)
1573                return ret;
1574
1575        ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1576        if (ret)
1577                goto assert_reset;
1578
1579        if (!dwc3_core_is_valid(dwc)) {
1580                dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1581                ret = -ENODEV;
1582                goto disable_clks;
1583        }
1584
1585        platform_set_drvdata(pdev, dwc);
1586        dwc3_cache_hwparams(dwc);
1587
1588        spin_lock_init(&dwc->lock);
1589        mutex_init(&dwc->mutex);
1590
1591        pm_runtime_set_active(dev);
1592        pm_runtime_use_autosuspend(dev);
1593        pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1594        pm_runtime_enable(dev);
1595        ret = pm_runtime_get_sync(dev);
1596        if (ret < 0)
1597                goto err1;
1598
1599        pm_runtime_forbid(dev);
1600
1601        ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1602        if (ret) {
1603                dev_err(dwc->dev, "failed to allocate event buffers\n");
1604                ret = -ENOMEM;
1605                goto err2;
1606        }
1607
1608        ret = dwc3_get_dr_mode(dwc);
1609        if (ret)
1610                goto err3;
1611
1612        ret = dwc3_alloc_scratch_buffers(dwc);
1613        if (ret)
1614                goto err3;
1615
1616        ret = dwc3_core_init(dwc);
1617        if (ret) {
1618                dev_err_probe(dev, ret, "failed to initialize core\n");
1619                goto err4;
1620        }
1621
1622        dwc3_check_params(dwc);
1623        dwc3_debugfs_init(dwc);
1624
1625        ret = dwc3_core_init_mode(dwc);
1626        if (ret)
1627                goto err5;
1628
1629        pm_runtime_put(dev);
1630
1631        return 0;
1632
1633err5:
1634        dwc3_debugfs_exit(dwc);
1635        dwc3_event_buffers_cleanup(dwc);
1636
1637        usb_phy_shutdown(dwc->usb2_phy);
1638        usb_phy_shutdown(dwc->usb3_phy);
1639        phy_exit(dwc->usb2_generic_phy);
1640        phy_exit(dwc->usb3_generic_phy);
1641
1642        usb_phy_set_suspend(dwc->usb2_phy, 1);
1643        usb_phy_set_suspend(dwc->usb3_phy, 1);
1644        phy_power_off(dwc->usb2_generic_phy);
1645        phy_power_off(dwc->usb3_generic_phy);
1646
1647        dwc3_ulpi_exit(dwc);
1648
1649err4:
1650        dwc3_free_scratch_buffers(dwc);
1651
1652err3:
1653        dwc3_free_event_buffers(dwc);
1654
1655err2:
1656        pm_runtime_allow(&pdev->dev);
1657
1658err1:
1659        pm_runtime_put_sync(&pdev->dev);
1660        pm_runtime_disable(&pdev->dev);
1661
1662disable_clks:
1663        clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1664assert_reset:
1665        reset_control_assert(dwc->reset);
1666
1667        if (dwc->usb_psy)
1668                power_supply_put(dwc->usb_psy);
1669
1670        return ret;
1671}
1672
1673static int dwc3_remove(struct platform_device *pdev)
1674{
1675        struct dwc3     *dwc = platform_get_drvdata(pdev);
1676
1677        pm_runtime_get_sync(&pdev->dev);
1678
1679        dwc3_core_exit_mode(dwc);
1680        dwc3_debugfs_exit(dwc);
1681
1682        dwc3_core_exit(dwc);
1683        dwc3_ulpi_exit(dwc);
1684
1685        pm_runtime_disable(&pdev->dev);
1686        pm_runtime_put_noidle(&pdev->dev);
1687        pm_runtime_set_suspended(&pdev->dev);
1688
1689        dwc3_free_event_buffers(dwc);
1690        dwc3_free_scratch_buffers(dwc);
1691
1692        if (dwc->usb_psy)
1693                power_supply_put(dwc->usb_psy);
1694
1695        return 0;
1696}
1697
1698#ifdef CONFIG_PM
1699static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1700{
1701        int ret;
1702
1703        ret = reset_control_deassert(dwc->reset);
1704        if (ret)
1705                return ret;
1706
1707        ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1708        if (ret)
1709                goto assert_reset;
1710
1711        ret = dwc3_core_init(dwc);
1712        if (ret)
1713                goto disable_clks;
1714
1715        return 0;
1716
1717disable_clks:
1718        clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1719assert_reset:
1720        reset_control_assert(dwc->reset);
1721
1722        return ret;
1723}
1724
1725static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1726{
1727        unsigned long   flags;
1728        u32 reg;
1729
1730        switch (dwc->current_dr_role) {
1731        case DWC3_GCTL_PRTCAP_DEVICE:
1732                if (pm_runtime_suspended(dwc->dev))
1733                        break;
1734                spin_lock_irqsave(&dwc->lock, flags);
1735                dwc3_gadget_suspend(dwc);
1736                spin_unlock_irqrestore(&dwc->lock, flags);
1737                synchronize_irq(dwc->irq_gadget);
1738                dwc3_core_exit(dwc);
1739                break;
1740        case DWC3_GCTL_PRTCAP_HOST:
1741                if (!PMSG_IS_AUTO(msg)) {
1742                        dwc3_core_exit(dwc);
1743                        break;
1744                }
1745
1746                /* Let controller to suspend HSPHY before PHY driver suspends */
1747                if (dwc->dis_u2_susphy_quirk ||
1748                    dwc->dis_enblslpm_quirk) {
1749                        reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1750                        reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1751                                DWC3_GUSB2PHYCFG_SUSPHY;
1752                        dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1753
1754                        /* Give some time for USB2 PHY to suspend */
1755                        usleep_range(5000, 6000);
1756                }
1757
1758                phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1759                phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1760                break;
1761        case DWC3_GCTL_PRTCAP_OTG:
1762                /* do nothing during runtime_suspend */
1763                if (PMSG_IS_AUTO(msg))
1764                        break;
1765
1766                if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1767                        spin_lock_irqsave(&dwc->lock, flags);
1768                        dwc3_gadget_suspend(dwc);
1769                        spin_unlock_irqrestore(&dwc->lock, flags);
1770                        synchronize_irq(dwc->irq_gadget);
1771                }
1772
1773                dwc3_otg_exit(dwc);
1774                dwc3_core_exit(dwc);
1775                break;
1776        default:
1777                /* do nothing */
1778                break;
1779        }
1780
1781        return 0;
1782}
1783
1784static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1785{
1786        unsigned long   flags;
1787        int             ret;
1788        u32             reg;
1789
1790        switch (dwc->current_dr_role) {
1791        case DWC3_GCTL_PRTCAP_DEVICE:
1792                ret = dwc3_core_init_for_resume(dwc);
1793                if (ret)
1794                        return ret;
1795
1796                dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1797                spin_lock_irqsave(&dwc->lock, flags);
1798                dwc3_gadget_resume(dwc);
1799                spin_unlock_irqrestore(&dwc->lock, flags);
1800                break;
1801        case DWC3_GCTL_PRTCAP_HOST:
1802                if (!PMSG_IS_AUTO(msg)) {
1803                        ret = dwc3_core_init_for_resume(dwc);
1804                        if (ret)
1805                                return ret;
1806                        dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1807                        break;
1808                }
1809                /* Restore GUSB2PHYCFG bits that were modified in suspend */
1810                reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1811                if (dwc->dis_u2_susphy_quirk)
1812                        reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1813
1814                if (dwc->dis_enblslpm_quirk)
1815                        reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1816
1817                dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1818
1819                phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1820                phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1821                break;
1822        case DWC3_GCTL_PRTCAP_OTG:
1823                /* nothing to do on runtime_resume */
1824                if (PMSG_IS_AUTO(msg))
1825                        break;
1826
1827                ret = dwc3_core_init_for_resume(dwc);
1828                if (ret)
1829                        return ret;
1830
1831                dwc3_set_prtcap(dwc, dwc->current_dr_role);
1832
1833                dwc3_otg_init(dwc);
1834                if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1835                        dwc3_otg_host_init(dwc);
1836                } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1837                        spin_lock_irqsave(&dwc->lock, flags);
1838                        dwc3_gadget_resume(dwc);
1839                        spin_unlock_irqrestore(&dwc->lock, flags);
1840                }
1841
1842                break;
1843        default:
1844                /* do nothing */
1845                break;
1846        }
1847
1848        return 0;
1849}
1850
1851static int dwc3_runtime_checks(struct dwc3 *dwc)
1852{
1853        switch (dwc->current_dr_role) {
1854        case DWC3_GCTL_PRTCAP_DEVICE:
1855                if (dwc->connected)
1856                        return -EBUSY;
1857                break;
1858        case DWC3_GCTL_PRTCAP_HOST:
1859        default:
1860                /* do nothing */
1861                break;
1862        }
1863
1864        return 0;
1865}
1866
1867static int dwc3_runtime_suspend(struct device *dev)
1868{
1869        struct dwc3     *dwc = dev_get_drvdata(dev);
1870        int             ret;
1871
1872        if (dwc3_runtime_checks(dwc))
1873                return -EBUSY;
1874
1875        ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1876        if (ret)
1877                return ret;
1878
1879        device_init_wakeup(dev, true);
1880
1881        return 0;
1882}
1883
1884static int dwc3_runtime_resume(struct device *dev)
1885{
1886        struct dwc3     *dwc = dev_get_drvdata(dev);
1887        int             ret;
1888
1889        device_init_wakeup(dev, false);
1890
1891        ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1892        if (ret)
1893                return ret;
1894
1895        switch (dwc->current_dr_role) {
1896        case DWC3_GCTL_PRTCAP_DEVICE:
1897                dwc3_gadget_process_pending_events(dwc);
1898                break;
1899        case DWC3_GCTL_PRTCAP_HOST:
1900        default:
1901                /* do nothing */
1902                break;
1903        }
1904
1905        pm_runtime_mark_last_busy(dev);
1906
1907        return 0;
1908}
1909
1910static int dwc3_runtime_idle(struct device *dev)
1911{
1912        struct dwc3     *dwc = dev_get_drvdata(dev);
1913
1914        switch (dwc->current_dr_role) {
1915        case DWC3_GCTL_PRTCAP_DEVICE:
1916                if (dwc3_runtime_checks(dwc))
1917                        return -EBUSY;
1918                break;
1919        case DWC3_GCTL_PRTCAP_HOST:
1920        default:
1921                /* do nothing */
1922                break;
1923        }
1924
1925        pm_runtime_mark_last_busy(dev);
1926        pm_runtime_autosuspend(dev);
1927
1928        return 0;
1929}
1930#endif /* CONFIG_PM */
1931
1932#ifdef CONFIG_PM_SLEEP
1933static int dwc3_suspend(struct device *dev)
1934{
1935        struct dwc3     *dwc = dev_get_drvdata(dev);
1936        int             ret;
1937
1938        ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1939        if (ret)
1940                return ret;
1941
1942        pinctrl_pm_select_sleep_state(dev);
1943
1944        return 0;
1945}
1946
1947static int dwc3_resume(struct device *dev)
1948{
1949        struct dwc3     *dwc = dev_get_drvdata(dev);
1950        int             ret;
1951
1952        pinctrl_pm_select_default_state(dev);
1953
1954        ret = dwc3_resume_common(dwc, PMSG_RESUME);
1955        if (ret)
1956                return ret;
1957
1958        pm_runtime_disable(dev);
1959        pm_runtime_set_active(dev);
1960        pm_runtime_enable(dev);
1961
1962        return 0;
1963}
1964
1965static void dwc3_complete(struct device *dev)
1966{
1967        struct dwc3     *dwc = dev_get_drvdata(dev);
1968        u32             reg;
1969
1970        if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
1971                        dwc->dis_split_quirk) {
1972                reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
1973                reg |= DWC3_GUCTL3_SPLITDISABLE;
1974                dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
1975        }
1976}
1977#else
1978#define dwc3_complete NULL
1979#endif /* CONFIG_PM_SLEEP */
1980
1981static const struct dev_pm_ops dwc3_dev_pm_ops = {
1982        SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1983        .complete = dwc3_complete,
1984        SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1985                        dwc3_runtime_idle)
1986};
1987
1988#ifdef CONFIG_OF
1989static const struct of_device_id of_dwc3_match[] = {
1990        {
1991                .compatible = "snps,dwc3"
1992        },
1993        {
1994                .compatible = "synopsys,dwc3"
1995        },
1996        { },
1997};
1998MODULE_DEVICE_TABLE(of, of_dwc3_match);
1999#endif
2000
2001#ifdef CONFIG_ACPI
2002
2003#define ACPI_ID_INTEL_BSW       "808622B7"
2004
2005static const struct acpi_device_id dwc3_acpi_match[] = {
2006        { ACPI_ID_INTEL_BSW, 0 },
2007        { },
2008};
2009MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2010#endif
2011
2012static struct platform_driver dwc3_driver = {
2013        .probe          = dwc3_probe,
2014        .remove         = dwc3_remove,
2015        .driver         = {
2016                .name   = "dwc3",
2017                .of_match_table = of_match_ptr(of_dwc3_match),
2018                .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2019                .pm     = &dwc3_dev_pm_ops,
2020        },
2021};
2022
2023module_platform_driver(dwc3_driver);
2024
2025MODULE_ALIAS("platform:dwc3");
2026MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
2027MODULE_LICENSE("GPL v2");
2028MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
2029