linux/drivers/usb/dwc2/core_intr.c
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   1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2/*
   3 * core_intr.c - DesignWare HS OTG Controller common interrupt handling
   4 *
   5 * Copyright (C) 2004-2013 Synopsys, Inc.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 * 1. Redistributions of source code must retain the above copyright
  11 *    notice, this list of conditions, and the following disclaimer,
  12 *    without modification.
  13 * 2. Redistributions in binary form must reproduce the above copyright
  14 *    notice, this list of conditions and the following disclaimer in the
  15 *    documentation and/or other materials provided with the distribution.
  16 * 3. The names of the above-listed copyright holders may not be used
  17 *    to endorse or promote products derived from this software without
  18 *    specific prior written permission.
  19 *
  20 * ALTERNATIVELY, this software may be distributed under the terms of the
  21 * GNU General Public License ("GPL") as published by the Free Software
  22 * Foundation; either version 2 of the License, or (at your option) any
  23 * later version.
  24 *
  25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36 */
  37
  38/*
  39 * This file contains the common interrupt handlers
  40 */
  41#include <linux/kernel.h>
  42#include <linux/module.h>
  43#include <linux/moduleparam.h>
  44#include <linux/spinlock.h>
  45#include <linux/interrupt.h>
  46#include <linux/dma-mapping.h>
  47#include <linux/io.h>
  48#include <linux/slab.h>
  49#include <linux/usb.h>
  50
  51#include <linux/usb/hcd.h>
  52#include <linux/usb/ch11.h>
  53
  54#include "core.h"
  55#include "hcd.h"
  56
  57static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  58{
  59        switch (hsotg->op_state) {
  60        case OTG_STATE_A_HOST:
  61                return "a_host";
  62        case OTG_STATE_A_SUSPEND:
  63                return "a_suspend";
  64        case OTG_STATE_A_PERIPHERAL:
  65                return "a_peripheral";
  66        case OTG_STATE_B_PERIPHERAL:
  67                return "b_peripheral";
  68        case OTG_STATE_B_HOST:
  69                return "b_host";
  70        default:
  71                return "unknown";
  72        }
  73}
  74
  75/**
  76 * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  77 * When the PRTINT interrupt fires, there are certain status bits in the Host
  78 * Port that needs to get cleared.
  79 *
  80 * @hsotg: Programming view of DWC_otg controller
  81 */
  82static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  83{
  84        u32 hprt0 = dwc2_readl(hsotg, HPRT0);
  85
  86        if (hprt0 & HPRT0_ENACHG) {
  87                hprt0 &= ~HPRT0_ENA;
  88                dwc2_writel(hsotg, hprt0, HPRT0);
  89        }
  90}
  91
  92/**
  93 * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  94 *
  95 * @hsotg: Programming view of DWC_otg controller
  96 */
  97static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  98{
  99        /* Clear interrupt */
 100        dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
 101
 102        dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
 103                 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 104}
 105
 106/**
 107 * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
 108 * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
 109 *
 110 * @hsotg: Programming view of DWC_otg controller
 111 */
 112static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
 113{
 114        u32 gotgint;
 115        u32 gotgctl;
 116        u32 gintmsk;
 117
 118        gotgint = dwc2_readl(hsotg, GOTGINT);
 119        gotgctl = dwc2_readl(hsotg, GOTGCTL);
 120        dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
 121                dwc2_op_state_str(hsotg));
 122
 123        if (gotgint & GOTGINT_SES_END_DET) {
 124                dev_dbg(hsotg->dev,
 125                        " ++OTG Interrupt: Session End Detected++ (%s)\n",
 126                        dwc2_op_state_str(hsotg));
 127                gotgctl = dwc2_readl(hsotg, GOTGCTL);
 128
 129                if (dwc2_is_device_mode(hsotg))
 130                        dwc2_hsotg_disconnect(hsotg);
 131
 132                if (hsotg->op_state == OTG_STATE_B_HOST) {
 133                        hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 134                } else {
 135                        /*
 136                         * If not B_HOST and Device HNP still set, HNP did
 137                         * not succeed!
 138                         */
 139                        if (gotgctl & GOTGCTL_DEVHNPEN) {
 140                                dev_dbg(hsotg->dev, "Session End Detected\n");
 141                                dev_err(hsotg->dev,
 142                                        "Device Not Connected/Responding!\n");
 143                        }
 144
 145                        /*
 146                         * If Session End Detected the B-Cable has been
 147                         * disconnected
 148                         */
 149                        /* Reset to a clean state */
 150                        hsotg->lx_state = DWC2_L0;
 151                }
 152
 153                gotgctl = dwc2_readl(hsotg, GOTGCTL);
 154                gotgctl &= ~GOTGCTL_DEVHNPEN;
 155                dwc2_writel(hsotg, gotgctl, GOTGCTL);
 156        }
 157
 158        if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
 159                dev_dbg(hsotg->dev,
 160                        " ++OTG Interrupt: Session Request Success Status Change++\n");
 161                gotgctl = dwc2_readl(hsotg, GOTGCTL);
 162                if (gotgctl & GOTGCTL_SESREQSCS) {
 163                        if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
 164                            hsotg->params.i2c_enable) {
 165                                hsotg->srp_success = 1;
 166                        } else {
 167                                /* Clear Session Request */
 168                                gotgctl = dwc2_readl(hsotg, GOTGCTL);
 169                                gotgctl &= ~GOTGCTL_SESREQ;
 170                                dwc2_writel(hsotg, gotgctl, GOTGCTL);
 171                        }
 172                }
 173        }
 174
 175        if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
 176                /*
 177                 * Print statements during the HNP interrupt handling
 178                 * can cause it to fail
 179                 */
 180                gotgctl = dwc2_readl(hsotg, GOTGCTL);
 181                /*
 182                 * WA for 3.00a- HW is not setting cur_mode, even sometimes
 183                 * this does not help
 184                 */
 185                if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
 186                        udelay(100);
 187                if (gotgctl & GOTGCTL_HSTNEGSCS) {
 188                        if (dwc2_is_host_mode(hsotg)) {
 189                                hsotg->op_state = OTG_STATE_B_HOST;
 190                                /*
 191                                 * Need to disable SOF interrupt immediately.
 192                                 * When switching from device to host, the PCD
 193                                 * interrupt handler won't handle the interrupt
 194                                 * if host mode is already set. The HCD
 195                                 * interrupt handler won't get called if the
 196                                 * HCD state is HALT. This means that the
 197                                 * interrupt does not get handled and Linux
 198                                 * complains loudly.
 199                                 */
 200                                gintmsk = dwc2_readl(hsotg, GINTMSK);
 201                                gintmsk &= ~GINTSTS_SOF;
 202                                dwc2_writel(hsotg, gintmsk, GINTMSK);
 203
 204                                /*
 205                                 * Call callback function with spin lock
 206                                 * released
 207                                 */
 208                                spin_unlock(&hsotg->lock);
 209
 210                                /* Initialize the Core for Host mode */
 211                                dwc2_hcd_start(hsotg);
 212                                spin_lock(&hsotg->lock);
 213                                hsotg->op_state = OTG_STATE_B_HOST;
 214                        }
 215                } else {
 216                        gotgctl = dwc2_readl(hsotg, GOTGCTL);
 217                        gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
 218                        dwc2_writel(hsotg, gotgctl, GOTGCTL);
 219                        dev_dbg(hsotg->dev, "HNP Failed\n");
 220                        dev_err(hsotg->dev,
 221                                "Device Not Connected/Responding\n");
 222                }
 223        }
 224
 225        if (gotgint & GOTGINT_HST_NEG_DET) {
 226                /*
 227                 * The disconnect interrupt is set at the same time as
 228                 * Host Negotiation Detected. During the mode switch all
 229                 * interrupts are cleared so the disconnect interrupt
 230                 * handler will not get executed.
 231                 */
 232                dev_dbg(hsotg->dev,
 233                        " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
 234                        (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
 235                if (dwc2_is_device_mode(hsotg)) {
 236                        dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
 237                                hsotg->op_state);
 238                        spin_unlock(&hsotg->lock);
 239                        dwc2_hcd_disconnect(hsotg, false);
 240                        spin_lock(&hsotg->lock);
 241                        hsotg->op_state = OTG_STATE_A_PERIPHERAL;
 242                } else {
 243                        /* Need to disable SOF interrupt immediately */
 244                        gintmsk = dwc2_readl(hsotg, GINTMSK);
 245                        gintmsk &= ~GINTSTS_SOF;
 246                        dwc2_writel(hsotg, gintmsk, GINTMSK);
 247                        spin_unlock(&hsotg->lock);
 248                        dwc2_hcd_start(hsotg);
 249                        spin_lock(&hsotg->lock);
 250                        hsotg->op_state = OTG_STATE_A_HOST;
 251                }
 252        }
 253
 254        if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
 255                dev_dbg(hsotg->dev,
 256                        " ++OTG Interrupt: A-Device Timeout Change++\n");
 257        if (gotgint & GOTGINT_DBNCE_DONE)
 258                dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
 259
 260        /* Clear GOTGINT */
 261        dwc2_writel(hsotg, gotgint, GOTGINT);
 262}
 263
 264/**
 265 * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
 266 * Change Interrupt
 267 *
 268 * @hsotg: Programming view of DWC_otg controller
 269 *
 270 * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
 271 * Device to Host Mode transition or a Host to Device Mode transition. This only
 272 * occurs when the cable is connected/removed from the PHY connector.
 273 */
 274static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
 275{
 276        u32 gintmsk;
 277
 278        /* Clear interrupt */
 279        dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
 280
 281        /* Need to disable SOF interrupt immediately */
 282        gintmsk = dwc2_readl(hsotg, GINTMSK);
 283        gintmsk &= ~GINTSTS_SOF;
 284        dwc2_writel(hsotg, gintmsk, GINTMSK);
 285
 286        dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++  (%s)\n",
 287                dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 288
 289        /*
 290         * Need to schedule a work, as there are possible DELAY function calls.
 291         */
 292        if (hsotg->wq_otg)
 293                queue_work(hsotg->wq_otg, &hsotg->wf_otg);
 294}
 295
 296/**
 297 * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
 298 * initiating the Session Request Protocol to request the host to turn on bus
 299 * power so a new session can begin
 300 *
 301 * @hsotg: Programming view of DWC_otg controller
 302 *
 303 * This handler responds by turning on bus power. If the DWC_otg controller is
 304 * in low power mode, this handler brings the controller out of low power mode
 305 * before turning on bus power.
 306 */
 307static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 308{
 309        int ret;
 310        u32 hprt0;
 311
 312        /* Clear interrupt */
 313        dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
 314
 315        dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
 316                hsotg->lx_state);
 317
 318        if (dwc2_is_device_mode(hsotg)) {
 319                if (hsotg->lx_state == DWC2_L2) {
 320                        if (hsotg->in_ppd) {
 321                                ret = dwc2_exit_partial_power_down(hsotg, 0,
 322                                                                   true);
 323                                if (ret)
 324                                        dev_err(hsotg->dev,
 325                                                "exit power_down failed\n");
 326                        }
 327
 328                        /* Exit gadget mode clock gating. */
 329                        if (hsotg->params.power_down ==
 330                            DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
 331                                dwc2_gadget_exit_clock_gating(hsotg, 0);
 332                }
 333
 334                /*
 335                 * Report disconnect if there is any previous session
 336                 * established
 337                 */
 338                dwc2_hsotg_disconnect(hsotg);
 339        } else {
 340                /* Turn on the port power bit. */
 341                hprt0 = dwc2_read_hprt0(hsotg);
 342                hprt0 |= HPRT0_PWR;
 343                dwc2_writel(hsotg, hprt0, HPRT0);
 344                /* Connect hcd after port power is set. */
 345                dwc2_hcd_connect(hsotg);
 346        }
 347}
 348
 349/**
 350 * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
 351 *
 352 * @hsotg: Programming view of DWC_otg controller
 353 *
 354 */
 355static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
 356{
 357        u32 glpmcfg;
 358        u32 i = 0;
 359
 360        if (hsotg->lx_state != DWC2_L1) {
 361                dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
 362                return;
 363        }
 364
 365        glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 366        if (dwc2_is_device_mode(hsotg)) {
 367                dev_dbg(hsotg->dev, "Exit from L1 state\n");
 368                glpmcfg &= ~GLPMCFG_ENBLSLPM;
 369                glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
 370                dwc2_writel(hsotg, glpmcfg, GLPMCFG);
 371
 372                do {
 373                        glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 374
 375                        if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
 376                                         GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
 377                                break;
 378
 379                        udelay(1);
 380                } while (++i < 200);
 381
 382                if (i == 200) {
 383                        dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n");
 384                        return;
 385                }
 386                dwc2_gadget_init_lpm(hsotg);
 387        } else {
 388                /* TODO */
 389                dev_err(hsotg->dev, "Host side LPM is not supported.\n");
 390                return;
 391        }
 392
 393        /* Change to L0 state */
 394        hsotg->lx_state = DWC2_L0;
 395
 396        /* Inform gadget to exit from L1 */
 397        call_gadget(hsotg, resume);
 398}
 399
 400/*
 401 * This interrupt indicates that the DWC_otg controller has detected a
 402 * resume or remote wakeup sequence. If the DWC_otg controller is in
 403 * low power mode, the handler must brings the controller out of low
 404 * power mode. The controller automatically begins resume signaling.
 405 * The handler schedules a time to stop resume signaling.
 406 */
 407static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 408{
 409        int ret;
 410
 411        /* Clear interrupt */
 412        dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
 413
 414        dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
 415        dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
 416
 417        if (hsotg->lx_state == DWC2_L1) {
 418                dwc2_wakeup_from_lpm_l1(hsotg);
 419                return;
 420        }
 421
 422        if (dwc2_is_device_mode(hsotg)) {
 423                dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
 424                        dwc2_readl(hsotg, DSTS));
 425                if (hsotg->lx_state == DWC2_L2) {
 426                        if (hsotg->in_ppd) {
 427                                u32 dctl = dwc2_readl(hsotg, DCTL);
 428                                /* Clear Remote Wakeup Signaling */
 429                                dctl &= ~DCTL_RMTWKUPSIG;
 430                                dwc2_writel(hsotg, dctl, DCTL);
 431                                ret = dwc2_exit_partial_power_down(hsotg, 1,
 432                                                                   true);
 433                                if (ret)
 434                                        dev_err(hsotg->dev,
 435                                                "exit partial_power_down failed\n");
 436                                call_gadget(hsotg, resume);
 437                        }
 438
 439                        /* Exit gadget mode clock gating. */
 440                        if (hsotg->params.power_down ==
 441                            DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
 442                                dwc2_gadget_exit_clock_gating(hsotg, 0);
 443                } else {
 444                        /* Change to L0 state */
 445                        hsotg->lx_state = DWC2_L0;
 446                }
 447        } else {
 448                if (hsotg->lx_state == DWC2_L2) {
 449                        if (hsotg->in_ppd) {
 450                                ret = dwc2_exit_partial_power_down(hsotg, 1,
 451                                                                   true);
 452                                if (ret)
 453                                        dev_err(hsotg->dev,
 454                                                "exit partial_power_down failed\n");
 455                        }
 456
 457                        if (hsotg->params.power_down ==
 458                            DWC2_POWER_DOWN_PARAM_NONE && hsotg->bus_suspended)
 459                                dwc2_host_exit_clock_gating(hsotg, 1);
 460
 461                        /*
 462                         * If we've got this quirk then the PHY is stuck upon
 463                         * wakeup.  Assert reset.  This will propagate out and
 464                         * eventually we'll re-enumerate the device.  Not great
 465                         * but the best we can do.  We can't call phy_reset()
 466                         * at interrupt time but there's no hurry, so we'll
 467                         * schedule it for later.
 468                         */
 469                        if (hsotg->reset_phy_on_wake)
 470                                dwc2_host_schedule_phy_reset(hsotg);
 471
 472                        mod_timer(&hsotg->wkp_timer,
 473                                  jiffies + msecs_to_jiffies(71));
 474                } else {
 475                        /* Change to L0 state */
 476                        hsotg->lx_state = DWC2_L0;
 477                }
 478        }
 479}
 480
 481/*
 482 * This interrupt indicates that a device has been disconnected from the
 483 * root port
 484 */
 485static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
 486{
 487        dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
 488
 489        dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
 490                dwc2_is_host_mode(hsotg) ? "Host" : "Device",
 491                dwc2_op_state_str(hsotg));
 492
 493        if (hsotg->op_state == OTG_STATE_A_HOST)
 494                dwc2_hcd_disconnect(hsotg, false);
 495}
 496
 497/*
 498 * This interrupt indicates that SUSPEND state has been detected on the USB.
 499 *
 500 * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
 501 * to "a_host".
 502 *
 503 * When power management is enabled the core will be put in low power mode.
 504 */
 505static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
 506{
 507        u32 dsts;
 508        int ret;
 509
 510        /* Clear interrupt */
 511        dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
 512
 513        dev_dbg(hsotg->dev, "USB SUSPEND\n");
 514
 515        if (dwc2_is_device_mode(hsotg)) {
 516                /*
 517                 * Check the Device status register to determine if the Suspend
 518                 * state is active
 519                 */
 520                dsts = dwc2_readl(hsotg, DSTS);
 521                dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
 522                dev_dbg(hsotg->dev,
 523                        "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
 524                        !!(dsts & DSTS_SUSPSTS),
 525                        hsotg->hw_params.power_optimized,
 526                        hsotg->hw_params.hibernation);
 527
 528                /* Ignore suspend request before enumeration */
 529                if (!dwc2_is_device_connected(hsotg)) {
 530                        dev_dbg(hsotg->dev,
 531                                "ignore suspend request before enumeration\n");
 532                        return;
 533                }
 534                if (dsts & DSTS_SUSPSTS) {
 535                        switch (hsotg->params.power_down) {
 536                        case DWC2_POWER_DOWN_PARAM_PARTIAL:
 537                                ret = dwc2_enter_partial_power_down(hsotg);
 538                                if (ret)
 539                                        dev_err(hsotg->dev,
 540                                                "enter partial_power_down failed\n");
 541
 542                                udelay(100);
 543
 544                                /* Ask phy to be suspended */
 545                                if (!IS_ERR_OR_NULL(hsotg->uphy))
 546                                        usb_phy_set_suspend(hsotg->uphy, true);
 547                                break;
 548                        case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 549                                ret = dwc2_enter_hibernation(hsotg, 0);
 550                                if (ret)
 551                                        dev_err(hsotg->dev,
 552                                                "enter hibernation failed\n");
 553                                break;
 554                        case DWC2_POWER_DOWN_PARAM_NONE:
 555                                /*
 556                                 * If neither hibernation nor partial power down are supported,
 557                                 * clock gating is used to save power.
 558                                 */
 559                                if (!hsotg->params.no_clock_gating)
 560                                        dwc2_gadget_enter_clock_gating(hsotg);
 561                        }
 562
 563                        /*
 564                         * Change to L2 (suspend) state before releasing
 565                         * spinlock
 566                         */
 567                        hsotg->lx_state = DWC2_L2;
 568
 569                        /* Call gadget suspend callback */
 570                        call_gadget(hsotg, suspend);
 571                }
 572        } else {
 573                if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
 574                        dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
 575
 576                        /* Change to L2 (suspend) state */
 577                        hsotg->lx_state = DWC2_L2;
 578                        /* Clear the a_peripheral flag, back to a_host */
 579                        spin_unlock(&hsotg->lock);
 580                        dwc2_hcd_start(hsotg);
 581                        spin_lock(&hsotg->lock);
 582                        hsotg->op_state = OTG_STATE_A_HOST;
 583                }
 584        }
 585}
 586
 587/**
 588 * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
 589 *
 590 * @hsotg: Programming view of DWC_otg controller
 591 *
 592 */
 593static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
 594{
 595        u32 glpmcfg;
 596        u32 pcgcctl;
 597        u32 hird;
 598        u32 hird_thres;
 599        u32 hird_thres_en;
 600        u32 enslpm;
 601
 602        /* Clear interrupt */
 603        dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
 604
 605        glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 606
 607        if (!(glpmcfg & GLPMCFG_LPMCAP)) {
 608                dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
 609                return;
 610        }
 611
 612        hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
 613        hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
 614                        ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
 615        hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
 616        enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
 617
 618        if (dwc2_is_device_mode(hsotg)) {
 619                dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
 620
 621                if (hird_thres_en && hird >= hird_thres) {
 622                        dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
 623                } else if (enslpm) {
 624                        dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
 625                } else {
 626                        dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
 627
 628                        pcgcctl = dwc2_readl(hsotg, PCGCTL);
 629                        pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
 630                        dwc2_writel(hsotg, pcgcctl, PCGCTL);
 631                }
 632                /**
 633                 * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
 634                 */
 635                udelay(10);
 636
 637                glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 638
 639                if (glpmcfg & GLPMCFG_SLPSTS) {
 640                        /* Save the current state */
 641                        hsotg->lx_state = DWC2_L1;
 642                        dev_dbg(hsotg->dev,
 643                                "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
 644
 645                        /* Inform gadget that we are in L1 state */
 646                        call_gadget(hsotg, suspend);
 647                }
 648        }
 649}
 650
 651#define GINTMSK_COMMON  (GINTSTS_WKUPINT | GINTSTS_SESSREQINT |         \
 652                         GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT |        \
 653                         GINTSTS_MODEMIS | GINTSTS_DISCONNINT |         \
 654                         GINTSTS_USBSUSP | GINTSTS_PRTINT |             \
 655                         GINTSTS_LPMTRANRCVD)
 656
 657/*
 658 * This function returns the Core Interrupt register
 659 */
 660static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
 661{
 662        u32 gintsts;
 663        u32 gintmsk;
 664        u32 gahbcfg;
 665        u32 gintmsk_common = GINTMSK_COMMON;
 666
 667        gintsts = dwc2_readl(hsotg, GINTSTS);
 668        gintmsk = dwc2_readl(hsotg, GINTMSK);
 669        gahbcfg = dwc2_readl(hsotg, GAHBCFG);
 670
 671        /* If any common interrupts set */
 672        if (gintsts & gintmsk_common)
 673                dev_dbg(hsotg->dev, "gintsts=%08x  gintmsk=%08x\n",
 674                        gintsts, gintmsk);
 675
 676        if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
 677                return gintsts & gintmsk & gintmsk_common;
 678        else
 679                return 0;
 680}
 681
 682/**
 683 * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect.
 684 * Exits hibernation without restoring registers.
 685 *
 686 * @hsotg: Programming view of DWC_otg controller
 687 * @gpwrdn: GPWRDN register
 688 */
 689static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
 690                                              u32 gpwrdn)
 691{
 692        u32 gpwrdn_tmp;
 693
 694        /* Switch-on voltage to the core */
 695        gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 696        gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
 697        dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 698        udelay(5);
 699
 700        /* Reset core */
 701        gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 702        gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
 703        dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 704        udelay(5);
 705
 706        /* Disable Power Down Clamp */
 707        gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 708        gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
 709        dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 710        udelay(5);
 711
 712        /* Deassert reset core */
 713        gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 714        gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
 715        dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 716        udelay(5);
 717
 718        /* Disable PMU interrupt */
 719        gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 720        gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
 721        dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 722
 723        /* De-assert Wakeup Logic */
 724        gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 725        gpwrdn_tmp &= ~GPWRDN_PMUACTV;
 726        dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 727
 728        hsotg->hibernated = 0;
 729        hsotg->bus_suspended = 0;
 730
 731        if (gpwrdn & GPWRDN_IDSTS) {
 732                hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 733                dwc2_core_init(hsotg, false);
 734                dwc2_enable_global_interrupts(hsotg);
 735                dwc2_hsotg_core_init_disconnected(hsotg, false);
 736                dwc2_hsotg_core_connect(hsotg);
 737        } else {
 738                hsotg->op_state = OTG_STATE_A_HOST;
 739
 740                /* Initialize the Core for Host mode */
 741                dwc2_core_init(hsotg, false);
 742                dwc2_enable_global_interrupts(hsotg);
 743                dwc2_hcd_start(hsotg);
 744        }
 745}
 746
 747/*
 748 * GPWRDN interrupt handler.
 749 *
 750 * The GPWRDN interrupts are those that occur in both Host and
 751 * Device mode while core is in hibernated state.
 752 */
 753static int dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
 754{
 755        u32 gpwrdn;
 756        int linestate;
 757        int ret = 0;
 758
 759        gpwrdn = dwc2_readl(hsotg, GPWRDN);
 760        /* clear all interrupt */
 761        dwc2_writel(hsotg, gpwrdn, GPWRDN);
 762        linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
 763        dev_dbg(hsotg->dev,
 764                "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
 765                gpwrdn);
 766
 767        if ((gpwrdn & GPWRDN_DISCONN_DET) &&
 768            (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
 769                dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
 770                /*
 771                 * Call disconnect detect function to exit from
 772                 * hibernation
 773                 */
 774                dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
 775        } else if ((gpwrdn & GPWRDN_LNSTSCHG) &&
 776                   (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
 777                dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
 778                if (hsotg->hw_params.hibernation &&
 779                    hsotg->hibernated) {
 780                        if (gpwrdn & GPWRDN_IDSTS) {
 781                                ret = dwc2_exit_hibernation(hsotg, 0, 0, 0);
 782                                if (ret)
 783                                        dev_err(hsotg->dev,
 784                                                "exit hibernation failed.\n");
 785                                call_gadget(hsotg, resume);
 786                        } else {
 787                                ret = dwc2_exit_hibernation(hsotg, 1, 0, 1);
 788                                if (ret)
 789                                        dev_err(hsotg->dev,
 790                                                "exit hibernation failed.\n");
 791                        }
 792                }
 793        } else if ((gpwrdn & GPWRDN_RST_DET) &&
 794                   (gpwrdn & GPWRDN_RST_DET_MSK)) {
 795                dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
 796                if (!linestate) {
 797                        ret = dwc2_exit_hibernation(hsotg, 0, 1, 0);
 798                        if (ret)
 799                                dev_err(hsotg->dev,
 800                                        "exit hibernation failed.\n");
 801                }
 802        } else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
 803                   (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
 804                dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
 805                /*
 806                 * As GPWRDN_STS_CHGINT exit from hibernation flow is
 807                 * the same as in GPWRDN_DISCONN_DET flow. Call
 808                 * disconnect detect helper function to exit from
 809                 * hibernation.
 810                 */
 811                dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
 812        }
 813
 814        return ret;
 815}
 816
 817/*
 818 * Common interrupt handler
 819 *
 820 * The common interrupts are those that occur in both Host and Device mode.
 821 * This handler handles the following interrupts:
 822 * - Mode Mismatch Interrupt
 823 * - OTG Interrupt
 824 * - Connector ID Status Change Interrupt
 825 * - Disconnect Interrupt
 826 * - Session Request Interrupt
 827 * - Resume / Remote Wakeup Detected Interrupt
 828 * - Suspend Interrupt
 829 */
 830irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
 831{
 832        struct dwc2_hsotg *hsotg = dev;
 833        u32 gintsts;
 834        irqreturn_t retval = IRQ_NONE;
 835
 836        spin_lock(&hsotg->lock);
 837
 838        if (!dwc2_is_controller_alive(hsotg)) {
 839                dev_warn(hsotg->dev, "Controller is dead\n");
 840                goto out;
 841        }
 842
 843        /* Reading current frame number value in device or host modes. */
 844        if (dwc2_is_device_mode(hsotg))
 845                hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
 846                                       & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
 847        else
 848                hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
 849                                       & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
 850
 851        gintsts = dwc2_read_common_intr(hsotg);
 852        if (gintsts & ~GINTSTS_PRTINT)
 853                retval = IRQ_HANDLED;
 854
 855        /* In case of hibernated state gintsts must not work */
 856        if (hsotg->hibernated) {
 857                dwc2_handle_gpwrdn_intr(hsotg);
 858                retval = IRQ_HANDLED;
 859                goto out;
 860        }
 861
 862        if (gintsts & GINTSTS_MODEMIS)
 863                dwc2_handle_mode_mismatch_intr(hsotg);
 864        if (gintsts & GINTSTS_OTGINT)
 865                dwc2_handle_otg_intr(hsotg);
 866        if (gintsts & GINTSTS_CONIDSTSCHNG)
 867                dwc2_handle_conn_id_status_change_intr(hsotg);
 868        if (gintsts & GINTSTS_DISCONNINT)
 869                dwc2_handle_disconnect_intr(hsotg);
 870        if (gintsts & GINTSTS_SESSREQINT)
 871                dwc2_handle_session_req_intr(hsotg);
 872        if (gintsts & GINTSTS_WKUPINT)
 873                dwc2_handle_wakeup_detected_intr(hsotg);
 874        if (gintsts & GINTSTS_USBSUSP)
 875                dwc2_handle_usb_suspend_intr(hsotg);
 876        if (gintsts & GINTSTS_LPMTRANRCVD)
 877                dwc2_handle_lpm_intr(hsotg);
 878
 879        if (gintsts & GINTSTS_PRTINT) {
 880                /*
 881                 * The port interrupt occurs while in device mode with HPRT0
 882                 * Port Enable/Disable
 883                 */
 884                if (dwc2_is_device_mode(hsotg)) {
 885                        dev_dbg(hsotg->dev,
 886                                " --Port interrupt received in Device mode--\n");
 887                        dwc2_handle_usb_port_intr(hsotg);
 888                        retval = IRQ_HANDLED;
 889                }
 890        }
 891
 892out:
 893        spin_unlock(&hsotg->lock);
 894        return retval;
 895}
 896