linux/drivers/staging/wfx/hwio.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Low-level API.
   4 *
   5 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
   6 * Copyright (c) 2010, ST-Ericsson
   7 */
   8#ifndef WFX_HWIO_H
   9#define WFX_HWIO_H
  10
  11#include <linux/types.h>
  12
  13struct wfx_dev;
  14
  15int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len);
  16int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len);
  17
  18int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
  19int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
  20
  21int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
  22int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
  23
  24int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
  25int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
  26
  27int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
  28int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
  29
  30#define CFG_ERR_SPI_FRAME          0x00000001 // only with SPI
  31#define CFG_ERR_SDIO_BUF_MISMATCH  0x00000001 // only with SDIO
  32#define CFG_ERR_BUF_UNDERRUN       0x00000002
  33#define CFG_ERR_DATA_IN_TOO_LARGE  0x00000004
  34#define CFG_ERR_HOST_NO_OUT_QUEUE  0x00000008
  35#define CFG_ERR_BUF_OVERRUN        0x00000010
  36#define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
  37#define CFG_ERR_HOST_NO_IN_QUEUE   0x00000040
  38#define CFG_ERR_HOST_CRC_MISS      0x00000080 // only with SDIO
  39#define CFG_SPI_IGNORE_CS          0x00000080 // only with SPI
  40#define CFG_BYTE_ORDER_MASK        0x00000300 // only writable with SPI
  41#define     CFG_BYTE_ORDER_BADC    0x00000000
  42#define     CFG_BYTE_ORDER_DCBA    0x00000100
  43#define     CFG_BYTE_ORDER_ABCD    0x00000200 // SDIO always use this value
  44#define CFG_DIRECT_ACCESS_MODE     0x00000400
  45#define CFG_PREFETCH_AHB           0x00000800
  46#define CFG_DISABLE_CPU_CLK        0x00001000
  47#define CFG_PREFETCH_SRAM          0x00002000
  48#define CFG_CPU_RESET              0x00004000
  49#define CFG_SDIO_DISABLE_IRQ       0x00008000 // only with SDIO
  50#define CFG_IRQ_ENABLE_DATA        0x00010000
  51#define CFG_IRQ_ENABLE_WRDY        0x00020000
  52#define CFG_CLK_RISE_EDGE          0x00040000
  53#define CFG_SDIO_DISABLE_CRC_CHK   0x00080000 // only with SDIO
  54#define CFG_RESERVED               0x00F00000
  55#define CFG_DEVICE_ID_MAJOR        0x07000000
  56#define CFG_DEVICE_ID_RESERVED     0x78000000
  57#define CFG_DEVICE_ID_TYPE         0x80000000
  58int config_reg_read(struct wfx_dev *wdev, u32 *val);
  59int config_reg_write(struct wfx_dev *wdev, u32 val);
  60int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
  61
  62#define CTRL_NEXT_LEN_MASK   0x00000FFF
  63#define CTRL_WLAN_WAKEUP     0x00001000
  64#define CTRL_WLAN_READY      0x00002000
  65int control_reg_read(struct wfx_dev *wdev, u32 *val);
  66int control_reg_write(struct wfx_dev *wdev, u32 val);
  67int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
  68
  69#define IGPR_RW          0x80000000
  70#define IGPR_INDEX       0x7F000000
  71#define IGPR_VALUE       0x00FFFFFF
  72int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
  73int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
  74
  75#endif /* WFX_HWIO_H */
  76