linux/drivers/rtc/rtc-jz4740.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   4 *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
   5 *       JZ4740 SoC RTC driver
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/io.h>
  10#include <linux/kernel.h>
  11#include <linux/module.h>
  12#include <linux/of_device.h>
  13#include <linux/platform_device.h>
  14#include <linux/pm_wakeirq.h>
  15#include <linux/reboot.h>
  16#include <linux/rtc.h>
  17#include <linux/slab.h>
  18#include <linux/spinlock.h>
  19
  20#define JZ_REG_RTC_CTRL         0x00
  21#define JZ_REG_RTC_SEC          0x04
  22#define JZ_REG_RTC_SEC_ALARM    0x08
  23#define JZ_REG_RTC_REGULATOR    0x0C
  24#define JZ_REG_RTC_HIBERNATE    0x20
  25#define JZ_REG_RTC_WAKEUP_FILTER        0x24
  26#define JZ_REG_RTC_RESET_COUNTER        0x28
  27#define JZ_REG_RTC_SCRATCHPAD   0x34
  28
  29/* The following are present on the jz4780 */
  30#define JZ_REG_RTC_WENR 0x3C
  31#define JZ_RTC_WENR_WEN BIT(31)
  32
  33#define JZ_RTC_CTRL_WRDY        BIT(7)
  34#define JZ_RTC_CTRL_1HZ         BIT(6)
  35#define JZ_RTC_CTRL_1HZ_IRQ     BIT(5)
  36#define JZ_RTC_CTRL_AF          BIT(4)
  37#define JZ_RTC_CTRL_AF_IRQ      BIT(3)
  38#define JZ_RTC_CTRL_AE          BIT(2)
  39#define JZ_RTC_CTRL_ENABLE      BIT(0)
  40
  41/* Magic value to enable writes on jz4780 */
  42#define JZ_RTC_WENR_MAGIC       0xA55A
  43
  44#define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0
  45#define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0
  46
  47enum jz4740_rtc_type {
  48        ID_JZ4740,
  49        ID_JZ4760,
  50        ID_JZ4780,
  51};
  52
  53struct jz4740_rtc {
  54        void __iomem *base;
  55        enum jz4740_rtc_type type;
  56
  57        struct rtc_device *rtc;
  58
  59        spinlock_t lock;
  60};
  61
  62static struct device *dev_for_power_off;
  63
  64static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
  65{
  66        return readl(rtc->base + reg);
  67}
  68
  69static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
  70{
  71        uint32_t ctrl;
  72        int timeout = 10000;
  73
  74        do {
  75                ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  76        } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
  77
  78        return timeout ? 0 : -EIO;
  79}
  80
  81static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
  82{
  83        uint32_t ctrl;
  84        int ret, timeout = 10000;
  85
  86        ret = jz4740_rtc_wait_write_ready(rtc);
  87        if (ret != 0)
  88                return ret;
  89
  90        writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
  91
  92        do {
  93                ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
  94        } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
  95
  96        return timeout ? 0 : -EIO;
  97}
  98
  99static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 100        uint32_t val)
 101{
 102        int ret = 0;
 103
 104        if (rtc->type >= ID_JZ4760)
 105                ret = jz4780_rtc_enable_write(rtc);
 106        if (ret == 0)
 107                ret = jz4740_rtc_wait_write_ready(rtc);
 108        if (ret == 0)
 109                writel(val, rtc->base + reg);
 110
 111        return ret;
 112}
 113
 114static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 115        bool set)
 116{
 117        int ret;
 118        unsigned long flags;
 119        uint32_t ctrl;
 120
 121        spin_lock_irqsave(&rtc->lock, flags);
 122
 123        ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 124
 125        /* Don't clear interrupt flags by accident */
 126        ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 127
 128        if (set)
 129                ctrl |= mask;
 130        else
 131                ctrl &= ~mask;
 132
 133        ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 134
 135        spin_unlock_irqrestore(&rtc->lock, flags);
 136
 137        return ret;
 138}
 139
 140static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 141{
 142        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 143        uint32_t secs, secs2;
 144        int timeout = 5;
 145
 146        if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
 147                return -EINVAL;
 148
 149        /* If the seconds register is read while it is updated, it can contain a
 150         * bogus value. This can be avoided by making sure that two consecutive
 151         * reads have the same value.
 152         */
 153        secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 154        secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 155
 156        while (secs != secs2 && --timeout) {
 157                secs = secs2;
 158                secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 159        }
 160
 161        if (timeout == 0)
 162                return -EIO;
 163
 164        rtc_time64_to_tm(secs, time);
 165
 166        return 0;
 167}
 168
 169static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
 170{
 171        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 172        int ret;
 173
 174        ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
 175        if (ret)
 176                return ret;
 177
 178        return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 179}
 180
 181static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 182{
 183        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 184        uint32_t secs;
 185        uint32_t ctrl;
 186
 187        secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 188
 189        ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 190
 191        alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 192        alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 193
 194        rtc_time64_to_tm(secs, &alrm->time);
 195
 196        return 0;
 197}
 198
 199static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 200{
 201        int ret;
 202        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 203        uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
 204
 205        ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
 206        if (!ret)
 207                ret = jz4740_rtc_ctrl_set_bits(rtc,
 208                        JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
 209
 210        return ret;
 211}
 212
 213static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 214{
 215        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 216        return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
 217}
 218
 219static const struct rtc_class_ops jz4740_rtc_ops = {
 220        .read_time      = jz4740_rtc_read_time,
 221        .set_time       = jz4740_rtc_set_time,
 222        .read_alarm     = jz4740_rtc_read_alarm,
 223        .set_alarm      = jz4740_rtc_set_alarm,
 224        .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 225};
 226
 227static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 228{
 229        struct jz4740_rtc *rtc = data;
 230        uint32_t ctrl;
 231        unsigned long events = 0;
 232
 233        ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 234
 235        if (ctrl & JZ_RTC_CTRL_1HZ)
 236                events |= (RTC_UF | RTC_IRQF);
 237
 238        if (ctrl & JZ_RTC_CTRL_AF)
 239                events |= (RTC_AF | RTC_IRQF);
 240
 241        rtc_update_irq(rtc->rtc, 1, events);
 242
 243        jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
 244
 245        return IRQ_HANDLED;
 246}
 247
 248static void jz4740_rtc_poweroff(struct device *dev)
 249{
 250        struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 251        jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 252}
 253
 254static void jz4740_rtc_power_off(void)
 255{
 256        jz4740_rtc_poweroff(dev_for_power_off);
 257        kernel_halt();
 258}
 259
 260static void jz4740_rtc_clk_disable(void *data)
 261{
 262        clk_disable_unprepare(data);
 263}
 264
 265static const struct of_device_id jz4740_rtc_of_match[] = {
 266        { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
 267        { .compatible = "ingenic,jz4760-rtc", .data = (void *)ID_JZ4760 },
 268        { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
 269        {},
 270};
 271MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
 272
 273static void jz4740_rtc_set_wakeup_params(struct jz4740_rtc *rtc,
 274                                         struct device_node *np,
 275                                         unsigned long rate)
 276{
 277        unsigned long wakeup_ticks, reset_ticks;
 278        unsigned int min_wakeup_pin_assert_time = 60; /* Default: 60ms */
 279        unsigned int reset_pin_assert_time = 100; /* Default: 100ms */
 280
 281        of_property_read_u32(np, "ingenic,reset-pin-assert-time-ms",
 282                             &reset_pin_assert_time);
 283        of_property_read_u32(np, "ingenic,min-wakeup-pin-assert-time-ms",
 284                             &min_wakeup_pin_assert_time);
 285
 286        /*
 287         * Set minimum wakeup pin assertion time: 100 ms.
 288         * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
 289         */
 290        wakeup_ticks = (min_wakeup_pin_assert_time * rate) / 1000;
 291        if (wakeup_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
 292                wakeup_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
 293        else
 294                wakeup_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
 295        jz4740_rtc_reg_write(rtc, JZ_REG_RTC_WAKEUP_FILTER, wakeup_ticks);
 296
 297        /*
 298         * Set reset pin low-level assertion time after wakeup: 60 ms.
 299         * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
 300         */
 301        reset_ticks = (reset_pin_assert_time * rate) / 1000;
 302        if (reset_ticks < JZ_RTC_RESET_COUNTER_MASK)
 303                reset_ticks &= JZ_RTC_RESET_COUNTER_MASK;
 304        else
 305                reset_ticks = JZ_RTC_RESET_COUNTER_MASK;
 306        jz4740_rtc_reg_write(rtc, JZ_REG_RTC_RESET_COUNTER, reset_ticks);
 307}
 308
 309static int jz4740_rtc_probe(struct platform_device *pdev)
 310{
 311        struct device *dev = &pdev->dev;
 312        struct device_node *np = dev->of_node;
 313        struct jz4740_rtc *rtc;
 314        unsigned long rate;
 315        struct clk *clk;
 316        int ret, irq;
 317
 318        rtc = devm_kzalloc(dev, sizeof(*rtc), GFP_KERNEL);
 319        if (!rtc)
 320                return -ENOMEM;
 321
 322        rtc->type = (enum jz4740_rtc_type)device_get_match_data(dev);
 323
 324        irq = platform_get_irq(pdev, 0);
 325        if (irq < 0)
 326                return irq;
 327
 328        rtc->base = devm_platform_ioremap_resource(pdev, 0);
 329        if (IS_ERR(rtc->base))
 330                return PTR_ERR(rtc->base);
 331
 332        clk = devm_clk_get(dev, "rtc");
 333        if (IS_ERR(clk)) {
 334                dev_err(dev, "Failed to get RTC clock\n");
 335                return PTR_ERR(clk);
 336        }
 337
 338        ret = clk_prepare_enable(clk);
 339        if (ret) {
 340                dev_err(dev, "Failed to enable clock\n");
 341                return ret;
 342        }
 343
 344        ret = devm_add_action_or_reset(dev, jz4740_rtc_clk_disable, clk);
 345        if (ret) {
 346                dev_err(dev, "Failed to register devm action\n");
 347                return ret;
 348        }
 349
 350        spin_lock_init(&rtc->lock);
 351
 352        platform_set_drvdata(pdev, rtc);
 353
 354        device_init_wakeup(dev, 1);
 355
 356        ret = dev_pm_set_wake_irq(dev, irq);
 357        if (ret) {
 358                dev_err(dev, "Failed to set wake irq: %d\n", ret);
 359                return ret;
 360        }
 361
 362        rtc->rtc = devm_rtc_allocate_device(dev);
 363        if (IS_ERR(rtc->rtc)) {
 364                ret = PTR_ERR(rtc->rtc);
 365                dev_err(dev, "Failed to allocate rtc device: %d\n", ret);
 366                return ret;
 367        }
 368
 369        rtc->rtc->ops = &jz4740_rtc_ops;
 370        rtc->rtc->range_max = U32_MAX;
 371
 372        rate = clk_get_rate(clk);
 373        jz4740_rtc_set_wakeup_params(rtc, np, rate);
 374
 375        /* Each 1 Hz pulse should happen after (rate) ticks */
 376        jz4740_rtc_reg_write(rtc, JZ_REG_RTC_REGULATOR, rate - 1);
 377
 378        ret = devm_rtc_register_device(rtc->rtc);
 379        if (ret)
 380                return ret;
 381
 382        ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,
 383                               pdev->name, rtc);
 384        if (ret) {
 385                dev_err(dev, "Failed to request rtc irq: %d\n", ret);
 386                return ret;
 387        }
 388
 389        if (of_device_is_system_power_controller(np)) {
 390                dev_for_power_off = dev;
 391
 392                if (!pm_power_off)
 393                        pm_power_off = jz4740_rtc_power_off;
 394                else
 395                        dev_warn(dev, "Poweroff handler already present!\n");
 396        }
 397
 398        return 0;
 399}
 400
 401static struct platform_driver jz4740_rtc_driver = {
 402        .probe   = jz4740_rtc_probe,
 403        .driver  = {
 404                .name  = "jz4740-rtc",
 405                .of_match_table = jz4740_rtc_of_match,
 406        },
 407};
 408
 409module_platform_driver(jz4740_rtc_driver);
 410
 411MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 412MODULE_LICENSE("GPL");
 413MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
 414MODULE_ALIAS("platform:jz4740-rtc");
 415