linux/drivers/regulator/mc13892-regulator.c
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   1// SPDX-License-Identifier: GPL-2.0
   2//
   3// Regulator Driver for Freescale MC13892 PMIC
   4//
   5// Copyright 2010 Yong Shen <yong.shen@linaro.org>
   6//
   7// Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org>
   8
   9#include <linux/mfd/mc13892.h>
  10#include <linux/regulator/machine.h>
  11#include <linux/regulator/driver.h>
  12#include <linux/platform_device.h>
  13#include <linux/kernel.h>
  14#include <linux/slab.h>
  15#include <linux/init.h>
  16#include <linux/err.h>
  17#include <linux/module.h>
  18#include "mc13xxx.h"
  19
  20#define MC13892_REVISION                        7
  21
  22#define MC13892_POWERCTL0                       13
  23#define MC13892_POWERCTL0_USEROFFSPI            3
  24#define MC13892_POWERCTL0_VCOINCELLVSEL         20
  25#define MC13892_POWERCTL0_VCOINCELLVSEL_M       (7<<20)
  26#define MC13892_POWERCTL0_VCOINCELLEN           (1<<23)
  27
  28#define MC13892_SWITCHERS0_SWxHI                (1<<23)
  29
  30#define MC13892_SWITCHERS0                      24
  31#define MC13892_SWITCHERS0_SW1VSEL              0
  32#define MC13892_SWITCHERS0_SW1VSEL_M            (0x1f<<0)
  33#define MC13892_SWITCHERS0_SW1HI                (1<<23)
  34#define MC13892_SWITCHERS0_SW1EN                0
  35
  36#define MC13892_SWITCHERS1                      25
  37#define MC13892_SWITCHERS1_SW2VSEL              0
  38#define MC13892_SWITCHERS1_SW2VSEL_M            (0x1f<<0)
  39#define MC13892_SWITCHERS1_SW2HI                (1<<23)
  40#define MC13892_SWITCHERS1_SW2EN                0
  41
  42#define MC13892_SWITCHERS2                      26
  43#define MC13892_SWITCHERS2_SW3VSEL              0
  44#define MC13892_SWITCHERS2_SW3VSEL_M            (0x1f<<0)
  45#define MC13892_SWITCHERS2_SW3HI                (1<<23)
  46#define MC13892_SWITCHERS2_SW3EN                0
  47
  48#define MC13892_SWITCHERS3                      27
  49#define MC13892_SWITCHERS3_SW4VSEL              0
  50#define MC13892_SWITCHERS3_SW4VSEL_M            (0x1f<<0)
  51#define MC13892_SWITCHERS3_SW4HI                (1<<23)
  52#define MC13892_SWITCHERS3_SW4EN                0
  53
  54#define MC13892_SWITCHERS4                      28
  55#define MC13892_SWITCHERS4_SW1MODE              0
  56#define MC13892_SWITCHERS4_SW1MODE_AUTO         (8<<0)
  57#define MC13892_SWITCHERS4_SW1MODE_M            (0xf<<0)
  58#define MC13892_SWITCHERS4_SW2MODE              10
  59#define MC13892_SWITCHERS4_SW2MODE_AUTO         (8<<10)
  60#define MC13892_SWITCHERS4_SW2MODE_M            (0xf<<10)
  61
  62#define MC13892_SWITCHERS5                      29
  63#define MC13892_SWITCHERS5_SW3MODE              0
  64#define MC13892_SWITCHERS5_SW3MODE_AUTO         (8<<0)
  65#define MC13892_SWITCHERS5_SW3MODE_M            (0xf<<0)
  66#define MC13892_SWITCHERS5_SW4MODE              8
  67#define MC13892_SWITCHERS5_SW4MODE_AUTO         (8<<8)
  68#define MC13892_SWITCHERS5_SW4MODE_M            (0xf<<8)
  69#define MC13892_SWITCHERS5_SWBSTEN              (1<<20)
  70
  71#define MC13892_REGULATORSETTING0               30
  72#define MC13892_REGULATORSETTING0_VGEN1VSEL     0
  73#define MC13892_REGULATORSETTING0_VDIGVSEL      4
  74#define MC13892_REGULATORSETTING0_VGEN2VSEL     6
  75#define MC13892_REGULATORSETTING0_VPLLVSEL      9
  76#define MC13892_REGULATORSETTING0_VUSB2VSEL     11
  77#define MC13892_REGULATORSETTING0_VGEN3VSEL     14
  78#define MC13892_REGULATORSETTING0_VCAMVSEL      16
  79
  80#define MC13892_REGULATORSETTING0_VGEN1VSEL_M   (3<<0)
  81#define MC13892_REGULATORSETTING0_VDIGVSEL_M    (3<<4)
  82#define MC13892_REGULATORSETTING0_VGEN2VSEL_M   (7<<6)
  83#define MC13892_REGULATORSETTING0_VPLLVSEL_M    (3<<9)
  84#define MC13892_REGULATORSETTING0_VUSB2VSEL_M   (3<<11)
  85#define MC13892_REGULATORSETTING0_VGEN3VSEL_M   (1<<14)
  86#define MC13892_REGULATORSETTING0_VCAMVSEL_M    (3<<16)
  87
  88#define MC13892_REGULATORSETTING1               31
  89#define MC13892_REGULATORSETTING1_VVIDEOVSEL    2
  90#define MC13892_REGULATORSETTING1_VAUDIOVSEL    4
  91#define MC13892_REGULATORSETTING1_VSDVSEL       6
  92
  93#define MC13892_REGULATORSETTING1_VVIDEOVSEL_M  (3<<2)
  94#define MC13892_REGULATORSETTING1_VAUDIOVSEL_M  (3<<4)
  95#define MC13892_REGULATORSETTING1_VSDVSEL_M     (7<<6)
  96
  97#define MC13892_REGULATORMODE0                  32
  98#define MC13892_REGULATORMODE0_VGEN1EN          (1<<0)
  99#define MC13892_REGULATORMODE0_VGEN1STDBY       (1<<1)
 100#define MC13892_REGULATORMODE0_VGEN1MODE        (1<<2)
 101#define MC13892_REGULATORMODE0_VIOHIEN          (1<<3)
 102#define MC13892_REGULATORMODE0_VIOHISTDBY       (1<<4)
 103#define MC13892_REGULATORMODE0_VIOHIMODE        (1<<5)
 104#define MC13892_REGULATORMODE0_VDIGEN           (1<<9)
 105#define MC13892_REGULATORMODE0_VDIGSTDBY        (1<<10)
 106#define MC13892_REGULATORMODE0_VDIGMODE         (1<<11)
 107#define MC13892_REGULATORMODE0_VGEN2EN          (1<<12)
 108#define MC13892_REGULATORMODE0_VGEN2STDBY       (1<<13)
 109#define MC13892_REGULATORMODE0_VGEN2MODE        (1<<14)
 110#define MC13892_REGULATORMODE0_VPLLEN           (1<<15)
 111#define MC13892_REGULATORMODE0_VPLLSTDBY        (1<<16)
 112#define MC13892_REGULATORMODE0_VPLLMODE         (1<<17)
 113#define MC13892_REGULATORMODE0_VUSB2EN          (1<<18)
 114#define MC13892_REGULATORMODE0_VUSB2STDBY       (1<<19)
 115#define MC13892_REGULATORMODE0_VUSB2MODE        (1<<20)
 116
 117#define MC13892_REGULATORMODE1                  33
 118#define MC13892_REGULATORMODE1_VGEN3EN          (1<<0)
 119#define MC13892_REGULATORMODE1_VGEN3STDBY       (1<<1)
 120#define MC13892_REGULATORMODE1_VGEN3MODE        (1<<2)
 121#define MC13892_REGULATORMODE1_VCAMEN           (1<<6)
 122#define MC13892_REGULATORMODE1_VCAMSTDBY        (1<<7)
 123#define MC13892_REGULATORMODE1_VCAMMODE         (1<<8)
 124#define MC13892_REGULATORMODE1_VCAMCONFIGEN     (1<<9)
 125#define MC13892_REGULATORMODE1_VVIDEOEN         (1<<12)
 126#define MC13892_REGULATORMODE1_VVIDEOSTDBY      (1<<13)
 127#define MC13892_REGULATORMODE1_VVIDEOMODE       (1<<14)
 128#define MC13892_REGULATORMODE1_VAUDIOEN         (1<<15)
 129#define MC13892_REGULATORMODE1_VAUDIOSTDBY      (1<<16)
 130#define MC13892_REGULATORMODE1_VAUDIOMODE       (1<<17)
 131#define MC13892_REGULATORMODE1_VSDEN            (1<<18)
 132#define MC13892_REGULATORMODE1_VSDSTDBY         (1<<19)
 133#define MC13892_REGULATORMODE1_VSDMODE          (1<<20)
 134
 135#define MC13892_POWERMISC                       34
 136#define MC13892_POWERMISC_GPO1EN                (1<<6)
 137#define MC13892_POWERMISC_GPO2EN                (1<<8)
 138#define MC13892_POWERMISC_GPO3EN                (1<<10)
 139#define MC13892_POWERMISC_GPO4EN                (1<<12)
 140#define MC13892_POWERMISC_PWGT1SPIEN            (1<<15)
 141#define MC13892_POWERMISC_PWGT2SPIEN            (1<<16)
 142#define MC13892_POWERMISC_GPO4ADINEN            (1<<21)
 143
 144#define MC13892_POWERMISC_PWGTSPI_M             (3 << 15)
 145
 146#define MC13892_USB1                            50
 147#define MC13892_USB1_VUSBEN                     (1<<3)
 148
 149static const unsigned int mc13892_vcoincell[] = {
 150        2500000, 2700000, 2800000, 2900000, 3000000, 3100000,
 151        3200000, 3300000,
 152};
 153
 154static const unsigned int mc13892_sw1[] = {
 155        600000,   625000,  650000,  675000,  700000,  725000,
 156        750000,   775000,  800000,  825000,  850000,  875000,
 157        900000,   925000,  950000,  975000, 1000000, 1025000,
 158        1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
 159        1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
 160        1350000, 1375000
 161};
 162
 163/*
 164 * Note: this table is used to derive SWxVSEL by index into
 165 * the array. Offset the values by the index of 1100000uV
 166 * to get the actual register value for that voltage selector
 167 * if the HI bit is to be set as well.
 168 */
 169#define MC13892_SWxHI_SEL_OFFSET                20
 170
 171static const unsigned int mc13892_sw[] = {
 172        600000,   625000,  650000,  675000,  700000,  725000,
 173        750000,   775000,  800000,  825000,  850000,  875000,
 174        900000,   925000,  950000,  975000, 1000000, 1025000,
 175        1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
 176        1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
 177        1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
 178        1500000, 1525000, 1550000, 1575000, 1600000, 1625000,
 179        1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
 180        1800000, 1825000, 1850000, 1875000
 181};
 182
 183static const unsigned int mc13892_swbst[] = {
 184        5000000,
 185};
 186
 187static const unsigned int mc13892_viohi[] = {
 188        2775000,
 189};
 190
 191static const unsigned int mc13892_vpll[] = {
 192        1050000, 1250000, 1650000, 1800000,
 193};
 194
 195static const unsigned int mc13892_vdig[] = {
 196        1050000, 1250000, 1650000, 1800000,
 197};
 198
 199static const unsigned int mc13892_vsd[] = {
 200        1800000, 2000000, 2600000, 2700000,
 201        2800000, 2900000, 3000000, 3150000,
 202};
 203
 204static const unsigned int mc13892_vusb2[] = {
 205        2400000, 2600000, 2700000, 2775000,
 206};
 207
 208static const unsigned int mc13892_vvideo[] = {
 209        2700000, 2775000, 2500000, 2600000,
 210};
 211
 212static const unsigned int mc13892_vaudio[] = {
 213        2300000, 2500000, 2775000, 3000000,
 214};
 215
 216static const unsigned int mc13892_vcam[] = {
 217        2500000, 2600000, 2750000, 3000000,
 218};
 219
 220static const unsigned int mc13892_vgen1[] = {
 221        1200000, 1500000, 2775000, 3150000,
 222};
 223
 224static const unsigned int mc13892_vgen2[] = {
 225        1200000, 1500000, 1600000, 1800000,
 226        2700000, 2800000, 3000000, 3150000,
 227};
 228
 229static const unsigned int mc13892_vgen3[] = {
 230        1800000, 2900000,
 231};
 232
 233static const unsigned int mc13892_vusb[] = {
 234        3300000,
 235};
 236
 237static const unsigned int mc13892_gpo[] = {
 238        2750000,
 239};
 240
 241static const unsigned int mc13892_pwgtdrv[] = {
 242        5000000,
 243};
 244
 245static const struct regulator_ops mc13892_gpo_regulator_ops;
 246static const struct regulator_ops mc13892_sw_regulator_ops;
 247
 248
 249#define MC13892_FIXED_DEFINE(name, node, reg, voltages)                 \
 250        MC13xxx_FIXED_DEFINE(MC13892_, name, node, reg, voltages,       \
 251                        mc13xxx_fixed_regulator_ops)
 252
 253#define MC13892_GPO_DEFINE(name, node, reg, voltages)                   \
 254        MC13xxx_GPO_DEFINE(MC13892_, name, node, reg, voltages,         \
 255                        mc13892_gpo_regulator_ops)
 256
 257#define MC13892_SW_DEFINE(name, node, reg, vsel_reg, voltages)          \
 258        MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages,   \
 259                        mc13892_sw_regulator_ops)
 260
 261#define MC13892_DEFINE_REGU(name, node, reg, vsel_reg, voltages)        \
 262        MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
 263                        mc13xxx_regulator_ops)
 264
 265static struct mc13xxx_regulator mc13892_regulators[] = {
 266        MC13892_DEFINE_REGU(VCOINCELL, vcoincell, POWERCTL0, POWERCTL0, mc13892_vcoincell),
 267        MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
 268        MC13892_SW_DEFINE(SW2, sw2, SWITCHERS1, SWITCHERS1, mc13892_sw),
 269        MC13892_SW_DEFINE(SW3, sw3, SWITCHERS2, SWITCHERS2, mc13892_sw),
 270        MC13892_SW_DEFINE(SW4, sw4, SWITCHERS3, SWITCHERS3, mc13892_sw),
 271        MC13892_FIXED_DEFINE(SWBST, swbst, SWITCHERS5, mc13892_swbst),
 272        MC13892_FIXED_DEFINE(VIOHI, viohi, REGULATORMODE0, mc13892_viohi),
 273        MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
 274                mc13892_vpll),
 275        MC13892_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
 276                mc13892_vdig),
 277        MC13892_DEFINE_REGU(VSD, vsd, REGULATORMODE1, REGULATORSETTING1,
 278                mc13892_vsd),
 279        MC13892_DEFINE_REGU(VUSB2, vusb2, REGULATORMODE0, REGULATORSETTING0,
 280                mc13892_vusb2),
 281        MC13892_DEFINE_REGU(VVIDEO, vvideo, REGULATORMODE1, REGULATORSETTING1,
 282                mc13892_vvideo),
 283        MC13892_DEFINE_REGU(VAUDIO, vaudio, REGULATORMODE1, REGULATORSETTING1,
 284                mc13892_vaudio),
 285        MC13892_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
 286                mc13892_vcam),
 287        MC13892_DEFINE_REGU(VGEN1, vgen1, REGULATORMODE0, REGULATORSETTING0,
 288                mc13892_vgen1),
 289        MC13892_DEFINE_REGU(VGEN2, vgen2, REGULATORMODE0, REGULATORSETTING0,
 290                mc13892_vgen2),
 291        MC13892_DEFINE_REGU(VGEN3, vgen3, REGULATORMODE1, REGULATORSETTING0,
 292                mc13892_vgen3),
 293        MC13892_FIXED_DEFINE(VUSB, vusb, USB1, mc13892_vusb),
 294        MC13892_GPO_DEFINE(GPO1, gpo1, POWERMISC, mc13892_gpo),
 295        MC13892_GPO_DEFINE(GPO2, gpo2, POWERMISC, mc13892_gpo),
 296        MC13892_GPO_DEFINE(GPO3, gpo3, POWERMISC, mc13892_gpo),
 297        MC13892_GPO_DEFINE(GPO4, gpo4, POWERMISC, mc13892_gpo),
 298        MC13892_GPO_DEFINE(PWGT1SPI, pwgt1spi, POWERMISC, mc13892_pwgtdrv),
 299        MC13892_GPO_DEFINE(PWGT2SPI, pwgt2spi, POWERMISC, mc13892_pwgtdrv),
 300};
 301
 302static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
 303                                 u32 val)
 304{
 305        struct mc13xxx *mc13892 = priv->mc13xxx;
 306        int ret;
 307        u32 valread;
 308
 309        BUG_ON(val & ~mask);
 310
 311        mc13xxx_lock(priv->mc13xxx);
 312        ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread);
 313        if (ret)
 314                goto out;
 315
 316        /* Update the stored state for Power Gates. */
 317        priv->powermisc_pwgt_state =
 318                (priv->powermisc_pwgt_state & ~mask) | val;
 319        priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M;
 320
 321        /* Construct the new register value */
 322        valread = (valread & ~mask) | val;
 323        /* Overwrite the PWGTxEN with the stored version */
 324        valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) |
 325                priv->powermisc_pwgt_state;
 326
 327        ret = mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread);
 328out:
 329        mc13xxx_unlock(priv->mc13xxx);
 330        return ret;
 331}
 332
 333static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev)
 334{
 335        struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
 336        int id = rdev_get_id(rdev);
 337        u32 en_val = mc13892_regulators[id].enable_bit;
 338        u32 mask = mc13892_regulators[id].enable_bit;
 339
 340        dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 341
 342        /* Power Gate enable value is 0 */
 343        if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
 344                en_val = 0;
 345
 346        if (id == MC13892_GPO4)
 347                mask |= MC13892_POWERMISC_GPO4ADINEN;
 348
 349        return mc13892_powermisc_rmw(priv, mask, en_val);
 350}
 351
 352static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev)
 353{
 354        struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
 355        int id = rdev_get_id(rdev);
 356        u32 dis_val = 0;
 357
 358        dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 359
 360        /* Power Gate disable value is 1 */
 361        if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
 362                dis_val = mc13892_regulators[id].enable_bit;
 363
 364        return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit,
 365                dis_val);
 366}
 367
 368static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev)
 369{
 370        struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
 371        int ret, id = rdev_get_id(rdev);
 372        unsigned int val;
 373
 374        mc13xxx_lock(priv->mc13xxx);
 375        ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
 376        mc13xxx_unlock(priv->mc13xxx);
 377
 378        if (ret)
 379                return ret;
 380
 381        /* Power Gates state is stored in powermisc_pwgt_state
 382         * where the meaning of bits is negated */
 383        val = (val & ~MC13892_POWERMISC_PWGTSPI_M) |
 384                (priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M);
 385
 386        return (val & mc13892_regulators[id].enable_bit) != 0;
 387}
 388
 389
 390static const struct regulator_ops mc13892_gpo_regulator_ops = {
 391        .enable = mc13892_gpo_regulator_enable,
 392        .disable = mc13892_gpo_regulator_disable,
 393        .is_enabled = mc13892_gpo_regulator_is_enabled,
 394        .list_voltage = regulator_list_voltage_table,
 395        .set_voltage = mc13xxx_fixed_regulator_set_voltage,
 396};
 397
 398static int mc13892_sw_regulator_get_voltage_sel(struct regulator_dev *rdev)
 399{
 400        struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
 401        int ret, id = rdev_get_id(rdev);
 402        unsigned int val, selector;
 403
 404        dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
 405
 406        mc13xxx_lock(priv->mc13xxx);
 407        ret = mc13xxx_reg_read(priv->mc13xxx,
 408                mc13892_regulators[id].vsel_reg, &val);
 409        mc13xxx_unlock(priv->mc13xxx);
 410        if (ret)
 411                return ret;
 412
 413        /*
 414         * Figure out if the HI bit is set inside the switcher mode register
 415         * since this means the selector value we return is at a different
 416         * offset into the selector table.
 417         *
 418         * According to the MC13892 documentation note 59 (Table 47) the SW1
 419         * buck switcher does not support output range programming therefore
 420         * the HI bit must always remain 0. So do not do anything strange if
 421         * our register is MC13892_SWITCHERS0.
 422         */
 423
 424        selector = val & mc13892_regulators[id].vsel_mask;
 425
 426        if ((mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) &&
 427            (val & MC13892_SWITCHERS0_SWxHI)) {
 428                selector += MC13892_SWxHI_SEL_OFFSET;
 429        }
 430
 431        dev_dbg(rdev_get_dev(rdev), "%s id: %d val: 0x%08x selector: %d\n",
 432                        __func__, id, val, selector);
 433
 434        return selector;
 435}
 436
 437static int mc13892_sw_regulator_set_voltage_sel(struct regulator_dev *rdev,
 438                                                unsigned selector)
 439{
 440        struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
 441        int volt, mask, id = rdev_get_id(rdev);
 442        u32 reg_value;
 443        int ret;
 444
 445        volt = rdev->desc->volt_table[selector];
 446        mask = mc13892_regulators[id].vsel_mask;
 447        reg_value = selector;
 448
 449        /*
 450         * Don't mess with the HI bit or support HI voltage offsets for SW1.
 451         *
 452         * Since the get_voltage_sel callback has given a fudged value for
 453         * the selector offset, we need to back out that offset if HI is
 454         * to be set so we write the correct value to the register.
 455         *
 456         * The HI bit addition and selector offset handling COULD be more
 457         * complicated by shifting and masking off the voltage selector part
 458         * of the register then logical OR it back in, but since the selector
 459         * is at bits 4:0 there is very little point. This makes the whole
 460         * thing more readable and we do far less work.
 461         */
 462
 463        if (mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) {
 464                mask |= MC13892_SWITCHERS0_SWxHI;
 465
 466                if (volt > 1375000) {
 467                        reg_value -= MC13892_SWxHI_SEL_OFFSET;
 468                        reg_value |= MC13892_SWITCHERS0_SWxHI;
 469                } else {
 470                        reg_value &= ~MC13892_SWITCHERS0_SWxHI;
 471                }
 472        }
 473
 474        mc13xxx_lock(priv->mc13xxx);
 475        ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].vsel_reg,
 476                              mask, reg_value);
 477        mc13xxx_unlock(priv->mc13xxx);
 478
 479        return ret;
 480}
 481
 482static const struct regulator_ops mc13892_sw_regulator_ops = {
 483        .list_voltage = regulator_list_voltage_table,
 484        .map_voltage = regulator_map_voltage_ascend,
 485        .set_voltage_sel = mc13892_sw_regulator_set_voltage_sel,
 486        .get_voltage_sel = mc13892_sw_regulator_get_voltage_sel,
 487};
 488
 489static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode)
 490{
 491        unsigned int en_val = 0;
 492        struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
 493        int ret, id = rdev_get_id(rdev);
 494
 495        if (mode == REGULATOR_MODE_FAST)
 496                en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN;
 497
 498        mc13xxx_lock(priv->mc13xxx);
 499        ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg,
 500                MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val);
 501        mc13xxx_unlock(priv->mc13xxx);
 502
 503        return ret;
 504}
 505
 506static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev)
 507{
 508        struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
 509        int ret, id = rdev_get_id(rdev);
 510        unsigned int val;
 511
 512        mc13xxx_lock(priv->mc13xxx);
 513        ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
 514        mc13xxx_unlock(priv->mc13xxx);
 515
 516        if (ret)
 517                return ret;
 518
 519        if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN)
 520                return REGULATOR_MODE_FAST;
 521
 522        return REGULATOR_MODE_NORMAL;
 523}
 524
 525static struct regulator_ops mc13892_vcam_ops;
 526
 527static int mc13892_regulator_probe(struct platform_device *pdev)
 528{
 529        struct mc13xxx_regulator_priv *priv;
 530        struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent);
 531        struct mc13xxx_regulator_platform_data *pdata =
 532                dev_get_platdata(&pdev->dev);
 533        struct mc13xxx_regulator_init_data *mc13xxx_data;
 534        struct regulator_config config = { };
 535        int i, ret;
 536        int num_regulators = 0;
 537        u32 val;
 538
 539        num_regulators = mc13xxx_get_num_regulators_dt(pdev);
 540
 541        if (num_regulators <= 0 && pdata)
 542                num_regulators = pdata->num_regulators;
 543        if (num_regulators <= 0)
 544                return -EINVAL;
 545
 546        priv = devm_kzalloc(&pdev->dev,
 547                            struct_size(priv, regulators, num_regulators),
 548                            GFP_KERNEL);
 549        if (!priv)
 550                return -ENOMEM;
 551
 552        priv->num_regulators = num_regulators;
 553        priv->mc13xxx_regulators = mc13892_regulators;
 554        priv->mc13xxx = mc13892;
 555        platform_set_drvdata(pdev, priv);
 556
 557        mc13xxx_lock(mc13892);
 558        ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val);
 559        if (ret)
 560                goto err_unlock;
 561
 562        /* enable switch auto mode (on 2.0A silicon only) */
 563        if ((val & 0x0000FFFF) == 0x45d0) {
 564                ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4,
 565                        MC13892_SWITCHERS4_SW1MODE_M |
 566                        MC13892_SWITCHERS4_SW2MODE_M,
 567                        MC13892_SWITCHERS4_SW1MODE_AUTO |
 568                        MC13892_SWITCHERS4_SW2MODE_AUTO);
 569                if (ret)
 570                        goto err_unlock;
 571
 572                ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5,
 573                        MC13892_SWITCHERS5_SW3MODE_M |
 574                        MC13892_SWITCHERS5_SW4MODE_M,
 575                        MC13892_SWITCHERS5_SW3MODE_AUTO |
 576                        MC13892_SWITCHERS5_SW4MODE_AUTO);
 577                if (ret)
 578                        goto err_unlock;
 579        }
 580        mc13xxx_unlock(mc13892);
 581
 582        /* update mc13892_vcam ops */
 583        memcpy(&mc13892_vcam_ops, mc13892_regulators[MC13892_VCAM].desc.ops,
 584                                                sizeof(struct regulator_ops));
 585        mc13892_vcam_ops.set_mode = mc13892_vcam_set_mode;
 586        mc13892_vcam_ops.get_mode = mc13892_vcam_get_mode;
 587        mc13892_regulators[MC13892_VCAM].desc.ops = &mc13892_vcam_ops;
 588
 589        mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators,
 590                                        ARRAY_SIZE(mc13892_regulators));
 591
 592        for (i = 0; i < priv->num_regulators; i++) {
 593                struct regulator_init_data *init_data;
 594                struct regulator_desc *desc;
 595                struct device_node *node = NULL;
 596                int id;
 597
 598                if (mc13xxx_data) {
 599                        id = mc13xxx_data[i].id;
 600                        init_data = mc13xxx_data[i].init_data;
 601                        node = mc13xxx_data[i].node;
 602                } else {
 603                        id = pdata->regulators[i].id;
 604                        init_data = pdata->regulators[i].init_data;
 605                }
 606                desc = &mc13892_regulators[id].desc;
 607
 608                config.dev = &pdev->dev;
 609                config.init_data = init_data;
 610                config.driver_data = priv;
 611                config.of_node = node;
 612
 613                priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
 614                                                              &config);
 615                if (IS_ERR(priv->regulators[i])) {
 616                        dev_err(&pdev->dev, "failed to register regulator %s\n",
 617                                mc13892_regulators[i].desc.name);
 618                        return PTR_ERR(priv->regulators[i]);
 619                }
 620        }
 621
 622        return 0;
 623
 624err_unlock:
 625        mc13xxx_unlock(mc13892);
 626        return ret;
 627}
 628
 629static struct platform_driver mc13892_regulator_driver = {
 630        .driver = {
 631                .name   = "mc13892-regulator",
 632        },
 633        .probe  = mc13892_regulator_probe,
 634};
 635
 636static int __init mc13892_regulator_init(void)
 637{
 638        return platform_driver_register(&mc13892_regulator_driver);
 639}
 640subsys_initcall(mc13892_regulator_init);
 641
 642static void __exit mc13892_regulator_exit(void)
 643{
 644        platform_driver_unregister(&mc13892_regulator_driver);
 645}
 646module_exit(mc13892_regulator_exit);
 647
 648MODULE_LICENSE("GPL v2");
 649MODULE_AUTHOR("Yong Shen <yong.shen@linaro.org>");
 650MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC");
 651MODULE_ALIAS("platform:mc13892-regulator");
 652