linux/drivers/pci/msi.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * PCI Message Signaled Interrupt (MSI)
   4 *
   5 * Copyright (C) 2003-2004 Intel
   6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   7 * Copyright (C) 2016 Christoph Hellwig.
   8 */
   9
  10#include <linux/err.h>
  11#include <linux/mm.h>
  12#include <linux/irq.h>
  13#include <linux/interrupt.h>
  14#include <linux/export.h>
  15#include <linux/ioport.h>
  16#include <linux/pci.h>
  17#include <linux/proc_fs.h>
  18#include <linux/msi.h>
  19#include <linux/smp.h>
  20#include <linux/errno.h>
  21#include <linux/io.h>
  22#include <linux/acpi_iort.h>
  23#include <linux/slab.h>
  24#include <linux/irqdomain.h>
  25#include <linux/of_irq.h>
  26
  27#include "pci.h"
  28
  29#ifdef CONFIG_PCI_MSI
  30
  31static int pci_msi_enable = 1;
  32int pci_msi_ignore_mask;
  33
  34#define msix_table_size(flags)  ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
  35
  36#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
  37static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  38{
  39        struct irq_domain *domain;
  40
  41        domain = dev_get_msi_domain(&dev->dev);
  42        if (domain && irq_domain_is_hierarchy(domain))
  43                return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
  44
  45        return arch_setup_msi_irqs(dev, nvec, type);
  46}
  47
  48static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
  49{
  50        struct irq_domain *domain;
  51
  52        domain = dev_get_msi_domain(&dev->dev);
  53        if (domain && irq_domain_is_hierarchy(domain))
  54                msi_domain_free_irqs(domain, &dev->dev);
  55        else
  56                arch_teardown_msi_irqs(dev);
  57}
  58#else
  59#define pci_msi_setup_msi_irqs          arch_setup_msi_irqs
  60#define pci_msi_teardown_msi_irqs       arch_teardown_msi_irqs
  61#endif
  62
  63#ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
  64/* Arch hooks */
  65int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
  66{
  67        return -EINVAL;
  68}
  69
  70void __weak arch_teardown_msi_irq(unsigned int irq)
  71{
  72}
  73
  74int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
  75{
  76        struct msi_desc *entry;
  77        int ret;
  78
  79        /*
  80         * If an architecture wants to support multiple MSI, it needs to
  81         * override arch_setup_msi_irqs()
  82         */
  83        if (type == PCI_CAP_ID_MSI && nvec > 1)
  84                return 1;
  85
  86        for_each_pci_msi_entry(entry, dev) {
  87                ret = arch_setup_msi_irq(dev, entry);
  88                if (ret < 0)
  89                        return ret;
  90                if (ret > 0)
  91                        return -ENOSPC;
  92        }
  93
  94        return 0;
  95}
  96
  97void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
  98{
  99        int i;
 100        struct msi_desc *entry;
 101
 102        for_each_pci_msi_entry(entry, dev)
 103                if (entry->irq)
 104                        for (i = 0; i < entry->nvec_used; i++)
 105                                arch_teardown_msi_irq(entry->irq + i);
 106}
 107#endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */
 108
 109static void default_restore_msi_irq(struct pci_dev *dev, int irq)
 110{
 111        struct msi_desc *entry;
 112
 113        entry = NULL;
 114        if (dev->msix_enabled) {
 115                for_each_pci_msi_entry(entry, dev) {
 116                        if (irq == entry->irq)
 117                                break;
 118                }
 119        } else if (dev->msi_enabled)  {
 120                entry = irq_get_msi_desc(irq);
 121        }
 122
 123        if (entry)
 124                __pci_write_msi_msg(entry, &entry->msg);
 125}
 126
 127void __weak arch_restore_msi_irqs(struct pci_dev *dev)
 128{
 129        return default_restore_msi_irqs(dev);
 130}
 131
 132static inline __attribute_const__ u32 msi_mask(unsigned x)
 133{
 134        /* Don't shift by >= width of type */
 135        if (x >= 5)
 136                return 0xffffffff;
 137        return (1 << (1 << x)) - 1;
 138}
 139
 140/*
 141 * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
 142 * mask all MSI interrupts by clearing the MSI enable bit does not work
 143 * reliably as devices without an INTx disable bit will then generate a
 144 * level IRQ which will never be cleared.
 145 */
 146void __pci_msi_desc_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 147{
 148        raw_spinlock_t *lock = &desc->dev->msi_lock;
 149        unsigned long flags;
 150
 151        if (pci_msi_ignore_mask || !desc->msi_attrib.maskbit)
 152                return;
 153
 154        raw_spin_lock_irqsave(lock, flags);
 155        desc->masked &= ~mask;
 156        desc->masked |= flag;
 157        pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
 158                               desc->masked);
 159        raw_spin_unlock_irqrestore(lock, flags);
 160}
 161
 162static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
 163{
 164        __pci_msi_desc_mask_irq(desc, mask, flag);
 165}
 166
 167static void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
 168{
 169        if (desc->msi_attrib.is_virtual)
 170                return NULL;
 171
 172        return desc->mask_base +
 173                desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
 174}
 175
 176/*
 177 * This internal function does not flush PCI writes to the device.
 178 * All users must ensure that they read from the device before either
 179 * assuming that the device state is up to date, or returning out of this
 180 * file.  This saves a few milliseconds when initialising devices with lots
 181 * of MSI-X interrupts.
 182 */
 183u32 __pci_msix_desc_mask_irq(struct msi_desc *desc, u32 flag)
 184{
 185        u32 mask_bits = desc->masked;
 186        void __iomem *desc_addr;
 187
 188        if (pci_msi_ignore_mask)
 189                return 0;
 190
 191        desc_addr = pci_msix_desc_addr(desc);
 192        if (!desc_addr)
 193                return 0;
 194
 195        mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
 196        if (flag & PCI_MSIX_ENTRY_CTRL_MASKBIT)
 197                mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 198
 199        writel(mask_bits, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 200
 201        return mask_bits;
 202}
 203
 204static void msix_mask_irq(struct msi_desc *desc, u32 flag)
 205{
 206        desc->masked = __pci_msix_desc_mask_irq(desc, flag);
 207}
 208
 209static void msi_set_mask_bit(struct irq_data *data, u32 flag)
 210{
 211        struct msi_desc *desc = irq_data_get_msi_desc(data);
 212
 213        if (desc->msi_attrib.is_msix) {
 214                msix_mask_irq(desc, flag);
 215                readl(desc->mask_base);         /* Flush write to device */
 216        } else {
 217                unsigned offset = data->irq - desc->irq;
 218                msi_mask_irq(desc, 1 << offset, flag << offset);
 219        }
 220}
 221
 222/**
 223 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
 224 * @data:       pointer to irqdata associated to that interrupt
 225 */
 226void pci_msi_mask_irq(struct irq_data *data)
 227{
 228        msi_set_mask_bit(data, 1);
 229}
 230EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
 231
 232/**
 233 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
 234 * @data:       pointer to irqdata associated to that interrupt
 235 */
 236void pci_msi_unmask_irq(struct irq_data *data)
 237{
 238        msi_set_mask_bit(data, 0);
 239}
 240EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
 241
 242void default_restore_msi_irqs(struct pci_dev *dev)
 243{
 244        struct msi_desc *entry;
 245
 246        for_each_pci_msi_entry(entry, dev)
 247                default_restore_msi_irq(dev, entry->irq);
 248}
 249
 250void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 251{
 252        struct pci_dev *dev = msi_desc_to_pci_dev(entry);
 253
 254        BUG_ON(dev->current_state != PCI_D0);
 255
 256        if (entry->msi_attrib.is_msix) {
 257                void __iomem *base = pci_msix_desc_addr(entry);
 258
 259                if (!base) {
 260                        WARN_ON(1);
 261                        return;
 262                }
 263
 264                msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
 265                msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
 266                msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
 267        } else {
 268                int pos = dev->msi_cap;
 269                u16 data;
 270
 271                pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
 272                                      &msg->address_lo);
 273                if (entry->msi_attrib.is_64) {
 274                        pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
 275                                              &msg->address_hi);
 276                        pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
 277                } else {
 278                        msg->address_hi = 0;
 279                        pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
 280                }
 281                msg->data = data;
 282        }
 283}
 284
 285void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 286{
 287        struct pci_dev *dev = msi_desc_to_pci_dev(entry);
 288
 289        if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
 290                /* Don't touch the hardware now */
 291        } else if (entry->msi_attrib.is_msix) {
 292                void __iomem *base = pci_msix_desc_addr(entry);
 293                bool unmasked = !(entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT);
 294
 295                if (!base)
 296                        goto skip;
 297
 298                /*
 299                 * The specification mandates that the entry is masked
 300                 * when the message is modified:
 301                 *
 302                 * "If software changes the Address or Data value of an
 303                 * entry while the entry is unmasked, the result is
 304                 * undefined."
 305                 */
 306                if (unmasked)
 307                        __pci_msix_desc_mask_irq(entry, PCI_MSIX_ENTRY_CTRL_MASKBIT);
 308
 309                writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
 310                writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
 311                writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
 312
 313                if (unmasked)
 314                        __pci_msix_desc_mask_irq(entry, 0);
 315
 316                /* Ensure that the writes are visible in the device */
 317                readl(base + PCI_MSIX_ENTRY_DATA);
 318        } else {
 319                int pos = dev->msi_cap;
 320                u16 msgctl;
 321
 322                pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
 323                msgctl &= ~PCI_MSI_FLAGS_QSIZE;
 324                msgctl |= entry->msi_attrib.multiple << 4;
 325                pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
 326
 327                pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
 328                                       msg->address_lo);
 329                if (entry->msi_attrib.is_64) {
 330                        pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
 331                                               msg->address_hi);
 332                        pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
 333                                              msg->data);
 334                } else {
 335                        pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
 336                                              msg->data);
 337                }
 338                /* Ensure that the writes are visible in the device */
 339                pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
 340        }
 341
 342skip:
 343        entry->msg = *msg;
 344
 345        if (entry->write_msi_msg)
 346                entry->write_msi_msg(entry, entry->write_msi_msg_data);
 347
 348}
 349
 350void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
 351{
 352        struct msi_desc *entry = irq_get_msi_desc(irq);
 353
 354        __pci_write_msi_msg(entry, msg);
 355}
 356EXPORT_SYMBOL_GPL(pci_write_msi_msg);
 357
 358static void free_msi_irqs(struct pci_dev *dev)
 359{
 360        struct list_head *msi_list = dev_to_msi_list(&dev->dev);
 361        struct msi_desc *entry, *tmp;
 362        struct attribute **msi_attrs;
 363        struct device_attribute *dev_attr;
 364        int i, count = 0;
 365
 366        for_each_pci_msi_entry(entry, dev)
 367                if (entry->irq)
 368                        for (i = 0; i < entry->nvec_used; i++)
 369                                BUG_ON(irq_has_action(entry->irq + i));
 370
 371        pci_msi_teardown_msi_irqs(dev);
 372
 373        list_for_each_entry_safe(entry, tmp, msi_list, list) {
 374                if (entry->msi_attrib.is_msix) {
 375                        if (list_is_last(&entry->list, msi_list))
 376                                iounmap(entry->mask_base);
 377                }
 378
 379                list_del(&entry->list);
 380                free_msi_entry(entry);
 381        }
 382
 383        if (dev->msi_irq_groups) {
 384                sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
 385                msi_attrs = dev->msi_irq_groups[0]->attrs;
 386                while (msi_attrs[count]) {
 387                        dev_attr = container_of(msi_attrs[count],
 388                                                struct device_attribute, attr);
 389                        kfree(dev_attr->attr.name);
 390                        kfree(dev_attr);
 391                        ++count;
 392                }
 393                kfree(msi_attrs);
 394                kfree(dev->msi_irq_groups[0]);
 395                kfree(dev->msi_irq_groups);
 396                dev->msi_irq_groups = NULL;
 397        }
 398}
 399
 400static void pci_intx_for_msi(struct pci_dev *dev, int enable)
 401{
 402        if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
 403                pci_intx(dev, enable);
 404}
 405
 406static void pci_msi_set_enable(struct pci_dev *dev, int enable)
 407{
 408        u16 control;
 409
 410        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 411        control &= ~PCI_MSI_FLAGS_ENABLE;
 412        if (enable)
 413                control |= PCI_MSI_FLAGS_ENABLE;
 414        pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 415}
 416
 417static void __pci_restore_msi_state(struct pci_dev *dev)
 418{
 419        u16 control;
 420        struct msi_desc *entry;
 421
 422        if (!dev->msi_enabled)
 423                return;
 424
 425        entry = irq_get_msi_desc(dev->irq);
 426
 427        pci_intx_for_msi(dev, 0);
 428        pci_msi_set_enable(dev, 0);
 429        arch_restore_msi_irqs(dev);
 430
 431        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 432        msi_mask_irq(entry, msi_mask(entry->msi_attrib.multi_cap),
 433                     entry->masked);
 434        control &= ~PCI_MSI_FLAGS_QSIZE;
 435        control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
 436        pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 437}
 438
 439static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
 440{
 441        u16 ctrl;
 442
 443        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
 444        ctrl &= ~clear;
 445        ctrl |= set;
 446        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
 447}
 448
 449static void __pci_restore_msix_state(struct pci_dev *dev)
 450{
 451        struct msi_desc *entry;
 452
 453        if (!dev->msix_enabled)
 454                return;
 455        BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
 456
 457        /* route the table */
 458        pci_intx_for_msi(dev, 0);
 459        pci_msix_clear_and_set_ctrl(dev, 0,
 460                                PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
 461
 462        arch_restore_msi_irqs(dev);
 463        for_each_pci_msi_entry(entry, dev)
 464                msix_mask_irq(entry, entry->masked);
 465
 466        pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
 467}
 468
 469void pci_restore_msi_state(struct pci_dev *dev)
 470{
 471        __pci_restore_msi_state(dev);
 472        __pci_restore_msix_state(dev);
 473}
 474EXPORT_SYMBOL_GPL(pci_restore_msi_state);
 475
 476static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
 477                             char *buf)
 478{
 479        struct msi_desc *entry;
 480        unsigned long irq;
 481        int retval;
 482
 483        retval = kstrtoul(attr->attr.name, 10, &irq);
 484        if (retval)
 485                return retval;
 486
 487        entry = irq_get_msi_desc(irq);
 488        if (!entry)
 489                return -ENODEV;
 490
 491        return sysfs_emit(buf, "%s\n",
 492                          entry->msi_attrib.is_msix ? "msix" : "msi");
 493}
 494
 495static int populate_msi_sysfs(struct pci_dev *pdev)
 496{
 497        struct attribute **msi_attrs;
 498        struct attribute *msi_attr;
 499        struct device_attribute *msi_dev_attr;
 500        struct attribute_group *msi_irq_group;
 501        const struct attribute_group **msi_irq_groups;
 502        struct msi_desc *entry;
 503        int ret = -ENOMEM;
 504        int num_msi = 0;
 505        int count = 0;
 506        int i;
 507
 508        /* Determine how many msi entries we have */
 509        for_each_pci_msi_entry(entry, pdev)
 510                num_msi += entry->nvec_used;
 511        if (!num_msi)
 512                return 0;
 513
 514        /* Dynamically create the MSI attributes for the PCI device */
 515        msi_attrs = kcalloc(num_msi + 1, sizeof(void *), GFP_KERNEL);
 516        if (!msi_attrs)
 517                return -ENOMEM;
 518        for_each_pci_msi_entry(entry, pdev) {
 519                for (i = 0; i < entry->nvec_used; i++) {
 520                        msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
 521                        if (!msi_dev_attr)
 522                                goto error_attrs;
 523                        msi_attrs[count] = &msi_dev_attr->attr;
 524
 525                        sysfs_attr_init(&msi_dev_attr->attr);
 526                        msi_dev_attr->attr.name = kasprintf(GFP_KERNEL, "%d",
 527                                                            entry->irq + i);
 528                        if (!msi_dev_attr->attr.name)
 529                                goto error_attrs;
 530                        msi_dev_attr->attr.mode = S_IRUGO;
 531                        msi_dev_attr->show = msi_mode_show;
 532                        ++count;
 533                }
 534        }
 535
 536        msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
 537        if (!msi_irq_group)
 538                goto error_attrs;
 539        msi_irq_group->name = "msi_irqs";
 540        msi_irq_group->attrs = msi_attrs;
 541
 542        msi_irq_groups = kcalloc(2, sizeof(void *), GFP_KERNEL);
 543        if (!msi_irq_groups)
 544                goto error_irq_group;
 545        msi_irq_groups[0] = msi_irq_group;
 546
 547        ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
 548        if (ret)
 549                goto error_irq_groups;
 550        pdev->msi_irq_groups = msi_irq_groups;
 551
 552        return 0;
 553
 554error_irq_groups:
 555        kfree(msi_irq_groups);
 556error_irq_group:
 557        kfree(msi_irq_group);
 558error_attrs:
 559        count = 0;
 560        msi_attr = msi_attrs[count];
 561        while (msi_attr) {
 562                msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
 563                kfree(msi_attr->name);
 564                kfree(msi_dev_attr);
 565                ++count;
 566                msi_attr = msi_attrs[count];
 567        }
 568        kfree(msi_attrs);
 569        return ret;
 570}
 571
 572static struct msi_desc *
 573msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
 574{
 575        struct irq_affinity_desc *masks = NULL;
 576        struct msi_desc *entry;
 577        u16 control;
 578
 579        if (affd)
 580                masks = irq_create_affinity_masks(nvec, affd);
 581
 582        /* MSI Entry Initialization */
 583        entry = alloc_msi_entry(&dev->dev, nvec, masks);
 584        if (!entry)
 585                goto out;
 586
 587        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 588
 589        entry->msi_attrib.is_msix       = 0;
 590        entry->msi_attrib.is_64         = !!(control & PCI_MSI_FLAGS_64BIT);
 591        entry->msi_attrib.is_virtual    = 0;
 592        entry->msi_attrib.entry_nr      = 0;
 593        entry->msi_attrib.maskbit       = !!(control & PCI_MSI_FLAGS_MASKBIT);
 594        entry->msi_attrib.default_irq   = dev->irq;     /* Save IOAPIC IRQ */
 595        entry->msi_attrib.multi_cap     = (control & PCI_MSI_FLAGS_QMASK) >> 1;
 596        entry->msi_attrib.multiple      = ilog2(__roundup_pow_of_two(nvec));
 597
 598        if (control & PCI_MSI_FLAGS_64BIT)
 599                entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
 600        else
 601                entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
 602
 603        /* Save the initial mask status */
 604        if (entry->msi_attrib.maskbit)
 605                pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
 606
 607out:
 608        kfree(masks);
 609        return entry;
 610}
 611
 612static int msi_verify_entries(struct pci_dev *dev)
 613{
 614        struct msi_desc *entry;
 615
 616        for_each_pci_msi_entry(entry, dev) {
 617                if (entry->msg.address_hi && dev->no_64bit_msi) {
 618                        pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
 619                                entry->msg.address_hi, entry->msg.address_lo);
 620                        return -EIO;
 621                }
 622        }
 623        return 0;
 624}
 625
 626/**
 627 * msi_capability_init - configure device's MSI capability structure
 628 * @dev: pointer to the pci_dev data structure of MSI device function
 629 * @nvec: number of interrupts to allocate
 630 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
 631 *
 632 * Setup the MSI capability structure of the device with the requested
 633 * number of interrupts.  A return value of zero indicates the successful
 634 * setup of an entry with the new MSI IRQ.  A negative return value indicates
 635 * an error, and a positive return value indicates the number of interrupts
 636 * which could have been allocated.
 637 */
 638static int msi_capability_init(struct pci_dev *dev, int nvec,
 639                               struct irq_affinity *affd)
 640{
 641        struct msi_desc *entry;
 642        int ret;
 643        unsigned mask;
 644
 645        pci_msi_set_enable(dev, 0);     /* Disable MSI during set up */
 646
 647        entry = msi_setup_entry(dev, nvec, affd);
 648        if (!entry)
 649                return -ENOMEM;
 650
 651        /* All MSIs are unmasked by default; mask them all */
 652        mask = msi_mask(entry->msi_attrib.multi_cap);
 653        msi_mask_irq(entry, mask, mask);
 654
 655        list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
 656
 657        /* Configure MSI capability structure */
 658        ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
 659        if (ret) {
 660                msi_mask_irq(entry, mask, 0);
 661                free_msi_irqs(dev);
 662                return ret;
 663        }
 664
 665        ret = msi_verify_entries(dev);
 666        if (ret) {
 667                msi_mask_irq(entry, mask, 0);
 668                free_msi_irqs(dev);
 669                return ret;
 670        }
 671
 672        ret = populate_msi_sysfs(dev);
 673        if (ret) {
 674                msi_mask_irq(entry, mask, 0);
 675                free_msi_irqs(dev);
 676                return ret;
 677        }
 678
 679        /* Set MSI enabled bits */
 680        pci_intx_for_msi(dev, 0);
 681        pci_msi_set_enable(dev, 1);
 682        dev->msi_enabled = 1;
 683
 684        pcibios_free_irq(dev);
 685        dev->irq = entry->irq;
 686        return 0;
 687}
 688
 689static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
 690{
 691        resource_size_t phys_addr;
 692        u32 table_offset;
 693        unsigned long flags;
 694        u8 bir;
 695
 696        pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
 697                              &table_offset);
 698        bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
 699        flags = pci_resource_flags(dev, bir);
 700        if (!flags || (flags & IORESOURCE_UNSET))
 701                return NULL;
 702
 703        table_offset &= PCI_MSIX_TABLE_OFFSET;
 704        phys_addr = pci_resource_start(dev, bir) + table_offset;
 705
 706        return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
 707}
 708
 709static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
 710                              struct msix_entry *entries, int nvec,
 711                              struct irq_affinity *affd)
 712{
 713        struct irq_affinity_desc *curmsk, *masks = NULL;
 714        struct msi_desc *entry;
 715        void __iomem *addr;
 716        int ret, i;
 717        int vec_count = pci_msix_vec_count(dev);
 718
 719        if (affd)
 720                masks = irq_create_affinity_masks(nvec, affd);
 721
 722        for (i = 0, curmsk = masks; i < nvec; i++) {
 723                entry = alloc_msi_entry(&dev->dev, 1, curmsk);
 724                if (!entry) {
 725                        if (!i)
 726                                iounmap(base);
 727                        else
 728                                free_msi_irqs(dev);
 729                        /* No enough memory. Don't try again */
 730                        ret = -ENOMEM;
 731                        goto out;
 732                }
 733
 734                entry->msi_attrib.is_msix       = 1;
 735                entry->msi_attrib.is_64         = 1;
 736
 737                if (entries)
 738                        entry->msi_attrib.entry_nr = entries[i].entry;
 739                else
 740                        entry->msi_attrib.entry_nr = i;
 741
 742                entry->msi_attrib.is_virtual =
 743                        entry->msi_attrib.entry_nr >= vec_count;
 744
 745                entry->msi_attrib.default_irq   = dev->irq;
 746                entry->mask_base                = base;
 747
 748                addr = pci_msix_desc_addr(entry);
 749                if (addr)
 750                        entry->masked = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
 751
 752                list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
 753                if (masks)
 754                        curmsk++;
 755        }
 756        ret = 0;
 757out:
 758        kfree(masks);
 759        return ret;
 760}
 761
 762static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
 763{
 764        struct msi_desc *entry;
 765
 766        for_each_pci_msi_entry(entry, dev) {
 767                if (entries) {
 768                        entries->vector = entry->irq;
 769                        entries++;
 770                }
 771        }
 772}
 773
 774static void msix_mask_all(void __iomem *base, int tsize)
 775{
 776        u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
 777        int i;
 778
 779        if (pci_msi_ignore_mask)
 780                return;
 781
 782        for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
 783                writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
 784}
 785
 786/**
 787 * msix_capability_init - configure device's MSI-X capability
 788 * @dev: pointer to the pci_dev data structure of MSI-X device function
 789 * @entries: pointer to an array of struct msix_entry entries
 790 * @nvec: number of @entries
 791 * @affd: Optional pointer to enable automatic affinity assignment
 792 *
 793 * Setup the MSI-X capability structure of device function with a
 794 * single MSI-X IRQ. A return of zero indicates the successful setup of
 795 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
 796 **/
 797static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
 798                                int nvec, struct irq_affinity *affd)
 799{
 800        void __iomem *base;
 801        int ret, tsize;
 802        u16 control;
 803
 804        /*
 805         * Some devices require MSI-X to be enabled before the MSI-X
 806         * registers can be accessed.  Mask all the vectors to prevent
 807         * interrupts coming in before they're fully set up.
 808         */
 809        pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
 810                                    PCI_MSIX_FLAGS_ENABLE);
 811
 812        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
 813        /* Request & Map MSI-X table region */
 814        tsize = msix_table_size(control);
 815        base = msix_map_region(dev, tsize);
 816        if (!base) {
 817                ret = -ENOMEM;
 818                goto out_disable;
 819        }
 820
 821        /* Ensure that all table entries are masked. */
 822        msix_mask_all(base, tsize);
 823
 824        ret = msix_setup_entries(dev, base, entries, nvec, affd);
 825        if (ret)
 826                goto out_disable;
 827
 828        ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
 829        if (ret)
 830                goto out_avail;
 831
 832        /* Check if all MSI entries honor device restrictions */
 833        ret = msi_verify_entries(dev);
 834        if (ret)
 835                goto out_free;
 836
 837        msix_update_entries(dev, entries);
 838
 839        ret = populate_msi_sysfs(dev);
 840        if (ret)
 841                goto out_free;
 842
 843        /* Set MSI-X enabled bits and unmask the function */
 844        pci_intx_for_msi(dev, 0);
 845        dev->msix_enabled = 1;
 846        pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
 847
 848        pcibios_free_irq(dev);
 849        return 0;
 850
 851out_avail:
 852        if (ret < 0) {
 853                /*
 854                 * If we had some success, report the number of IRQs
 855                 * we succeeded in setting up.
 856                 */
 857                struct msi_desc *entry;
 858                int avail = 0;
 859
 860                for_each_pci_msi_entry(entry, dev) {
 861                        if (entry->irq != 0)
 862                                avail++;
 863                }
 864                if (avail != 0)
 865                        ret = avail;
 866        }
 867
 868out_free:
 869        free_msi_irqs(dev);
 870
 871out_disable:
 872        pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
 873
 874        return ret;
 875}
 876
 877/**
 878 * pci_msi_supported - check whether MSI may be enabled on a device
 879 * @dev: pointer to the pci_dev data structure of MSI device function
 880 * @nvec: how many MSIs have been requested?
 881 *
 882 * Look at global flags, the device itself, and its parent buses
 883 * to determine if MSI/-X are supported for the device. If MSI/-X is
 884 * supported return 1, else return 0.
 885 **/
 886static int pci_msi_supported(struct pci_dev *dev, int nvec)
 887{
 888        struct pci_bus *bus;
 889
 890        /* MSI must be globally enabled and supported by the device */
 891        if (!pci_msi_enable)
 892                return 0;
 893
 894        if (!dev || dev->no_msi)
 895                return 0;
 896
 897        /*
 898         * You can't ask to have 0 or less MSIs configured.
 899         *  a) it's stupid ..
 900         *  b) the list manipulation code assumes nvec >= 1.
 901         */
 902        if (nvec < 1)
 903                return 0;
 904
 905        /*
 906         * Any bridge which does NOT route MSI transactions from its
 907         * secondary bus to its primary bus must set NO_MSI flag on
 908         * the secondary pci_bus.
 909         *
 910         * The NO_MSI flag can either be set directly by:
 911         * - arch-specific PCI host bus controller drivers (deprecated)
 912         * - quirks for specific PCI bridges
 913         *
 914         * or indirectly by platform-specific PCI host bridge drivers by
 915         * advertising the 'msi_domain' property, which results in
 916         * the NO_MSI flag when no MSI domain is found for this bridge
 917         * at probe time.
 918         */
 919        for (bus = dev->bus; bus; bus = bus->parent)
 920                if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
 921                        return 0;
 922
 923        return 1;
 924}
 925
 926/**
 927 * pci_msi_vec_count - Return the number of MSI vectors a device can send
 928 * @dev: device to report about
 929 *
 930 * This function returns the number of MSI vectors a device requested via
 931 * Multiple Message Capable register. It returns a negative errno if the
 932 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
 933 * and returns a power of two, up to a maximum of 2^5 (32), according to the
 934 * MSI specification.
 935 **/
 936int pci_msi_vec_count(struct pci_dev *dev)
 937{
 938        int ret;
 939        u16 msgctl;
 940
 941        if (!dev->msi_cap)
 942                return -EINVAL;
 943
 944        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
 945        ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
 946
 947        return ret;
 948}
 949EXPORT_SYMBOL(pci_msi_vec_count);
 950
 951static void pci_msi_shutdown(struct pci_dev *dev)
 952{
 953        struct msi_desc *desc;
 954        u32 mask;
 955
 956        if (!pci_msi_enable || !dev || !dev->msi_enabled)
 957                return;
 958
 959        BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
 960        desc = first_pci_msi_entry(dev);
 961
 962        pci_msi_set_enable(dev, 0);
 963        pci_intx_for_msi(dev, 1);
 964        dev->msi_enabled = 0;
 965
 966        /* Return the device with MSI unmasked as initial states */
 967        mask = msi_mask(desc->msi_attrib.multi_cap);
 968        msi_mask_irq(desc, mask, 0);
 969
 970        /* Restore dev->irq to its default pin-assertion IRQ */
 971        dev->irq = desc->msi_attrib.default_irq;
 972        pcibios_alloc_irq(dev);
 973}
 974
 975void pci_disable_msi(struct pci_dev *dev)
 976{
 977        if (!pci_msi_enable || !dev || !dev->msi_enabled)
 978                return;
 979
 980        pci_msi_shutdown(dev);
 981        free_msi_irqs(dev);
 982}
 983EXPORT_SYMBOL(pci_disable_msi);
 984
 985/**
 986 * pci_msix_vec_count - return the number of device's MSI-X table entries
 987 * @dev: pointer to the pci_dev data structure of MSI-X device function
 988 * This function returns the number of device's MSI-X table entries and
 989 * therefore the number of MSI-X vectors device is capable of sending.
 990 * It returns a negative errno if the device is not capable of sending MSI-X
 991 * interrupts.
 992 **/
 993int pci_msix_vec_count(struct pci_dev *dev)
 994{
 995        u16 control;
 996
 997        if (!dev->msix_cap)
 998                return -EINVAL;
 999
1000        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
1001        return msix_table_size(control);
1002}
1003EXPORT_SYMBOL(pci_msix_vec_count);
1004
1005static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
1006                             int nvec, struct irq_affinity *affd, int flags)
1007{
1008        int nr_entries;
1009        int i, j;
1010
1011        if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
1012                return -EINVAL;
1013
1014        nr_entries = pci_msix_vec_count(dev);
1015        if (nr_entries < 0)
1016                return nr_entries;
1017        if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
1018                return nr_entries;
1019
1020        if (entries) {
1021                /* Check for any invalid entries */
1022                for (i = 0; i < nvec; i++) {
1023                        if (entries[i].entry >= nr_entries)
1024                                return -EINVAL;         /* invalid entry */
1025                        for (j = i + 1; j < nvec; j++) {
1026                                if (entries[i].entry == entries[j].entry)
1027                                        return -EINVAL; /* duplicate entry */
1028                        }
1029                }
1030        }
1031
1032        /* Check whether driver already requested for MSI IRQ */
1033        if (dev->msi_enabled) {
1034                pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
1035                return -EINVAL;
1036        }
1037        return msix_capability_init(dev, entries, nvec, affd);
1038}
1039
1040static void pci_msix_shutdown(struct pci_dev *dev)
1041{
1042        struct msi_desc *entry;
1043
1044        if (!pci_msi_enable || !dev || !dev->msix_enabled)
1045                return;
1046
1047        if (pci_dev_is_disconnected(dev)) {
1048                dev->msix_enabled = 0;
1049                return;
1050        }
1051
1052        /* Return the device with MSI-X masked as initial states */
1053        for_each_pci_msi_entry(entry, dev)
1054                __pci_msix_desc_mask_irq(entry, 1);
1055
1056        pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1057        pci_intx_for_msi(dev, 1);
1058        dev->msix_enabled = 0;
1059        pcibios_alloc_irq(dev);
1060}
1061
1062void pci_disable_msix(struct pci_dev *dev)
1063{
1064        if (!pci_msi_enable || !dev || !dev->msix_enabled)
1065                return;
1066
1067        pci_msix_shutdown(dev);
1068        free_msi_irqs(dev);
1069}
1070EXPORT_SYMBOL(pci_disable_msix);
1071
1072void pci_no_msi(void)
1073{
1074        pci_msi_enable = 0;
1075}
1076
1077/**
1078 * pci_msi_enabled - is MSI enabled?
1079 *
1080 * Returns true if MSI has not been disabled by the command-line option
1081 * pci=nomsi.
1082 **/
1083int pci_msi_enabled(void)
1084{
1085        return pci_msi_enable;
1086}
1087EXPORT_SYMBOL(pci_msi_enabled);
1088
1089static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1090                                  struct irq_affinity *affd)
1091{
1092        int nvec;
1093        int rc;
1094
1095        if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
1096                return -EINVAL;
1097
1098        /* Check whether driver already requested MSI-X IRQs */
1099        if (dev->msix_enabled) {
1100                pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
1101                return -EINVAL;
1102        }
1103
1104        if (maxvec < minvec)
1105                return -ERANGE;
1106
1107        if (WARN_ON_ONCE(dev->msi_enabled))
1108                return -EINVAL;
1109
1110        nvec = pci_msi_vec_count(dev);
1111        if (nvec < 0)
1112                return nvec;
1113        if (nvec < minvec)
1114                return -ENOSPC;
1115
1116        if (nvec > maxvec)
1117                nvec = maxvec;
1118
1119        for (;;) {
1120                if (affd) {
1121                        nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1122                        if (nvec < minvec)
1123                                return -ENOSPC;
1124                }
1125
1126                rc = msi_capability_init(dev, nvec, affd);
1127                if (rc == 0)
1128                        return nvec;
1129
1130                if (rc < 0)
1131                        return rc;
1132                if (rc < minvec)
1133                        return -ENOSPC;
1134
1135                nvec = rc;
1136        }
1137}
1138
1139/* deprecated, don't use */
1140int pci_enable_msi(struct pci_dev *dev)
1141{
1142        int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1143        if (rc < 0)
1144                return rc;
1145        return 0;
1146}
1147EXPORT_SYMBOL(pci_enable_msi);
1148
1149static int __pci_enable_msix_range(struct pci_dev *dev,
1150                                   struct msix_entry *entries, int minvec,
1151                                   int maxvec, struct irq_affinity *affd,
1152                                   int flags)
1153{
1154        int rc, nvec = maxvec;
1155
1156        if (maxvec < minvec)
1157                return -ERANGE;
1158
1159        if (WARN_ON_ONCE(dev->msix_enabled))
1160                return -EINVAL;
1161
1162        for (;;) {
1163                if (affd) {
1164                        nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1165                        if (nvec < minvec)
1166                                return -ENOSPC;
1167                }
1168
1169                rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
1170                if (rc == 0)
1171                        return nvec;
1172
1173                if (rc < 0)
1174                        return rc;
1175                if (rc < minvec)
1176                        return -ENOSPC;
1177
1178                nvec = rc;
1179        }
1180}
1181
1182/**
1183 * pci_enable_msix_range - configure device's MSI-X capability structure
1184 * @dev: pointer to the pci_dev data structure of MSI-X device function
1185 * @entries: pointer to an array of MSI-X entries
1186 * @minvec: minimum number of MSI-X IRQs requested
1187 * @maxvec: maximum number of MSI-X IRQs requested
1188 *
1189 * Setup the MSI-X capability structure of device function with a maximum
1190 * possible number of interrupts in the range between @minvec and @maxvec
1191 * upon its software driver call to request for MSI-X mode enabled on its
1192 * hardware device function. It returns a negative errno if an error occurs.
1193 * If it succeeds, it returns the actual number of interrupts allocated and
1194 * indicates the successful configuration of MSI-X capability structure
1195 * with new allocated MSI-X interrupts.
1196 **/
1197int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1198                int minvec, int maxvec)
1199{
1200        return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
1201}
1202EXPORT_SYMBOL(pci_enable_msix_range);
1203
1204/**
1205 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1206 * @dev:                PCI device to operate on
1207 * @min_vecs:           minimum number of vectors required (must be >= 1)
1208 * @max_vecs:           maximum (desired) number of vectors
1209 * @flags:              flags or quirks for the allocation
1210 * @affd:               optional description of the affinity requirements
1211 *
1212 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1213 * vectors if available, and fall back to a single legacy vector
1214 * if neither is available.  Return the number of vectors allocated,
1215 * (which might be smaller than @max_vecs) if successful, or a negative
1216 * error code on error. If less than @min_vecs interrupt vectors are
1217 * available for @dev the function will fail with -ENOSPC.
1218 *
1219 * To get the Linux IRQ number used for a vector that can be passed to
1220 * request_irq() use the pci_irq_vector() helper.
1221 */
1222int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1223                                   unsigned int max_vecs, unsigned int flags,
1224                                   struct irq_affinity *affd)
1225{
1226        struct irq_affinity msi_default_affd = {0};
1227        int nvecs = -ENOSPC;
1228
1229        if (flags & PCI_IRQ_AFFINITY) {
1230                if (!affd)
1231                        affd = &msi_default_affd;
1232        } else {
1233                if (WARN_ON(affd))
1234                        affd = NULL;
1235        }
1236
1237        if (flags & PCI_IRQ_MSIX) {
1238                nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1239                                                affd, flags);
1240                if (nvecs > 0)
1241                        return nvecs;
1242        }
1243
1244        if (flags & PCI_IRQ_MSI) {
1245                nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1246                if (nvecs > 0)
1247                        return nvecs;
1248        }
1249
1250        /* use legacy IRQ if allowed */
1251        if (flags & PCI_IRQ_LEGACY) {
1252                if (min_vecs == 1 && dev->irq) {
1253                        /*
1254                         * Invoke the affinity spreading logic to ensure that
1255                         * the device driver can adjust queue configuration
1256                         * for the single interrupt case.
1257                         */
1258                        if (affd)
1259                                irq_create_affinity_masks(1, affd);
1260                        pci_intx(dev, 1);
1261                        return 1;
1262                }
1263        }
1264
1265        return nvecs;
1266}
1267EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1268
1269/**
1270 * pci_free_irq_vectors - free previously allocated IRQs for a device
1271 * @dev:                PCI device to operate on
1272 *
1273 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1274 */
1275void pci_free_irq_vectors(struct pci_dev *dev)
1276{
1277        pci_disable_msix(dev);
1278        pci_disable_msi(dev);
1279}
1280EXPORT_SYMBOL(pci_free_irq_vectors);
1281
1282/**
1283 * pci_irq_vector - return Linux IRQ number of a device vector
1284 * @dev: PCI device to operate on
1285 * @nr: device-relative interrupt vector index (0-based).
1286 */
1287int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1288{
1289        if (dev->msix_enabled) {
1290                struct msi_desc *entry;
1291                int i = 0;
1292
1293                for_each_pci_msi_entry(entry, dev) {
1294                        if (i == nr)
1295                                return entry->irq;
1296                        i++;
1297                }
1298                WARN_ON_ONCE(1);
1299                return -EINVAL;
1300        }
1301
1302        if (dev->msi_enabled) {
1303                struct msi_desc *entry = first_pci_msi_entry(dev);
1304
1305                if (WARN_ON_ONCE(nr >= entry->nvec_used))
1306                        return -EINVAL;
1307        } else {
1308                if (WARN_ON_ONCE(nr > 0))
1309                        return -EINVAL;
1310        }
1311
1312        return dev->irq + nr;
1313}
1314EXPORT_SYMBOL(pci_irq_vector);
1315
1316/**
1317 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1318 * @dev:        PCI device to operate on
1319 * @nr:         device-relative interrupt vector index (0-based).
1320 */
1321const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1322{
1323        if (dev->msix_enabled) {
1324                struct msi_desc *entry;
1325                int i = 0;
1326
1327                for_each_pci_msi_entry(entry, dev) {
1328                        if (i == nr)
1329                                return &entry->affinity->mask;
1330                        i++;
1331                }
1332                WARN_ON_ONCE(1);
1333                return NULL;
1334        } else if (dev->msi_enabled) {
1335                struct msi_desc *entry = first_pci_msi_entry(dev);
1336
1337                if (WARN_ON_ONCE(!entry || !entry->affinity ||
1338                                 nr >= entry->nvec_used))
1339                        return NULL;
1340
1341                return &entry->affinity[nr].mask;
1342        } else {
1343                return cpu_possible_mask;
1344        }
1345}
1346EXPORT_SYMBOL(pci_irq_get_affinity);
1347
1348struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1349{
1350        return to_pci_dev(desc->dev);
1351}
1352EXPORT_SYMBOL(msi_desc_to_pci_dev);
1353
1354void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1355{
1356        struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1357
1358        return dev->bus->sysdata;
1359}
1360EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1361
1362#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1363/**
1364 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1365 * @irq_data:   Pointer to interrupt data of the MSI interrupt
1366 * @msg:        Pointer to the message
1367 */
1368void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1369{
1370        struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1371
1372        /*
1373         * For MSI-X desc->irq is always equal to irq_data->irq. For
1374         * MSI only the first interrupt of MULTI MSI passes the test.
1375         */
1376        if (desc->irq == irq_data->irq)
1377                __pci_write_msi_msg(desc, msg);
1378}
1379
1380/**
1381 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1382 * @desc:       Pointer to the MSI descriptor
1383 *
1384 * The ID number is only used within the irqdomain.
1385 */
1386static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc)
1387{
1388        struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1389
1390        return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1391                pci_dev_id(dev) << 11 |
1392                (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1393}
1394
1395static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1396{
1397        return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1398}
1399
1400/**
1401 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1402 *                            for @dev
1403 * @domain:     The interrupt domain to check
1404 * @info:       The domain info for verification
1405 * @dev:        The device to check
1406 *
1407 * Returns:
1408 *  0 if the functionality is supported
1409 *  1 if Multi MSI is requested, but the domain does not support it
1410 *  -ENOTSUPP otherwise
1411 */
1412int pci_msi_domain_check_cap(struct irq_domain *domain,
1413                             struct msi_domain_info *info, struct device *dev)
1414{
1415        struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1416
1417        /* Special handling to support __pci_enable_msi_range() */
1418        if (pci_msi_desc_is_multi_msi(desc) &&
1419            !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1420                return 1;
1421        else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1422                return -ENOTSUPP;
1423
1424        return 0;
1425}
1426
1427static int pci_msi_domain_handle_error(struct irq_domain *domain,
1428                                       struct msi_desc *desc, int error)
1429{
1430        /* Special handling to support __pci_enable_msi_range() */
1431        if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1432                return 1;
1433
1434        return error;
1435}
1436
1437static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1438                                    struct msi_desc *desc)
1439{
1440        arg->desc = desc;
1441        arg->hwirq = pci_msi_domain_calc_hwirq(desc);
1442}
1443
1444static struct msi_domain_ops pci_msi_domain_ops_default = {
1445        .set_desc       = pci_msi_domain_set_desc,
1446        .msi_check      = pci_msi_domain_check_cap,
1447        .handle_error   = pci_msi_domain_handle_error,
1448};
1449
1450static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1451{
1452        struct msi_domain_ops *ops = info->ops;
1453
1454        if (ops == NULL) {
1455                info->ops = &pci_msi_domain_ops_default;
1456        } else {
1457                if (ops->set_desc == NULL)
1458                        ops->set_desc = pci_msi_domain_set_desc;
1459                if (ops->msi_check == NULL)
1460                        ops->msi_check = pci_msi_domain_check_cap;
1461                if (ops->handle_error == NULL)
1462                        ops->handle_error = pci_msi_domain_handle_error;
1463        }
1464}
1465
1466static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1467{
1468        struct irq_chip *chip = info->chip;
1469
1470        BUG_ON(!chip);
1471        if (!chip->irq_write_msi_msg)
1472                chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1473        if (!chip->irq_mask)
1474                chip->irq_mask = pci_msi_mask_irq;
1475        if (!chip->irq_unmask)
1476                chip->irq_unmask = pci_msi_unmask_irq;
1477}
1478
1479/**
1480 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1481 * @fwnode:     Optional fwnode of the interrupt controller
1482 * @info:       MSI domain info
1483 * @parent:     Parent irq domain
1484 *
1485 * Updates the domain and chip ops and creates a MSI interrupt domain.
1486 *
1487 * Returns:
1488 * A domain pointer or NULL in case of failure.
1489 */
1490struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1491                                             struct msi_domain_info *info,
1492                                             struct irq_domain *parent)
1493{
1494        struct irq_domain *domain;
1495
1496        if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
1497                info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
1498
1499        if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1500                pci_msi_domain_update_dom_ops(info);
1501        if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1502                pci_msi_domain_update_chip_ops(info);
1503
1504        info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1505        if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
1506                info->flags |= MSI_FLAG_MUST_REACTIVATE;
1507
1508        /* PCI-MSI is oneshot-safe */
1509        info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
1510
1511        domain = msi_create_irq_domain(fwnode, info, parent);
1512        if (!domain)
1513                return NULL;
1514
1515        irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1516        return domain;
1517}
1518EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1519
1520/*
1521 * Users of the generic MSI infrastructure expect a device to have a single ID,
1522 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1523 * DMA phantom functions tend to still emit MSIs from the real function number,
1524 * so we ignore those and only consider topological aliases where either the
1525 * alias device or RID appears on a different bus number. We also make the
1526 * reasonable assumption that bridges are walked in an upstream direction (so
1527 * the last one seen wins), and the much braver assumption that the most likely
1528 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1529 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1530 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1531 * for taking ownership all we can really do is close our eyes and hope...
1532 */
1533static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1534{
1535        u32 *pa = data;
1536        u8 bus = PCI_BUS_NUM(*pa);
1537
1538        if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1539                *pa = alias;
1540
1541        return 0;
1542}
1543
1544/**
1545 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1546 * @domain:     The interrupt domain
1547 * @pdev:       The PCI device.
1548 *
1549 * The RID for a device is formed from the alias, with a firmware
1550 * supplied mapping applied
1551 *
1552 * Returns: The RID.
1553 */
1554u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1555{
1556        struct device_node *of_node;
1557        u32 rid = pci_dev_id(pdev);
1558
1559        pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1560
1561        of_node = irq_domain_get_of_node(domain);
1562        rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) :
1563                        iort_msi_map_id(&pdev->dev, rid);
1564
1565        return rid;
1566}
1567
1568/**
1569 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1570 * @pdev:       The PCI device
1571 *
1572 * Use the firmware data to find a device-specific MSI domain
1573 * (i.e. not one that is set as a default).
1574 *
1575 * Returns: The corresponding MSI domain or NULL if none has been found.
1576 */
1577struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1578{
1579        struct irq_domain *dom;
1580        u32 rid = pci_dev_id(pdev);
1581
1582        pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1583        dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI);
1584        if (!dom)
1585                dom = iort_get_device_domain(&pdev->dev, rid,
1586                                             DOMAIN_BUS_PCI_MSI);
1587        return dom;
1588}
1589
1590/**
1591 * pci_dev_has_special_msi_domain - Check whether the device is handled by
1592 *                                  a non-standard PCI-MSI domain
1593 * @pdev:       The PCI device to check.
1594 *
1595 * Returns: True if the device irqdomain or the bus irqdomain is
1596 * non-standard PCI/MSI.
1597 */
1598bool pci_dev_has_special_msi_domain(struct pci_dev *pdev)
1599{
1600        struct irq_domain *dom = dev_get_msi_domain(&pdev->dev);
1601
1602        if (!dom)
1603                dom = dev_get_msi_domain(&pdev->bus->dev);
1604
1605        if (!dom)
1606                return true;
1607
1608        return dom->bus_token != DOMAIN_BUS_PCI_MSI;
1609}
1610
1611#endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1612#endif /* CONFIG_PCI_MSI */
1613
1614void pci_msi_init(struct pci_dev *dev)
1615{
1616        u16 ctrl;
1617
1618        /*
1619         * Disable the MSI hardware to avoid screaming interrupts
1620         * during boot.  This is the power on reset default so
1621         * usually this should be a noop.
1622         */
1623        dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1624        if (!dev->msi_cap)
1625                return;
1626
1627        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
1628        if (ctrl & PCI_MSI_FLAGS_ENABLE)
1629                pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS,
1630                                      ctrl & ~PCI_MSI_FLAGS_ENABLE);
1631
1632        if (!(ctrl & PCI_MSI_FLAGS_64BIT))
1633                dev->no_64bit_msi = 1;
1634}
1635
1636void pci_msix_init(struct pci_dev *dev)
1637{
1638        u16 ctrl;
1639
1640        dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1641        if (!dev->msix_cap)
1642                return;
1643
1644        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
1645        if (ctrl & PCI_MSIX_FLAGS_ENABLE)
1646                pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS,
1647                                      ctrl & ~PCI_MSIX_FLAGS_ENABLE);
1648}
1649