linux/drivers/mtd/nand/raw/cs553x_nand.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * (C) 2005, 2006 Red Hat Inc.
   4 *
   5 * Author: David Woodhouse <dwmw2@infradead.org>
   6 *         Tom Sylla <tom.sylla@amd.com>
   7 *
   8 *  Overview:
   9 *   This is a device driver for the NAND flash controller found on
  10 *   the AMD CS5535/CS5536 companion chipsets for the Geode processor.
  11 *   mtd-id for command line partitioning is cs553x_nand_cs[0-3]
  12 *   where 0-3 reflects the chip select for NAND.
  13 */
  14
  15#include <linux/kernel.h>
  16#include <linux/slab.h>
  17#include <linux/init.h>
  18#include <linux/module.h>
  19#include <linux/delay.h>
  20#include <linux/mtd/mtd.h>
  21#include <linux/mtd/nand-ecc-sw-hamming.h>
  22#include <linux/mtd/rawnand.h>
  23#include <linux/mtd/partitions.h>
  24#include <linux/iopoll.h>
  25
  26#include <asm/msr.h>
  27
  28#define NR_CS553X_CONTROLLERS   4
  29
  30#define MSR_DIVIL_GLD_CAP       0x51400000      /* DIVIL capabilitiies */
  31#define CAP_CS5535              0x2df000ULL
  32#define CAP_CS5536              0x5df500ULL
  33
  34/* NAND Timing MSRs */
  35#define MSR_NANDF_DATA          0x5140001b      /* NAND Flash Data Timing MSR */
  36#define MSR_NANDF_CTL           0x5140001c      /* NAND Flash Control Timing */
  37#define MSR_NANDF_RSVD          0x5140001d      /* Reserved */
  38
  39/* NAND BAR MSRs */
  40#define MSR_DIVIL_LBAR_FLSH0    0x51400010      /* Flash Chip Select 0 */
  41#define MSR_DIVIL_LBAR_FLSH1    0x51400011      /* Flash Chip Select 1 */
  42#define MSR_DIVIL_LBAR_FLSH2    0x51400012      /* Flash Chip Select 2 */
  43#define MSR_DIVIL_LBAR_FLSH3    0x51400013      /* Flash Chip Select 3 */
  44        /* Each made up of... */
  45#define FLSH_LBAR_EN            (1ULL<<32)
  46#define FLSH_NOR_NAND           (1ULL<<33)      /* 1 for NAND */
  47#define FLSH_MEM_IO             (1ULL<<34)      /* 1 for MMIO */
  48        /* I/O BARs have BASE_ADDR in bits 15:4, IO_MASK in 47:36 */
  49        /* MMIO BARs have BASE_ADDR in bits 31:12, MEM_MASK in 63:44 */
  50
  51/* Pin function selection MSR (IDE vs. flash on the IDE pins) */
  52#define MSR_DIVIL_BALL_OPTS     0x51400015
  53#define PIN_OPT_IDE             (1<<0)  /* 0 for flash, 1 for IDE */
  54
  55/* Registers within the NAND flash controller BAR -- memory mapped */
  56#define MM_NAND_DATA            0x00    /* 0 to 0x7ff, in fact */
  57#define MM_NAND_CTL             0x800   /* Any even address 0x800-0x80e */
  58#define MM_NAND_IO              0x801   /* Any odd address 0x801-0x80f */
  59#define MM_NAND_STS             0x810
  60#define MM_NAND_ECC_LSB         0x811
  61#define MM_NAND_ECC_MSB         0x812
  62#define MM_NAND_ECC_COL         0x813
  63#define MM_NAND_LAC             0x814
  64#define MM_NAND_ECC_CTL         0x815
  65
  66/* Registers within the NAND flash controller BAR -- I/O mapped */
  67#define IO_NAND_DATA            0x00    /* 0 to 3, in fact */
  68#define IO_NAND_CTL             0x04
  69#define IO_NAND_IO              0x05
  70#define IO_NAND_STS             0x06
  71#define IO_NAND_ECC_CTL         0x08
  72#define IO_NAND_ECC_LSB         0x09
  73#define IO_NAND_ECC_MSB         0x0a
  74#define IO_NAND_ECC_COL         0x0b
  75#define IO_NAND_LAC             0x0c
  76
  77#define CS_NAND_CTL_DIST_EN     (1<<4)  /* Enable NAND Distract interrupt */
  78#define CS_NAND_CTL_RDY_INT_MASK        (1<<3)  /* Enable RDY/BUSY# interrupt */
  79#define CS_NAND_CTL_ALE         (1<<2)
  80#define CS_NAND_CTL_CLE         (1<<1)
  81#define CS_NAND_CTL_CE          (1<<0)  /* Keep low; 1 to reset */
  82
  83#define CS_NAND_STS_FLASH_RDY   (1<<3)
  84#define CS_NAND_CTLR_BUSY       (1<<2)
  85#define CS_NAND_CMD_COMP        (1<<1)
  86#define CS_NAND_DIST_ST         (1<<0)
  87
  88#define CS_NAND_ECC_PARITY      (1<<2)
  89#define CS_NAND_ECC_CLRECC      (1<<1)
  90#define CS_NAND_ECC_ENECC       (1<<0)
  91
  92struct cs553x_nand_controller {
  93        struct nand_controller base;
  94        struct nand_chip chip;
  95        void __iomem *mmio;
  96};
  97
  98static struct cs553x_nand_controller *
  99to_cs553x(struct nand_controller *controller)
 100{
 101        return container_of(controller, struct cs553x_nand_controller, base);
 102}
 103
 104static int cs553x_write_ctrl_byte(struct cs553x_nand_controller *cs553x,
 105                                  u32 ctl, u8 data)
 106{
 107        u8 status;
 108        int ret;
 109
 110        writeb(ctl, cs553x->mmio + MM_NAND_CTL);
 111        writeb(data, cs553x->mmio + MM_NAND_IO);
 112        ret = readb_poll_timeout_atomic(cs553x->mmio + MM_NAND_STS, status,
 113                                        !(status & CS_NAND_CTLR_BUSY), 1,
 114                                        100000);
 115        if (ret)
 116                return ret;
 117
 118        return 0;
 119}
 120
 121static void cs553x_data_in(struct cs553x_nand_controller *cs553x, void *buf,
 122                           unsigned int len)
 123{
 124        writeb(0, cs553x->mmio + MM_NAND_CTL);
 125        while (unlikely(len > 0x800)) {
 126                memcpy_fromio(buf, cs553x->mmio, 0x800);
 127                buf += 0x800;
 128                len -= 0x800;
 129        }
 130        memcpy_fromio(buf, cs553x->mmio, len);
 131}
 132
 133static void cs553x_data_out(struct cs553x_nand_controller *cs553x,
 134                            const void *buf, unsigned int len)
 135{
 136        writeb(0, cs553x->mmio + MM_NAND_CTL);
 137        while (unlikely(len > 0x800)) {
 138                memcpy_toio(cs553x->mmio, buf, 0x800);
 139                buf += 0x800;
 140                len -= 0x800;
 141        }
 142        memcpy_toio(cs553x->mmio, buf, len);
 143}
 144
 145static int cs553x_wait_ready(struct cs553x_nand_controller *cs553x,
 146                             unsigned int timeout_ms)
 147{
 148        u8 mask = CS_NAND_CTLR_BUSY | CS_NAND_STS_FLASH_RDY;
 149        u8 status;
 150
 151        return readb_poll_timeout(cs553x->mmio + MM_NAND_STS, status,
 152                                  (status & mask) == CS_NAND_STS_FLASH_RDY, 100,
 153                                  timeout_ms * 1000);
 154}
 155
 156static int cs553x_exec_instr(struct cs553x_nand_controller *cs553x,
 157                             const struct nand_op_instr *instr)
 158{
 159        unsigned int i;
 160        int ret = 0;
 161
 162        switch (instr->type) {
 163        case NAND_OP_CMD_INSTR:
 164                ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_CLE,
 165                                             instr->ctx.cmd.opcode);
 166                break;
 167
 168        case NAND_OP_ADDR_INSTR:
 169                for (i = 0; i < instr->ctx.addr.naddrs; i++) {
 170                        ret = cs553x_write_ctrl_byte(cs553x, CS_NAND_CTL_ALE,
 171                                                     instr->ctx.addr.addrs[i]);
 172                        if (ret)
 173                                break;
 174                }
 175                break;
 176
 177        case NAND_OP_DATA_IN_INSTR:
 178                cs553x_data_in(cs553x, instr->ctx.data.buf.in,
 179                               instr->ctx.data.len);
 180                break;
 181
 182        case NAND_OP_DATA_OUT_INSTR:
 183                cs553x_data_out(cs553x, instr->ctx.data.buf.out,
 184                                instr->ctx.data.len);
 185                break;
 186
 187        case NAND_OP_WAITRDY_INSTR:
 188                ret = cs553x_wait_ready(cs553x, instr->ctx.waitrdy.timeout_ms);
 189                break;
 190        }
 191
 192        if (instr->delay_ns)
 193                ndelay(instr->delay_ns);
 194
 195        return ret;
 196}
 197
 198static int cs553x_exec_op(struct nand_chip *this,
 199                          const struct nand_operation *op,
 200                          bool check_only)
 201{
 202        struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
 203        unsigned int i;
 204        int ret;
 205
 206        if (check_only)
 207                return true;
 208
 209        /* De-assert the CE pin */
 210        writeb(0, cs553x->mmio + MM_NAND_CTL);
 211        for (i = 0; i < op->ninstrs; i++) {
 212                ret = cs553x_exec_instr(cs553x, &op->instrs[i]);
 213                if (ret)
 214                        break;
 215        }
 216
 217        /* Re-assert the CE pin. */
 218        writeb(CS_NAND_CTL_CE, cs553x->mmio + MM_NAND_CTL);
 219
 220        return ret;
 221}
 222
 223static void cs_enable_hwecc(struct nand_chip *this, int mode)
 224{
 225        struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
 226
 227        writeb(0x07, cs553x->mmio + MM_NAND_ECC_CTL);
 228}
 229
 230static int cs_calculate_ecc(struct nand_chip *this, const u_char *dat,
 231                            u_char *ecc_code)
 232{
 233        struct cs553x_nand_controller *cs553x = to_cs553x(this->controller);
 234        uint32_t ecc;
 235
 236        ecc = readl(cs553x->mmio + MM_NAND_STS);
 237
 238        ecc_code[1] = ecc >> 8;
 239        ecc_code[0] = ecc >> 16;
 240        ecc_code[2] = ecc >> 24;
 241        return 0;
 242}
 243
 244static int cs553x_ecc_correct(struct nand_chip *chip,
 245                              unsigned char *buf,
 246                              unsigned char *read_ecc,
 247                              unsigned char *calc_ecc)
 248{
 249        return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
 250                                      chip->ecc.size, false);
 251}
 252
 253static struct cs553x_nand_controller *controllers[4];
 254
 255static int cs553x_attach_chip(struct nand_chip *chip)
 256{
 257        if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
 258                return 0;
 259
 260        chip->ecc.size = 256;
 261        chip->ecc.bytes = 3;
 262        chip->ecc.hwctl  = cs_enable_hwecc;
 263        chip->ecc.calculate = cs_calculate_ecc;
 264        chip->ecc.correct  = cs553x_ecc_correct;
 265        chip->ecc.strength = 1;
 266
 267        return 0;
 268}
 269
 270static const struct nand_controller_ops cs553x_nand_controller_ops = {
 271        .exec_op = cs553x_exec_op,
 272        .attach_chip = cs553x_attach_chip,
 273};
 274
 275static int __init cs553x_init_one(int cs, int mmio, unsigned long adr)
 276{
 277        struct cs553x_nand_controller *controller;
 278        int err = 0;
 279        struct nand_chip *this;
 280        struct mtd_info *new_mtd;
 281
 282        pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n",
 283                  cs, mmio ? "MM" : "P", adr);
 284
 285        if (!mmio) {
 286                pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");
 287                return -ENXIO;
 288        }
 289
 290        /* Allocate memory for MTD device structure and private data */
 291        controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 292        if (!controller) {
 293                err = -ENOMEM;
 294                goto out;
 295        }
 296
 297        this = &controller->chip;
 298        nand_controller_init(&controller->base);
 299        controller->base.ops = &cs553x_nand_controller_ops;
 300        this->controller = &controller->base;
 301        new_mtd = nand_to_mtd(this);
 302
 303        /* Link the private data with the MTD structure */
 304        new_mtd->owner = THIS_MODULE;
 305
 306        /* map physical address */
 307        controller->mmio = ioremap(adr, 4096);
 308        if (!controller->mmio) {
 309                pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
 310                err = -EIO;
 311                goto out_mtd;
 312        }
 313
 314        /* Enable the following for a flash based bad block table */
 315        this->bbt_options = NAND_BBT_USE_FLASH;
 316
 317        new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
 318        if (!new_mtd->name) {
 319                err = -ENOMEM;
 320                goto out_ior;
 321        }
 322
 323        /* Scan to find existence of the device */
 324        err = nand_scan(this, 1);
 325        if (err)
 326                goto out_free;
 327
 328        controllers[cs] = controller;
 329        goto out;
 330
 331out_free:
 332        kfree(new_mtd->name);
 333out_ior:
 334        iounmap(controller->mmio);
 335out_mtd:
 336        kfree(controller);
 337out:
 338        return err;
 339}
 340
 341static int is_geode(void)
 342{
 343        /* These are the CPUs which will have a CS553[56] companion chip */
 344        if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
 345            boot_cpu_data.x86 == 5 &&
 346            boot_cpu_data.x86_model == 10)
 347                return 1; /* Geode LX */
 348
 349        if ((boot_cpu_data.x86_vendor == X86_VENDOR_NSC ||
 350             boot_cpu_data.x86_vendor == X86_VENDOR_CYRIX) &&
 351            boot_cpu_data.x86 == 5 &&
 352            boot_cpu_data.x86_model == 5)
 353                return 1; /* Geode GX (n\xC3\xA9e GX2) */
 354
 355        return 0;
 356}
 357
 358static int __init cs553x_init(void)
 359{
 360        int err = -ENXIO;
 361        int i;
 362        uint64_t val;
 363
 364        /* If the CPU isn't a Geode GX or LX, abort */
 365        if (!is_geode())
 366                return -ENXIO;
 367
 368        /* If it doesn't have the CS553[56], abort */
 369        rdmsrl(MSR_DIVIL_GLD_CAP, val);
 370        val &= ~0xFFULL;
 371        if (val != CAP_CS5535 && val != CAP_CS5536)
 372                return -ENXIO;
 373
 374        /* If it doesn't have the NAND controller enabled, abort */
 375        rdmsrl(MSR_DIVIL_BALL_OPTS, val);
 376        if (val & PIN_OPT_IDE) {
 377                pr_info("CS553x NAND controller: Flash I/O not enabled in MSR_DIVIL_BALL_OPTS.\n");
 378                return -ENXIO;
 379        }
 380
 381        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 382                rdmsrl(MSR_DIVIL_LBAR_FLSH0 + i, val);
 383
 384                if ((val & (FLSH_LBAR_EN|FLSH_NOR_NAND)) == (FLSH_LBAR_EN|FLSH_NOR_NAND))
 385                        err = cs553x_init_one(i, !!(val & FLSH_MEM_IO), val & 0xFFFFFFFF);
 386        }
 387
 388        /* Register all devices together here. This means we can easily hack it to
 389           do mtdconcat etc. if we want to. */
 390        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 391                if (controllers[i]) {
 392                        /* If any devices registered, return success. Else the last error. */
 393                        mtd_device_register(nand_to_mtd(&controllers[i]->chip),
 394                                            NULL, 0);
 395                        err = 0;
 396                }
 397        }
 398
 399        return err;
 400}
 401
 402module_init(cs553x_init);
 403
 404static void __exit cs553x_cleanup(void)
 405{
 406        int i;
 407
 408        for (i = 0; i < NR_CS553X_CONTROLLERS; i++) {
 409                struct cs553x_nand_controller *controller = controllers[i];
 410                struct nand_chip *this = &controller->chip;
 411                struct mtd_info *mtd = nand_to_mtd(this);
 412                int ret;
 413
 414                if (!mtd)
 415                        continue;
 416
 417                /* Release resources, unregister device */
 418                ret = mtd_device_unregister(mtd);
 419                WARN_ON(ret);
 420                nand_cleanup(this);
 421                kfree(mtd->name);
 422                controllers[i] = NULL;
 423
 424                /* unmap physical address */
 425                iounmap(controller->mmio);
 426
 427                /* Free the MTD device structure */
 428                kfree(controller);
 429        }
 430}
 431
 432module_exit(cs553x_cleanup);
 433
 434MODULE_LICENSE("GPL");
 435MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
 436MODULE_DESCRIPTION("NAND controller driver for AMD CS5535/CS5536 companion chip");
 437