linux/drivers/mtd/maps/sc520cdp.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform
   3 *
   4 * Copyright (C) 2001 Sysgo Real-Time Solutions GmbH
   5 *
   6 * The SC520CDP is an evaluation board for the Elan SC520 processor available
   7 * from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
   8 * and up to 512 KiB of 8-bit DIL Flash ROM.
   9 * For details see https://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/types.h>
  14#include <linux/kernel.h>
  15#include <linux/init.h>
  16#include <asm/io.h>
  17#include <linux/mtd/mtd.h>
  18#include <linux/mtd/map.h>
  19#include <linux/mtd/concat.h>
  20
  21/*
  22** The Embedded Systems BIOS decodes the first FLASH starting at
  23** 0x8400000. This is a *terrible* place for it because accessing
  24** the flash at this location causes the A22 address line to be high
  25** (that's what 0x8400000 binary's ought to be). But this is the highest
  26** order address line on the raw flash devices themselves!!
  27** This causes the top HALF of the flash to be accessed first. Beyond
  28** the physical limits of the flash, the flash chip aliases over (to
  29** 0x880000 which causes the bottom half to be accessed. This splits the
  30** flash into two and inverts it! If you then try to access this from another
  31** program that does NOT do this insanity, then you *will* access the
  32** first half of the flash, but not find what you expect there. That
  33** stuff is in the *second* half! Similarly, the address used by the
  34** BIOS for the second FLASH bank is also quite a bad choice.
  35** If REPROGRAM_PAR is defined below (the default), then this driver will
  36** choose more useful addresses for the FLASH banks by reprogramming the
  37** responsible PARxx registers in the SC520's MMCR region. This will
  38** cause the settings to be incompatible with the BIOS's settings, which
  39** shouldn't be a problem since you are running Linux, (i.e. the BIOS is
  40** not much use anyway). However, if you need to be compatible with
  41** the BIOS for some reason, just undefine REPROGRAM_PAR.
  42*/
  43#define REPROGRAM_PAR
  44
  45
  46
  47#ifdef REPROGRAM_PAR
  48
  49/* These are the addresses we want.. */
  50#define WINDOW_ADDR_0   0x08800000
  51#define WINDOW_ADDR_1   0x09000000
  52#define WINDOW_ADDR_2   0x09800000
  53
  54/* .. and these are the addresses the BIOS gives us */
  55#define WINDOW_ADDR_0_BIOS      0x08400000
  56#define WINDOW_ADDR_1_BIOS      0x08c00000
  57#define WINDOW_ADDR_2_BIOS      0x09400000
  58
  59#else
  60
  61#define WINDOW_ADDR_0   0x08400000
  62#define WINDOW_ADDR_1   0x08C00000
  63#define WINDOW_ADDR_2   0x09400000
  64
  65#endif
  66
  67#define WINDOW_SIZE_0   0x00800000
  68#define WINDOW_SIZE_1   0x00800000
  69#define WINDOW_SIZE_2   0x00080000
  70
  71
  72static struct map_info sc520cdp_map[] = {
  73        {
  74                .name = "SC520CDP Flash Bank #0",
  75                .size = WINDOW_SIZE_0,
  76                .bankwidth = 4,
  77                .phys = WINDOW_ADDR_0
  78        },
  79        {
  80                .name = "SC520CDP Flash Bank #1",
  81                .size = WINDOW_SIZE_1,
  82                .bankwidth = 4,
  83                .phys = WINDOW_ADDR_1
  84        },
  85        {
  86                .name = "SC520CDP DIL Flash",
  87                .size = WINDOW_SIZE_2,
  88                .bankwidth = 1,
  89                .phys = WINDOW_ADDR_2
  90        },
  91};
  92
  93#define NUM_FLASH_BANKS ARRAY_SIZE(sc520cdp_map)
  94
  95static struct mtd_info *mymtd[NUM_FLASH_BANKS];
  96static struct mtd_info *merged_mtd;
  97
  98#ifdef REPROGRAM_PAR
  99
 100/*
 101** The SC520 MMCR (memory mapped control register) region resides
 102** at 0xFFFEF000. The 16 Programmable Address Region (PAR) registers
 103** are at offset 0x88 in the MMCR:
 104*/
 105#define SC520_MMCR_BASE         0xFFFEF000
 106#define SC520_MMCR_EXTENT       0x1000
 107#define SC520_PAR(x)            ((0x88/sizeof(unsigned long)) + (x))
 108#define NUM_SC520_PAR           16      /* total number of PAR registers */
 109
 110/*
 111** The highest three bits in a PAR register determine what target
 112** device is controlled by this PAR. Here, only ROMCS? and BOOTCS
 113** devices are of interest.
 114*/
 115#define SC520_PAR_BOOTCS        (0x4<<29)
 116#define SC520_PAR_ROMCS0        (0x5<<29)
 117#define SC520_PAR_ROMCS1        (0x6<<29)
 118#define SC520_PAR_TRGDEV        (0x7<<29)
 119
 120/*
 121** Bits 28 thru 26 determine some attributes for the
 122** region controlled by the PAR. (We only use non-cacheable)
 123*/
 124#define SC520_PAR_WRPROT        (1<<26) /* write protected       */
 125#define SC520_PAR_NOCACHE       (1<<27) /* non-cacheable         */
 126#define SC520_PAR_NOEXEC        (1<<28) /* code execution denied */
 127
 128
 129/*
 130** Bit 25 determines the granularity: 4K or 64K
 131*/
 132#define SC520_PAR_PG_SIZ4       (0<<25)
 133#define SC520_PAR_PG_SIZ64      (1<<25)
 134
 135/*
 136** Build a value to be written into a PAR register.
 137** We only need ROM entries, 64K page size:
 138*/
 139#define SC520_PAR_ENTRY(trgdev, address, size) \
 140        ((trgdev) | SC520_PAR_NOCACHE | SC520_PAR_PG_SIZ64 | \
 141        (address) >> 16 | (((size) >> 16) - 1) << 14)
 142
 143struct sc520_par_table
 144{
 145        unsigned long trgdev;
 146        unsigned long new_par;
 147        unsigned long default_address;
 148};
 149
 150static const struct sc520_par_table par_table[NUM_FLASH_BANKS] =
 151{
 152        {       /* Flash Bank #0: selected by ROMCS0 */
 153                SC520_PAR_ROMCS0,
 154                SC520_PAR_ENTRY(SC520_PAR_ROMCS0, WINDOW_ADDR_0, WINDOW_SIZE_0),
 155                WINDOW_ADDR_0_BIOS
 156        },
 157        {       /* Flash Bank #1: selected by ROMCS1 */
 158                SC520_PAR_ROMCS1,
 159                SC520_PAR_ENTRY(SC520_PAR_ROMCS1, WINDOW_ADDR_1, WINDOW_SIZE_1),
 160                WINDOW_ADDR_1_BIOS
 161        },
 162        {       /* DIL (BIOS) Flash: selected by BOOTCS */
 163                SC520_PAR_BOOTCS,
 164                SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2),
 165                WINDOW_ADDR_2_BIOS
 166        }
 167};
 168
 169
 170static void sc520cdp_setup_par(void)
 171{
 172        unsigned long __iomem *mmcr;
 173        unsigned long mmcr_val;
 174        int i, j;
 175
 176        /* map in SC520's MMCR area */
 177        mmcr = ioremap(SC520_MMCR_BASE, SC520_MMCR_EXTENT);
 178        if(!mmcr) { /* ioremap failed: skip the PAR reprogramming */
 179                /* force physical address fields to BIOS defaults: */
 180                for(i = 0; i < NUM_FLASH_BANKS; i++)
 181                        sc520cdp_map[i].phys = par_table[i].default_address;
 182                return;
 183        }
 184
 185        /*
 186        ** Find the PARxx registers that are responsible for activating
 187        ** ROMCS0, ROMCS1 and BOOTCS. Reprogram each of these with a
 188        ** new value from the table.
 189        */
 190        for(i = 0; i < NUM_FLASH_BANKS; i++) {          /* for each par_table entry  */
 191                for(j = 0; j < NUM_SC520_PAR; j++) {    /* for each PAR register     */
 192                        mmcr_val = readl(&mmcr[SC520_PAR(j)]);
 193                        /* if target device field matches, reprogram the PAR */
 194                        if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev)
 195                        {
 196                                writel(par_table[i].new_par, &mmcr[SC520_PAR(j)]);
 197                                break;
 198                        }
 199                }
 200                if(j == NUM_SC520_PAR)
 201                {       /* no matching PAR found: try default BIOS address */
 202                        printk(KERN_NOTICE "Could not find PAR responsible for %s\n",
 203                                sc520cdp_map[i].name);
 204                        printk(KERN_NOTICE "Trying default address 0x%lx\n",
 205                                par_table[i].default_address);
 206                        sc520cdp_map[i].phys = par_table[i].default_address;
 207                }
 208        }
 209        iounmap(mmcr);
 210}
 211#endif
 212
 213
 214static int __init init_sc520cdp(void)
 215{
 216        int i, j, devices_found = 0;
 217
 218#ifdef REPROGRAM_PAR
 219        /* reprogram PAR registers so flash appears at the desired addresses */
 220        sc520cdp_setup_par();
 221#endif
 222
 223        for (i = 0; i < NUM_FLASH_BANKS; i++) {
 224                printk(KERN_NOTICE "SC520 CDP flash device: 0x%Lx at 0x%Lx\n",
 225                        (unsigned long long)sc520cdp_map[i].size,
 226                        (unsigned long long)sc520cdp_map[i].phys);
 227
 228                sc520cdp_map[i].virt = ioremap(sc520cdp_map[i].phys, sc520cdp_map[i].size);
 229
 230                if (!sc520cdp_map[i].virt) {
 231                        printk("Failed to ioremap\n");
 232                        for (j = 0; j < i; j++) {
 233                                if (mymtd[j]) {
 234                                        map_destroy(mymtd[j]);
 235                                        iounmap(sc520cdp_map[j].virt);
 236                                }
 237                        }
 238                        return -EIO;
 239                }
 240
 241                simple_map_init(&sc520cdp_map[i]);
 242
 243                mymtd[i] = do_map_probe("cfi_probe", &sc520cdp_map[i]);
 244                if(!mymtd[i])
 245                        mymtd[i] = do_map_probe("jedec_probe", &sc520cdp_map[i]);
 246                if(!mymtd[i])
 247                        mymtd[i] = do_map_probe("map_rom", &sc520cdp_map[i]);
 248
 249                if (mymtd[i]) {
 250                        mymtd[i]->owner = THIS_MODULE;
 251                        ++devices_found;
 252                }
 253                else {
 254                        iounmap(sc520cdp_map[i].virt);
 255                }
 256        }
 257        if(devices_found >= 2) {
 258                /* Combine the two flash banks into a single MTD device & register it: */
 259                merged_mtd = mtd_concat_create(mymtd, 2, "SC520CDP Flash Banks #0 and #1");
 260                if(merged_mtd)
 261                        mtd_device_register(merged_mtd, NULL, 0);
 262        }
 263        if(devices_found == 3) /* register the third (DIL-Flash) device */
 264                mtd_device_register(mymtd[2], NULL, 0);
 265        return(devices_found ? 0 : -ENXIO);
 266}
 267
 268static void __exit cleanup_sc520cdp(void)
 269{
 270        int i;
 271
 272        if (merged_mtd) {
 273                mtd_device_unregister(merged_mtd);
 274                mtd_concat_destroy(merged_mtd);
 275        }
 276        if (mymtd[2])
 277                mtd_device_unregister(mymtd[2]);
 278
 279        for (i = 0; i < NUM_FLASH_BANKS; i++) {
 280                if (mymtd[i])
 281                        map_destroy(mymtd[i]);
 282                if (sc520cdp_map[i].virt) {
 283                        iounmap(sc520cdp_map[i].virt);
 284                        sc520cdp_map[i].virt = NULL;
 285                }
 286        }
 287}
 288
 289module_init(init_sc520cdp);
 290module_exit(cleanup_sc520cdp);
 291
 292MODULE_LICENSE("GPL");
 293MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
 294MODULE_DESCRIPTION("MTD map driver for AMD SC520 Customer Development Platform");
 295