linux/drivers/misc/habanalabs/gaudi/gaudiP.h
<<
>>
Prefs
   1/* SPDX-License-Identifier: GPL-2.0
   2 *
   3 * Copyright 2019-2020 HabanaLabs, Ltd.
   4 * All Rights Reserved.
   5 *
   6 */
   7
   8#ifndef GAUDIP_H_
   9#define GAUDIP_H_
  10
  11#include <uapi/misc/habanalabs.h>
  12#include "../common/habanalabs.h"
  13#include "../include/common/hl_boot_if.h"
  14#include "../include/gaudi/gaudi_packets.h"
  15#include "../include/gaudi/gaudi.h"
  16#include "../include/gaudi/gaudi_async_events.h"
  17#include "../include/gaudi/gaudi_fw_if.h"
  18
  19#define NUMBER_OF_EXT_HW_QUEUES         8
  20#define NUMBER_OF_CMPLT_QUEUES          NUMBER_OF_EXT_HW_QUEUES
  21#define NUMBER_OF_CPU_HW_QUEUES         1
  22#define NUMBER_OF_INT_HW_QUEUES         100
  23#define NUMBER_OF_HW_QUEUES             (NUMBER_OF_EXT_HW_QUEUES + \
  24                                        NUMBER_OF_CPU_HW_QUEUES + \
  25                                        NUMBER_OF_INT_HW_QUEUES)
  26
  27/* 10 NIC QMANs, DMA5 QMAN, TPC7 QMAN */
  28#define NUMBER_OF_COLLECTIVE_QUEUES     12
  29#define NUMBER_OF_SOBS_IN_GRP           11
  30
  31/*
  32 * Number of MSI interrupts IDS:
  33 * Each completion queue has 1 ID
  34 * The event queue has 1 ID
  35 */
  36#define NUMBER_OF_INTERRUPTS            (NUMBER_OF_CMPLT_QUEUES + \
  37                                                NUMBER_OF_CPU_HW_QUEUES)
  38
  39#if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES)
  40#error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES"
  41#endif
  42
  43#define CORESIGHT_TIMEOUT_USEC          100000          /* 100 ms */
  44
  45#define GAUDI_MAX_CLK_FREQ              2200000000ull   /* 2200 MHz */
  46
  47#define MAX_POWER_DEFAULT_PCI           200000          /* 200W */
  48#define MAX_POWER_DEFAULT_PMC           350000          /* 350W */
  49
  50#define DC_POWER_DEFAULT_PCI            60000           /* 60W */
  51#define DC_POWER_DEFAULT_PMC            60000           /* 60W */
  52
  53#define GAUDI_CPU_TIMEOUT_USEC          30000000        /* 30s */
  54
  55#define TPC_ENABLED_MASK                0xFF
  56
  57#define GAUDI_HBM_SIZE_32GB             0x800000000ull
  58#define GAUDI_HBM_DEVICES               4
  59#define GAUDI_HBM_CHANNELS              8
  60#define GAUDI_HBM_CFG_BASE              (mmHBM0_BASE - CFG_BASE)
  61#define GAUDI_HBM_CFG_OFFSET            (mmHBM1_BASE - mmHBM0_BASE)
  62
  63#define DMA_MAX_TRANSFER_SIZE           U32_MAX
  64
  65#define GAUDI_DEFAULT_CARD_NAME         "HL2000"
  66
  67#define GAUDI_MAX_PENDING_CS            SZ_16K
  68
  69#if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS)
  70#error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
  71#endif
  72
  73#define PCI_DMA_NUMBER_OF_CHNLS         2
  74#define HBM_DMA_NUMBER_OF_CHNLS         6
  75#define DMA_NUMBER_OF_CHNLS             (PCI_DMA_NUMBER_OF_CHNLS + \
  76                                                HBM_DMA_NUMBER_OF_CHNLS)
  77
  78#define MME_NUMBER_OF_SLAVE_ENGINES     2
  79#define MME_NUMBER_OF_ENGINES           (MME_NUMBER_OF_MASTER_ENGINES + \
  80                                        MME_NUMBER_OF_SLAVE_ENGINES)
  81#define MME_NUMBER_OF_QMANS             (MME_NUMBER_OF_MASTER_ENGINES * \
  82                                        QMAN_STREAMS)
  83
  84#define QMAN_STREAMS            4
  85#define PQ_FETCHER_CACHE_SIZE   8
  86
  87#define DMA_QMAN_OFFSET         (mmDMA1_QM_BASE - mmDMA0_QM_BASE)
  88#define TPC_QMAN_OFFSET         (mmTPC1_QM_BASE - mmTPC0_QM_BASE)
  89#define MME_QMAN_OFFSET         (mmMME1_QM_BASE - mmMME0_QM_BASE)
  90#define NIC_MACRO_QMAN_OFFSET   (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
  91#define NIC_ENGINE_QMAN_OFFSET  (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
  92
  93#define TPC_CFG_OFFSET          (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
  94
  95#define DMA_CORE_OFFSET         (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)
  96
  97#define QMAN_LDMA_SRC_OFFSET    (mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)
  98#define QMAN_LDMA_DST_OFFSET    (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
  99#define QMAN_LDMA_SIZE_OFFSET   (mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)
 100
 101#define QMAN_CPDMA_SRC_OFFSET   (mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)
 102#define QMAN_CPDMA_DST_OFFSET   (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
 103#define QMAN_CPDMA_SIZE_OFFSET  (mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)
 104
 105#define SIF_RTR_CTRL_OFFSET     (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)
 106
 107#define NIF_RTR_CTRL_OFFSET     (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)
 108
 109#define MME_ACC_OFFSET          (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
 110#define SRAM_BANK_OFFSET        (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
 111
 112#define NUM_OF_SOB_IN_BLOCK             \
 113        (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
 114        mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
 115
 116#define NUM_OF_MONITORS_IN_BLOCK        \
 117        (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \
 118        mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
 119
 120
 121/* DRAM Memory Map */
 122
 123#define CPU_FW_IMAGE_SIZE       0x10000000      /* 256MB */
 124#define MMU_PAGE_TABLES_SIZE    0x0BF00000      /* 191MB */
 125#define MMU_CACHE_MNG_SIZE      0x00100000      /* 1MB */
 126#define RESERVED                0x04000000      /* 64MB */
 127
 128#define CPU_FW_IMAGE_ADDR       DRAM_PHYS_BASE
 129#define MMU_PAGE_TABLES_ADDR    (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
 130#define MMU_CACHE_MNG_ADDR      (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
 131
 132#define DRAM_DRIVER_END_ADDR    (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\
 133                                                                RESERVED)
 134
 135#define DRAM_BASE_ADDR_USER     0x20000000
 136
 137#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
 138#error "Driver must reserve no more than 512MB"
 139#endif
 140
 141/* Internal QMANs PQ sizes */
 142
 143#define MME_QMAN_LENGTH                 1024
 144#define MME_QMAN_SIZE_IN_BYTES          (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
 145
 146#define HBM_DMA_QMAN_LENGTH             1024
 147#define HBM_DMA_QMAN_SIZE_IN_BYTES      \
 148                                (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
 149
 150#define TPC_QMAN_LENGTH                 1024
 151#define TPC_QMAN_SIZE_IN_BYTES          (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
 152
 153#define NIC_QMAN_LENGTH                 1024
 154#define NIC_QMAN_SIZE_IN_BYTES          (NIC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
 155
 156
 157#define SRAM_USER_BASE_OFFSET  GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
 158
 159/* Virtual address space */
 160#define VA_HOST_SPACE_START     0x1000000000000ull      /* 256TB */
 161#define VA_HOST_SPACE_END       0x3FF8000000000ull      /* 1PB - 512GB */
 162#define VA_HOST_SPACE_SIZE      (VA_HOST_SPACE_END - \
 163                                        VA_HOST_SPACE_START) /* 767TB */
 164#define HOST_SPACE_INTERNAL_CB_SZ       SZ_2M
 165
 166#define HW_CAP_PLL              BIT(0)
 167#define HW_CAP_HBM              BIT(1)
 168#define HW_CAP_MMU              BIT(2)
 169#define HW_CAP_MME              BIT(3)
 170#define HW_CAP_CPU              BIT(4)
 171#define HW_CAP_PCI_DMA          BIT(5)
 172#define HW_CAP_MSI              BIT(6)
 173#define HW_CAP_CPU_Q            BIT(7)
 174#define HW_CAP_HBM_DMA          BIT(8)
 175#define HW_CAP_CLK_GATE         BIT(9)
 176#define HW_CAP_SRAM_SCRAMBLER   BIT(10)
 177#define HW_CAP_HBM_SCRAMBLER    BIT(11)
 178
 179#define HW_CAP_NIC0             BIT(14)
 180#define HW_CAP_NIC1             BIT(15)
 181#define HW_CAP_NIC2             BIT(16)
 182#define HW_CAP_NIC3             BIT(17)
 183#define HW_CAP_NIC4             BIT(18)
 184#define HW_CAP_NIC5             BIT(19)
 185#define HW_CAP_NIC6             BIT(20)
 186#define HW_CAP_NIC7             BIT(21)
 187#define HW_CAP_NIC8             BIT(22)
 188#define HW_CAP_NIC9             BIT(23)
 189#define HW_CAP_NIC_MASK         GENMASK(23, 14)
 190#define HW_CAP_NIC_SHIFT        14
 191
 192#define HW_CAP_TPC0             BIT(24)
 193#define HW_CAP_TPC1             BIT(25)
 194#define HW_CAP_TPC2             BIT(26)
 195#define HW_CAP_TPC3             BIT(27)
 196#define HW_CAP_TPC4             BIT(28)
 197#define HW_CAP_TPC5             BIT(29)
 198#define HW_CAP_TPC6             BIT(30)
 199#define HW_CAP_TPC7             BIT(31)
 200#define HW_CAP_TPC_MASK         GENMASK(31, 24)
 201#define HW_CAP_TPC_SHIFT        24
 202
 203#define GAUDI_CPU_PCI_MSB_ADDR(addr)    (((addr) & GENMASK_ULL(49, 39)) >> 39)
 204#define GAUDI_PCI_TO_CPU_ADDR(addr)                     \
 205        do {                                            \
 206                (addr) &= ~GENMASK_ULL(49, 39);         \
 207                (addr) |= BIT_ULL(39);                  \
 208        } while (0)
 209#define GAUDI_CPU_TO_PCI_ADDR(addr, extension)          \
 210        do {                                            \
 211                (addr) &= ~GENMASK_ULL(49, 39);         \
 212                (addr) |= (u64) (extension) << 39;      \
 213        } while (0)
 214
 215enum gaudi_dma_channels {
 216        GAUDI_PCI_DMA_1,
 217        GAUDI_PCI_DMA_2,
 218        GAUDI_HBM_DMA_1,
 219        GAUDI_HBM_DMA_2,
 220        GAUDI_HBM_DMA_3,
 221        GAUDI_HBM_DMA_4,
 222        GAUDI_HBM_DMA_5,
 223        GAUDI_HBM_DMA_6,
 224        GAUDI_DMA_MAX
 225};
 226
 227enum gaudi_tpc_mask {
 228        GAUDI_TPC_MASK_TPC0 = 0x01,
 229        GAUDI_TPC_MASK_TPC1 = 0x02,
 230        GAUDI_TPC_MASK_TPC2 = 0x04,
 231        GAUDI_TPC_MASK_TPC3 = 0x08,
 232        GAUDI_TPC_MASK_TPC4 = 0x10,
 233        GAUDI_TPC_MASK_TPC5 = 0x20,
 234        GAUDI_TPC_MASK_TPC6 = 0x40,
 235        GAUDI_TPC_MASK_TPC7 = 0x80,
 236        GAUDI_TPC_MASK_ALL = 0xFF
 237};
 238
 239enum gaudi_nic_mask {
 240        GAUDI_NIC_MASK_NIC0 = 0x01,
 241        GAUDI_NIC_MASK_NIC1 = 0x02,
 242        GAUDI_NIC_MASK_NIC2 = 0x04,
 243        GAUDI_NIC_MASK_NIC3 = 0x08,
 244        GAUDI_NIC_MASK_NIC4 = 0x10,
 245        GAUDI_NIC_MASK_NIC5 = 0x20,
 246        GAUDI_NIC_MASK_NIC6 = 0x40,
 247        GAUDI_NIC_MASK_NIC7 = 0x80,
 248        GAUDI_NIC_MASK_NIC8 = 0x100,
 249        GAUDI_NIC_MASK_NIC9 = 0x200,
 250        GAUDI_NIC_MASK_ALL = 0x3FF
 251};
 252
 253/*
 254 * struct gaudi_hw_sob_group - H/W SOB group info.
 255 * @hdev: habanalabs device structure.
 256 * @kref: refcount of this SOB group. group will reset once refcount is zero.
 257 * @base_sob_id: base sob id of this SOB group.
 258 * @queue_id: id of the queue that waits on this sob group
 259 */
 260struct gaudi_hw_sob_group {
 261        struct hl_device        *hdev;
 262        struct kref             kref;
 263        u32                     base_sob_id;
 264        u32                     queue_id;
 265};
 266
 267#define NUM_SOB_GROUPS (HL_RSVD_SOBS * QMAN_STREAMS)
 268/**
 269 * struct gaudi_collective_properties -
 270 *     holds all SOB groups and queues info reserved for the collective
 271 * @hw_sob_group: H/W SOB groups.
 272 * @next_sob_group_val: the next value to use for the currently used SOB group.
 273 * @curr_sob_group_idx: the index of the currently used SOB group.
 274 * @mstr_sob_mask: pre-defined masks for collective master monitors
 275 */
 276struct gaudi_collective_properties {
 277        struct gaudi_hw_sob_group hw_sob_group[NUM_SOB_GROUPS];
 278        u16                     next_sob_group_val[QMAN_STREAMS];
 279        u8                      curr_sob_group_idx[QMAN_STREAMS];
 280        u8                      mstr_sob_mask[HL_COLLECTIVE_RSVD_MSTR_MONS];
 281};
 282
 283/**
 284 * struct gaudi_internal_qman_info - Internal QMAN information.
 285 * @pq_kernel_addr: Kernel address of the PQ memory area in the host.
 286 * @pq_dma_addr: DMA address of the PQ memory area in the host.
 287 * @pq_size: Size of allocated host memory for PQ.
 288 */
 289struct gaudi_internal_qman_info {
 290        void            *pq_kernel_addr;
 291        dma_addr_t      pq_dma_addr;
 292        size_t          pq_size;
 293};
 294
 295/**
 296 * struct gaudi_device - ASIC specific manage structure.
 297 * @cpucp_info_get: get information on device from CPU-CP
 298 * @hw_queues_lock: protects the H/W queues from concurrent access.
 299 * @clk_gate_mutex: protects code areas that require clock gating to be disabled
 300 *                  temporarily
 301 * @internal_qmans: Internal QMANs information. The array size is larger than
 302 *                  the actual number of internal queues because they are not in
 303 *                  consecutive order.
 304 * @hbm_bar_cur_addr: current address of HBM PCI bar.
 305 * @max_freq_value: current max clk frequency.
 306 * @events: array that holds all event id's
 307 * @events_stat: array that holds histogram of all received events.
 308 * @events_stat_aggregate: same as events_stat but doesn't get cleared on reset
 309 * @hw_cap_initialized: This field contains a bit per H/W engine. When that
 310 *                      engine is initialized, that bit is set by the driver to
 311 *                      signal we can use this engine in later code paths.
 312 *                      Each bit is cleared upon reset of its corresponding H/W
 313 *                      engine.
 314 * @multi_msi_mode: whether we are working in multi MSI single MSI mode.
 315 *                  Multi MSI is possible only with IOMMU enabled.
 316 * @mmu_cache_inv_pi: PI for MMU cache invalidation flow. The H/W expects an
 317 *                    8-bit value so use u8.
 318 */
 319struct gaudi_device {
 320        int (*cpucp_info_get)(struct hl_device *hdev);
 321
 322        /* TODO: remove hw_queues_lock after moving to scheduler code */
 323        spinlock_t                      hw_queues_lock;
 324        struct mutex                    clk_gate_mutex;
 325
 326        struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
 327
 328        struct gaudi_collective_properties collective_props;
 329
 330        u64                             hbm_bar_cur_addr;
 331        u64                             max_freq_value;
 332
 333        u32                             events[GAUDI_EVENT_SIZE];
 334        u32                             events_stat[GAUDI_EVENT_SIZE];
 335        u32                             events_stat_aggregate[GAUDI_EVENT_SIZE];
 336        u32                             hw_cap_initialized;
 337        u8                              multi_msi_mode;
 338        u8                              mmu_cache_inv_pi;
 339};
 340
 341void gaudi_init_security(struct hl_device *hdev);
 342void gaudi_ack_protection_bits_errors(struct hl_device *hdev);
 343void gaudi_add_device_attr(struct hl_device *hdev,
 344                        struct attribute_group *dev_attr_grp);
 345void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
 346int gaudi_debug_coresight(struct hl_device *hdev, void *data);
 347void gaudi_halt_coresight(struct hl_device *hdev);
 348int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
 349void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);
 350
 351#endif /* GAUDIP_H_ */
 352